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SuperH (sh): Remove obsolete architecture

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Updates rtems/rtos/rtems#5022
This commit is contained in:
Joel Sherrill
2024-12-19 16:24:06 -06:00
committed by Kinsey Moore
parent 740f736f9e
commit 00b074b124
140 changed files with 0 additions and 17064 deletions
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59
bsps/sh/gensh1/README.md
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@@ -1,59 +0,0 @@
gensh1
======
Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
```
BSP NAME: generic SH1 (gensh1)
BOARD: n/a
BUS: n/a
CPU FAMILY: Hitachi SH
CPU: SH 7032
COPROCESSORS: none
MODE: n/a
DEBUG MONITOR: gdb
```
PERIPHERALS
-----------
```
TIMERS: on-chip
RESOLUTION: cf. Hitachi SH 703X Hardware Manual (Phi/4)
SERIAL PORTS: on-chip (with 2 ports)
REAL-TIME CLOCK: none
DMA: not used
VIDEO: none
SCSI: none
NETWORKING: none
```
DRIVER INFORMATION
------------------
```
CLOCK DRIVER: on-chip timer
IOSUPP DRIVER: default
SHMSUPP: default
TIMER DRIVER: on-chip timer
TTY DRIVER: /dev/null (stub)
```
STDIO
-----
```
PORT: /dev/null (stub)
ELECTRICAL: n/a
BAUD: n/a
BITS PER CHARACTER: n/a
PARITY: n/a
STOP BITS: n/a
```
NOTES
-----
(1) The stub console driver (null) is enabled by default.
(2) The driver for the on-chip serial devices (sci) is still in its infancy
and not fully tested. It may even be non-functional and therefore is
disabled by default. Please let us know any problems you encounter with
it.
To activate it edit libbsp/sh/gensh1/include/bsp.h

195
bsps/sh/gensh1/btimer/btimer.c
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@@ -1,195 +0,0 @@
/**
* @file
* @brief Timer for the Hitachi SH 703X
*/
/*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <rtems/btimer.h>
#include <rtems/score/sh_io.h>
#include <rtems/score/ispsh7032.h>
#include <rtems/score/iosh7032.h>
extern uint32_t bsp_clicks_per_second;
#define I_CLK_PHI_1 0
#define I_CLK_PHI_2 1
#define I_CLK_PHI_4 2
#define I_CLK_PHI_8 3
/*
* Set I_CLK_PHI to one of the I_CLK_PHI_X values from above to choose
* a PHI/X clock rate.
*/
#define I_CLK_PHI I_CLK_PHI_4
#define CLOCK_SCALE (1<<I_CLK_PHI)
#define ITU1_STARTMASK 0xfd
#define ITU1_SYNCMASK 0xfd
#define ITU1_MODEMASK 0xfd
#define ITU1_TCRMASK (0x00 | I_CLK_PHI)
#define ITU1_TIORMASK 0x88
#define ITU1_STAT_MASK 0xf8
#define ITU1_TIERMASK 0xfc
#define IPRC_ITU1_MASK 0xfff0
#ifndef ITU1_PRIO
#define ITU1_PRIO 15
#endif
#define ITU1_VECTOR OVI1_ISP_V
extern rtems_isr timerisr(void);
static uint32_t Timer_interrupts;
bool benchmark_timer_find_average_overhead;
static uint32_t Timer_HZ ;
void benchmark_timer_initialize( void )
{
uint8_t temp8;
uint16_t temp16;
rtems_interrupt_level level;
rtems_isr *ignored;
Timer_HZ = bsp_clicks_per_second / CLOCK_SCALE ;
/*
* Timer has never overflowed. This may not be necessary on some
* implemenations of timer but ....
*/
Timer_interrupts /* .i */ = 0;
rtems_interrupt_disable( level );
/*
* Somehow start the timer
*/
/* stop Timer 1 */
temp8 = read8(ITU_TSTR) & ITU1_STARTMASK;
write8( temp8, ITU_TSTR );
/* initialize counter 1 */
write16( 0, ITU_TCNT1 );
/* Timer 1 is independent of other timers */
temp8 = read8(ITU_TSNC) & ITU1_SYNCMASK;
write8( temp8, ITU_TSNC );
/* Timer 1, normal mode */
temp8 = read8(ITU_TMDR) & ITU1_MODEMASK;
write8( temp8, ITU_TMDR );
/* Use a Phi/X counter */
write8( ITU1_TCRMASK, ITU_TCR1 );
/* gra and grb are not used */
write8( ITU1_TIORMASK, ITU_TIOR1 );
/* reset all status flags */
temp8 = read8(ITU_TSR1) & ITU1_STAT_MASK;
write8( temp8, ITU_TSR1 );
/* enable overflow interrupt */
write8( ITU1_TIERMASK, ITU_TIER1 );
/* set interrupt priority */
temp16 = read16(INTC_IPRC) & IPRC_ITU1_MASK;
temp16 |= ITU1_PRIO;
write16( temp16, INTC_IPRC );
/* initialize ISR */
_CPU_ISR_install_raw_handler( ITU1_VECTOR, timerisr, &ignored );
rtems_interrupt_enable( level );
/* start timer 1 */
temp8 = read8(ITU_TSTR) | ~ITU1_STARTMASK;
write8( temp8, ITU_TSTR );
}
/*
* The following controls the behavior of benchmark_timer_read().
*
* AVG_OVERHEAD is the overhead for starting and stopping the timer. It
* is usually deducted from the number returned.
*
* LEAST_VALID is the lowest number this routine should trust. Numbers
* below this are "noise" and zero is returned.
*/
#define AVG_OVERHEAD 1 /* It typically takes X.X microseconds */
/* (Y countdowns) to start/stop the timer. */
/* This value is in microseconds. */
#define LEAST_VALID 0 /* 20 */ /* Don't trust a clicks value lower than this */
benchmark_timer_t benchmark_timer_read( void )
{
uint32_t cclicks;
uint32_t total ;
/*
* Read the timer and see how many clicks it has been since we started.
*/
cclicks = read16( ITU_TCNT1 ); /* XXX: read some HW here */
/*
* Total is calculated by taking into account the number of timer overflow
* interrupts since the timer was initialized and clicks since the last
* interrupts.
*/
total = cclicks + Timer_interrupts * 65536;
if ( benchmark_timer_find_average_overhead )
return total / CLOCK_SCALE; /* in XXX microsecond units */
else
{
if ( total < LEAST_VALID )
return 0; /* below timer resolution */
/*
* Somehow convert total into microseconds
*/
return (total / CLOCK_SCALE - AVG_OVERHEAD);
}
}
void benchmark_timer_disable_subtracting_average_overhead(bool find_flag)
{
benchmark_timer_find_average_overhead = find_flag;
}
/* Timer 1 is used */
#pragma interrupt
void timerisr( void )
{
uint8_t temp8;
/* reset the flags of the status register */
temp8 = read8(ITU_TSR1) & ITU1_STAT_MASK;
write8( temp8, ITU_TSR1 );
Timer_interrupts += 1;
}

294
bsps/sh/gensh1/clock/ckinit.c
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/*
* This file contains the clock driver the Hitachi SH 703X
*/
/*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <stdlib.h>
#include <rtems/clockdrv.h>
#include <rtems/score/sh_io.h>
#include <rtems/score/sh.h>
#include <rtems/score/ispsh7032.h>
#include <rtems/score/iosh7032.h>
extern uint32_t bsp_clicks_per_second;
#ifndef CLOCKPRIO
#define CLOCKPRIO 10
#endif
#define I_CLK_PHI_1 0
#define I_CLK_PHI_2 1
#define I_CLK_PHI_4 2
#define I_CLK_PHI_8 3
/*
* Set I_CLK_PHI to one of the I_CLK_PHI_X values from above to choose
* a PHI/X clock rate.
*/
#define I_CLK_PHI I_CLK_PHI_4
#define CLOCK_SCALE (1<<I_CLK_PHI)
#define ITU0_STARTMASK 0xfe
#define ITU0_SYNCMASK 0xfe
#define ITU0_MODEMASK 0xfe
#define ITU0_TCRMASK (0x20 | I_CLK_PHI)
#define ITU_STAT_MASK 0xf8
#define ITU0_IRQMASK 0xfe
#define ITU0_TIERMASK 0x01
#define IPRC_ITU0_MASK 0xff0f
#define ITU0_TIORVAL 0x08
/*
* clicks_per_tick := clicks_per_sec * usec_per_tick
*
* This is a very expensive function ;-)
*
* Below are two variants:
* 1. A variant applying integer arithmetics, only.
* 2. A variant applying floating point arithmetics
*
* The floating point variant pulls in the fmath routines when linking,
* resulting in slightly larger executables for applications that do not
* apply fmath otherwise. However, the imath variant is significantly slower
* than the fmath variant and more complex.
*
* Assuming that most applications will not use fmath, but are critical
* in memory size constraints, we apply the integer variant.
*
* To the sake of simplicity, we might abandon one of both variants in
* future.
*/
static unsigned int sh_clicks_per_tick(
unsigned int clicks_per_sec,
unsigned int usec_per_tick
)
{
#if 1
unsigned int clicks_per_tick = 0 ;
unsigned int b = clicks_per_sec ;
unsigned int c = 1000000 ;
unsigned int d = 1 ;
unsigned int a = ( ( b / c ) * usec_per_tick ) / d;
clicks_per_tick += a ;
while ( ( b %= c ) > 0 )
{
c /= 10 ;
d *= 10 ;
a = ( ( b / c ) * usec_per_tick ) / d ;
clicks_per_tick += a ;
}
return clicks_per_tick ;
#else
double fclicks_per_tick =
((double) clicks_per_sec * (double) usec_per_tick) / 1000000.0 ;
return (uint32_t) fclicks_per_tick ;
#endif
}
/*
* The interrupt vector number associated with the clock tick device
* driver.
*/
#define CLOCK_VECTOR IMIA0_ISP_V
/*
* Clock_driver_ticks is a monotonically increasing counter of the
* number of clock ticks since the driver was initialized.
*/
volatile uint32_t Clock_driver_ticks;
static void Clock_exit( void );
static rtems_isr Clock_isr( rtems_vector_number vector );
/*
* Clock_isrs is the number of clock ISRs until the next invocation of
* the RTEMS clock tick routine. The clock tick device driver
* gets an interrupt once a millisecond and counts down until the
* length of time between the user configured microseconds per tick
* has passed.
*/
uint32_t Clock_isrs; /* ISRs until next tick */
static uint32_t Clock_isrs_const; /* only calculated once */
/*
* The previous ISR on this clock tick interrupt vector.
*/
rtems_isr_entry Old_ticker;
/*
* Isr Handler
*/
static rtems_isr Clock_isr(
rtems_vector_number vector
)
{
/*
* bump the number of clock driver ticks since initialization
*
* determine if it is time to announce the passing of tick as configured
* to RTEMS through the rtems_clock_tick directive
*
* perform any timer dependent tasks
*/
uint8_t temp;
/* reset the flags of the status register */
temp = read8( ITU_TSR0) & ITU_STAT_MASK;
write8( temp, ITU_TSR0);
Clock_driver_ticks++ ;
if( Clock_isrs == 1)
{
rtems_clock_tick();
Clock_isrs = Clock_isrs_const;
}
else
{
Clock_isrs-- ;
}
}
/*
* Install_clock
*
* Install a clock tick handler and reprograms the chip. This
* is used to initially establish the clock tick.
*/
static void Install_clock(
rtems_isr_entry clock_isr
)
{
uint8_t temp8 = 0;
uint32_t microseconds_per_tick;
uint32_t cclicks_per_tick;
uint16_t Clock_limit;
/*
* Initialize the clock tick device driver variables
*/
Clock_driver_ticks = 0;
if ( rtems_configuration_get_microseconds_per_tick() != 0 )
microseconds_per_tick = rtems_configuration_get_microseconds_per_tick() ;
else
microseconds_per_tick = 10000 ; /* 10000 us */
/* clock clicks per tick */
cclicks_per_tick = sh_clicks_per_tick(
bsp_clicks_per_second / CLOCK_SCALE, microseconds_per_tick );
Clock_isrs_const = cclicks_per_tick >> 16 ;
if ( ( cclicks_per_tick | 0xffff ) > 0 )
Clock_isrs_const++ ;
Clock_limit = cclicks_per_tick / Clock_isrs_const ;
Clock_isrs = Clock_isrs_const;
rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker );
/*
* Hardware specific initialize goes here
*/
/* stop Timer 0 */
temp8 = read8( ITU_TSTR) & ITU0_STARTMASK;
write8( temp8, ITU_TSTR);
/* set initial counter value to 0 */
write16( 0, ITU_TCNT0);
/* Timer 0 runs independent */
temp8 = read8( ITU_TSNC) & ITU0_SYNCMASK;
write8( temp8, ITU_TSNC);
/* Timer 0 normal mode */
temp8 = read8( ITU_TMDR) & ITU0_MODEMASK;
write8( temp8, ITU_TMDR);
/* TCNT is cleared by GRA ; internal clock /4 */
write8( ITU0_TCRMASK , ITU_TCR0);
/* use GRA without I/O - pins */
write8( ITU0_TIORVAL, ITU_TIOR0);
/* reset flags of the status register */
temp8 = read8( ITU_TSR0) & ITU_STAT_MASK;
write8( temp8, ITU_TSR0);
/* Irq if is equal GRA */
temp8 = read8( ITU_TIER0) | ITU0_TIERMASK;
write8( temp8, ITU_TIER0);
/* set interrupt priority */
if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
/* set counter limits */
write16( Clock_limit, ITU_GRA0);
/* start counter */
temp8 = read8( ITU_TSTR) |~ITU0_STARTMASK;
write8( temp8, ITU_TSTR);
/*
* Schedule the clock cleanup routine to execute if the application exits.
*/
atexit( Clock_exit );
}
/*
* Clean up before the application exits
*/
void Clock_exit( void )
{
uint8_t temp8 = 0;
/* turn off the timer interrupts */
/* set interrupt priority to 0 */
if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred( RTEMS_UNSATISFIED);
/*
* temp16 = read16( ITU_TIER0) & IPRC_ITU0_IRQMASK;
* write16( temp16, ITU_TIER0);
*/
/* stop counter */
temp8 = read8( ITU_TSTR) & ITU0_STARTMASK;
write8( temp8, ITU_TSTR);
/* old vector shall not be installed */
}
void _Clock_Initialize( void )
{
Install_clock( Clock_isr );
}

51
bsps/sh/gensh1/clock/delay.c
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@@ -1,51 +0,0 @@
/*
* This routine is a simple spin delay
*
* Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1999, Ralf Corsepius, Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
extern uint32_t bsp_clicks_per_second;
/*
* Simple spin delay in microsecond units for device drivers.
* This is very dependent on the clock speed of the target.
*
* Since we don't have a real time clock, this is a very rough
* approximation, assuming that each cycle of the delay loop takes
* approx. 4 machine cycles.
*
* e.g.: clicks_per_second = 20MHz
* => 5e-8 secs per instruction
* => 4 * 5e-8 secs per delay loop
*/
void CPU_delay( uint32_t microseconds )
{
register uint32_t clicks_per_usec = bsp_clicks_per_second / 1000000;
register uint32_t _delay = (microseconds) * (clicks_per_usec);
__asm__ volatile (
"0: add #-4,%0\n\
nop\n\
cmp/pl %0\n\
bt 0b\n\
nop"
:: "r" (_delay) );
}

13
bsps/sh/gensh1/config/gensh1-testsuite.tcfg
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@@ -1,13 +0,0 @@
#
# gensh1 RTEMS Test Database.
#
# Format is one line per test that is _NOT_ built.
#
include: testdata/disable-iconv-tests.tcfg
exclude: fileio
exclude: fsdosfsname01
exclude: iostream
exclude: linpack
exclude: record02
exclude: utf8proc01

22
bsps/sh/gensh1/config/gensh1.cfg
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@@ -1,22 +0,0 @@
#
# gensh1.cfg
#
# default configuration for Hitachi sh1 processors
#
# Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
#
include $(RTEMS_ROOT)/make/custom/default.cfg
RTEMS_CPU=sh
# This contains the compiler options necessary to select the CPU model
# and (hopefully) optimize for it.
#
CPU_CFLAGS = -m1
# optimize flag: typically -O2
CFLAGS_OPTIMIZE_V = -O2 -g
CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections
LDFLAGS = -Wl,--gc-sections

352
bsps/sh/gensh1/console/sci.c
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@@ -1,352 +0,0 @@
/*
* /dev/sci[0|1] for Hitachi SH 703X
*
* Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1999, Ralf Corsepius, Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp.h>
#include <stdlib.h>
#include <rtems/libio.h>
#include <rtems/iosupp.h>
#include <rtems/score/sh_io.h>
#include <rtems/score/ispsh7032.h>
#include <rtems/score/iosh7032.h>
#include <sh/sh7_sci.h>
#include <sh/sh7_pfc.h>
#include <sh/sci.h>
/*
* NOTE: Some SH variants have 3 sci devices
*/
#define SCI_MINOR_DEVICES 2
#define SH_SCI_BASE_0 SCI0_SMR
#define SH_SCI_BASE_1 SCI1_SMR
struct scidev_t {
char * name ;
uint32_t addr ;
rtems_device_minor_number minor ;
unsigned short opened ;
tcflag_t cflags ;
speed_t spd ;
} sci_device[SCI_MINOR_DEVICES] =
{
{ "/dev/sci0", SH_SCI_BASE_0, 0, 0, CS8, B9600 },
{ "/dev/sci1", SH_SCI_BASE_1, 1, 0, CS8, B9600 }
} ;
/* Translate termios' tcflag_t into sci settings */
static int _sci_set_cflags(
struct scidev_t *sci_dev,
tcflag_t c_cflag,
speed_t spd )
{
uint8_t smr ;
uint8_t brr ;
if ( spd )
{
if ( _sci_get_brparms( spd, &smr, &brr ) != 0 )
return -1 ;
}
if ( c_cflag & CSIZE )
{
if ( c_cflag & CS8 )
smr &= ~SCI_SEVEN_BIT_DATA;
else if ( c_cflag & CS7 )
smr |= SCI_SEVEN_BIT_DATA;
else
return -1 ;
}
if ( c_cflag & CSTOPB )
smr |= SCI_STOP_BITS_2;
else
smr &= ~SCI_STOP_BITS_2;
if ( c_cflag & PARENB )
smr |= SCI_PARITY_ON ;
else
smr &= ~SCI_PARITY_ON ;
if ( c_cflag & PARODD )
smr |= SCI_ODD_PARITY ;
else
smr &= ~SCI_ODD_PARITY;
write8( smr, sci_dev->addr + SCI_SMR );
write8( brr, sci_dev->addr + SCI_BRR );
return 0 ;
}
static void _sci_init(
rtems_device_minor_number minor )
{
uint16_t temp16 ;
/* Pin function controller initialisation for asynchronous mode */
if( minor == 0)
{
temp16 = read16( PFC_PBCR1);
temp16 &= ~( PB8MD | PB9MD );
temp16 |= (PB_TXD0 | PB_RXD0);
write16( temp16, PFC_PBCR1);
}
else
{
temp16 = read16( PFC_PBCR1);
temp16 &= ~( PB10MD | PB11MD);
temp16 |= (PB_TXD1 | PB_RXD1);
write16( temp16, PFC_PBCR1);
}
/* disable sck-pin */
if( minor == 0)
{
temp16 = read16( PFC_PBCR1);
temp16 &= ~(PB12MD);
write16( temp16, PFC_PBCR1);
}
else
{
temp16 = read16( PFC_PBCR1);
temp16 &= ~(PB13MD);
write16( temp16, PFC_PBCR1);
}
}
static void _sci_tx_polled(
int minor,
const char buf )
{
struct scidev_t *scidev = &sci_device[minor] ;
int8_t ssr ;
while ( !inb((scidev->addr + SCI_SSR) & SCI_TDRE ))
;
write8(buf,scidev->addr+SCI_TDR);
ssr = inb(scidev->addr+SCI_SSR);
ssr &= ~SCI_TDRE ;
write8(ssr,scidev->addr+SCI_SSR);
}
static int _sci_rx_polled (
int minor)
{
struct scidev_t *scidev = &sci_device[minor] ;
unsigned char c;
char ssr ;
ssr = read8(scidev->addr + SCI_SSR) ;
if (ssr & (SCI_PER | SCI_FER | SCI_ORER))
write8(ssr & ~(SCI_PER | SCI_FER | SCI_ORER), scidev->addr+SCI_SSR);
if ( !(ssr & SCI_RDRF) )
return -1;
c = read8(scidev->addr + SCI_RDR) ;
write8(ssr & ~SCI_RDRF,scidev->addr + SCI_SSR);
return c;
}
/*
* sci_initialize
*/
rtems_device_driver sh_sci_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *arg )
{
rtems_device_driver status ;
rtems_device_minor_number i;
/*
* register all possible devices.
* the initialization of the hardware is done by sci_open
*/
for ( i = 0 ; i < SCI_MINOR_DEVICES ; i++ )
{
status = rtems_io_register_name(
sci_device[i].name,
major,
sci_device[i].minor );
if (status != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred(status);
}
/* default hardware setup */
return RTEMS_SUCCESSFUL;
}
/*
* Open entry point
*/
rtems_device_driver sh_sci_open(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg )
{
uint8_t temp8;
/* check for valid minor number */
if(( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 ))
{
return RTEMS_INVALID_NUMBER;
}
/* device already opened */
if ( sci_device[minor].opened > 0 )
{
sci_device[minor].opened++ ;
return RTEMS_SUCCESSFUL ;
}
_sci_init( minor );
if (minor == 0) {
temp8 = read8(sci_device[minor].addr + SCI_SCR);
temp8 &= ~(SCI_TE | SCI_RE) ;
write8(temp8, sci_device[minor].addr + SCI_SCR); /* Clear SCR */
_sci_set_cflags( &sci_device[minor], sci_device[minor].cflags, sci_device[minor].spd );
/* FIXME: Should be one bit delay */
CPU_delay(50000); /* microseconds */
temp8 |= SCI_RE | SCI_TE;
write8(temp8, sci_device[minor].addr + SCI_SCR); /* Enable clock output */
} else {
temp8 = read8(sci_device[minor].addr + SCI_SCR);
temp8 &= ~(SCI_TE | SCI_RE) ;
write8(temp8, sci_device[minor].addr + SCI_SCR); /* Clear SCR */
_sci_set_cflags( &sci_device[minor], sci_device[minor].cflags, sci_device[minor].spd );
/* FIXME: Should be one bit delay */
CPU_delay(50000); /* microseconds */
temp8 |= SCI_RE | SCI_TE;
write8(temp8, sci_device[minor].addr + SCI_SCR); /* Enable clock output */
}
sci_device[minor].opened++ ;
return RTEMS_SUCCESSFUL ;
}
/*
* Close entry point
*/
rtems_device_driver sh_sci_close(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
if( sci_device[minor].opened == 0 )
{
return RTEMS_INVALID_NUMBER;
}
sci_device[minor].opened-- ;
return RTEMS_SUCCESSFUL ;
}
/*
* read bytes from the serial port.
*/
rtems_device_driver sh_sci_read(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
int count = 0;
rtems_libio_rw_args_t *rw_args = (rtems_libio_rw_args_t *) arg;
char * buffer = rw_args->buffer;
int maximum = rw_args->count;
for (count = 0; count < maximum; count++) {
buffer[ count ] = _sci_rx_polled(minor);
if (buffer[ count ] == '\n' || buffer[ count ] == '\r') {
buffer[ count++ ] = '\n';
break;
}
}
rw_args->bytes_moved = count;
return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED;
}
/*
* write bytes to the serial port.
*/
rtems_device_driver sh_sci_write(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
int count;
rtems_libio_rw_args_t *rw_args = (rtems_libio_rw_args_t *) arg;
char *buffer = rw_args->buffer;
int maximum = rw_args->count;
for (count = 0; count < maximum; count++) {
#if 0
if ( buffer[ count ] == '\n') {
outbyte(minor, '\r');
}
#endif
_sci_tx_polled( minor, buffer[ count ] );
}
rw_args->bytes_moved = maximum;
return 0;
}
/*
* IO Control entry point
*/
rtems_device_driver sh_sci_control(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
/* Not yet supported */
return RTEMS_SUCCESSFUL ;
}

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bsps/sh/gensh1/console/scitab.c
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@@ -1,51 +0,0 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (c) 2018 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* The content of this file was previously generated by the GPL licensed shgen
* tool during the BSP build for a configured clock frequency
* (CPU_CLOCK_RATE_HZ). All tools were removed from the RTEMS source repository
* at some point in time. Tools with a BSD-style license were moved to the
* RTEMS tools repository.
*/
#include <bsp.h>
int _sci_get_brparms(
unsigned int spd,
unsigned char *smr,
unsigned char *brr
)
{
if (spd != 9600) {
return -1;
}
*smr = 0x00;
*brr = 0x40;
return 0;
}

86
bsps/sh/gensh1/include/bsp.h
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@@ -1,86 +0,0 @@
/**
* @file
*
* @ingroup RTEMSBSPsSH1
*
* @brief Global BSP definitions.
*/
/*
* generic sh1
*
* This include file contains all board IO definitions.
*/
/*
* Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef LIBBSP_SH_GENSH1_BSP_H
#define LIBBSP_SH_GENSH1_BSP_H
/**
* @defgroup RTEMSBSPsSH1 SH-1
*
* @ingroup RTEMSBSPsSH
*
* @brief SH-1 Board Support Package.
*
* @{
*/
#include <rtems.h>
#include <termios.h> /* for tcflag_t */
#include <bspopts.h>
#include <bsp/default-initial-extension.h>
#ifdef __cplusplus
extern "C" {
#endif
/* EDIT: To activate the sci driver, change the define below */
#if 1
#include <rtems/devnull.h>
#define BSP_CONSOLE_DEVNAME "/dev/null"
#define BSP_CONSOLE_DRIVER_TABLE_ENTRY DEVNULL_DRIVER_TABLE_ENTRY
#else
#include <sh/sci.h>
#define BSP_CONSOLE_DEVNAME "/dev/sci0"
#define BSP_CONSOLE_DRIVER_TABLE_ENTRY DEVSCI_DRIVER_TABLE_ENTRY
#endif
/* Constants */
/*
* BSP methods that cross file boundaries.
*/
void bsp_hw_init(void);
int _sci_get_brparms(
unsigned int spd,
unsigned char *smr,
unsigned char *brr
);
#ifdef __cplusplus
}
#endif
/** @} */
#endif

1
bsps/sh/gensh1/include/bsp/irq.h
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@@ -1 +0,0 @@
#include <bsp/irq-default.h>

220
bsps/sh/gensh1/include/rtems/score/iosh7032.h
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@@ -1,220 +0,0 @@
/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
* contained no copyright notice.
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef __IOSH7030_H
#define __IOSH7030_H
/*
* After each line is explained whether the access is char short or long.
* The functions read/writeb, w, l, 8, 16, 32 can be found
* in exec/score/cpu/sh/sh_io.h
*
* 8 bit == char ( readb, writeb, read8, write8)
* 16 bit == short ( readw, writew, read16, write16 )
* 32 bit == long ( readl, writel, read32, write32 )
*/
#define SCI0_SMR 0x05fffec0 /* char */
#define SCI0_BRR 0x05fffec1 /* char */
#define SCI0_SCR 0x05fffec2 /* char */
#define SCI0_TDR 0x05fffec3 /* char */
#define SCI0_SSR 0x05fffec4 /* char */
#define SCI0_RDR 0x05fffec5 /* char */
#define SCI1_SMR 0x05fffec8 /* char */
#define SCI1_BRR 0x05fffec9 /* char */
#define SCI1_SCR 0x05fffeca /* char */
#define SCI1_TDR 0x05fffecb /* char */
#define SCI1_SSR 0x05fffecc /* char */
#define SCI1_RDR 0x05fffecd /* char */
#define ADDRAH 0x05fffee0 /* char */
#define ADDRAL 0x05fffee1 /* char */
#define ADDRBH 0x05fffee2 /* char */
#define ADDRBL 0x05fffee3 /* char */
#define ADDRCH 0x05fffee4 /* char */
#define ADDRCL 0x05fffee5 /* char */
#define ADDRDH 0x05fffee6 /* char */
#define ADDRDL 0x05fffee7 /* char */
#define AD_DRA 0x05fffee0 /* short */
#define AD_DRB 0x05fffee2 /* short */
#define AD_DRC 0x05fffee4 /* short */
#define AD_DRD 0x05fffee6 /* short */
#define ADCSR 0x05fffee8 /* char */
#define ADCR 0x05fffee9 /* char */
/*ITU SHARED*/
#define ITU_TSTR 0x05ffff00 /* char */
#define ITU_TSNC 0x05ffff01 /* char */
#define ITU_TMDR 0x05ffff02 /* char */
#define ITU_TFCR 0x05ffff03 /* char */
/*ITU CHANNEL 0*/
#define ITU_TCR0 0x05ffff04 /* char */
#define ITU_TIOR0 0x05ffff05 /* char */
#define ITU_TIER0 0x05ffff06 /* char */
#define ITU_TSR0 0x05ffff07 /* char */
#define ITU_TCNT0 0x05ffff08 /* short */
#define ITU_GRA0 0x05ffff0a /* short */
#define ITU_GRB0 0x05ffff0c /* short */
/*ITU CHANNEL 1*/
#define ITU_TCR1 0x05ffff0E /* char */
#define ITU_TIOR1 0x05ffff0F /* char */
#define ITU_TIER1 0x05ffff10 /* char */
#define ITU_TSR1 0x05ffff11 /* char */
#define ITU_TCNT1 0x05ffff12 /* short */
#define ITU_GRA1 0x05ffff14 /* short */
#define ITU_GRB1 0x05ffff16 /* short */
/*ITU CHANNEL 2*/
#define ITU_TCR2 0x05ffff18 /* char */
#define ITU_TIOR2 0x05ffff19 /* char */
#define ITU_TIER2 0x05ffff1A /* char */
#define ITU_TSR2 0x05ffff1B /* char */
#define ITU_TCNT2 0x05ffff1C /* short */
#define ITU_GRA2 0x05ffff1E /* short */
#define ITU_GRB2 0x05ffff20 /* short */
/*ITU CHANNEL 3*/
#define ITU_TCR3 0x05ffff22 /* char */
#define ITU_TIOR3 0x05ffff23 /* char */
#define ITU_TIER3 0x05ffff24 /* char */
#define ITU_TSR3 0x05ffff25 /* char */
#define ITU_TCNT3 0x05ffff26 /* short */
#define ITU_GRA3 0x05ffff28 /* short */
#define ITU_GRB3 0x05ffff2A /* short */
#define ITU_BRA3 0x05ffff2C /* short */
#define ITU_BRB3 0x05ffff2E /* short */
/*ITU CHANNELS 0-4 SHARED*/
#define ITU_TOCR 0x05ffff31 /* char */
/*ITU CHANNEL 4*/
#define ITU_TCR4 0x05ffff32 /* char */
#define ITU_TIOR4 0x05ffff33 /* char */
#define ITU_TIER4 0x05ffff34 /* char */
#define ITU_TSR4 0x05ffff35 /* char */
#define ITU_TCNT4 0x05ffff36 /* short */
#define ITU_GRA4 0x05ffff38 /* short */
#define ITU_GRB4 0x05ffff3A /* short */
#define ITU_BRA4 0x05ffff3C /* short */
#define ITU_BRB4 0x05ffff3E /* short */
/*DMAC CHANNELS 0-3 SHARED*/
#define DMAOR 0x05ffff48 /* short */
/*DMAC CHANNEL 0*/
#define DMA_SAR0 0x05ffff40 /* long */
#define DMA_DAR0 0x05ffff44 /* long */
#define DMA_TCR0 0x05ffff4a /* short */
#define DMA_CHCR0 0x05ffff4e /* short */
/*DMAC CHANNEL 1*/
#define DMA_SAR1 0x05ffff50 /* long */
#define DMA_DAR1 0x05ffff54 /* long */
#define DMA_TCR1 0x05fffF5a /* short */
#define DMA_CHCR1 0x05ffff5e /* short */
/*DMAC CHANNEL 3*/
#define DMA_SAR3 0x05ffff60 /* long */
#define DMA_DAR3 0x05ffff64 /* long */
#define DMA_TCR3 0x05fffF6a /* short */
#define DMA_CHCR3 0x05ffff6e /* short */
/*DMAC CHANNEL 4*/
#define DMA_SAR4 0x05ffff70 /* long */
#define DMA_DAR4 0x05ffff74 /* long */
#define DMA_TCR4 0x05fffF7a /* short */
#define DMA_CHCR4 0x05ffff7e /* short */
/*INTC*/
#define INTC_IPRA 0x05ffff84 /* short */
#define INTC_IPRB 0x05ffff86 /* short */
#define INTC_IPRC 0x05ffff88 /* short */
#define INTC_IPRD 0x05ffff8A /* short */
#define INTC_IPRE 0x05ffff8C /* short */
#define INTC_ICR 0x05ffff8E /* short */
/*UBC*/
#define UBC_BARH 0x05ffff90 /* short */
#define UBC_BARL 0x05ffff92 /* short */
#define UBC_BAMRH 0x05ffff94 /* short */
#define UBC_BAMRL 0x05ffff96 /* short */
#define UBC_BBR 0x05ffff98 /* short */
/*BSC*/
#define BSC_BCR 0x05ffffA0 /* short */
#define BSC_WCR1 0x05ffffA2 /* short */
#define BSC_WCR2 0x05ffffA4 /* short */
#define BSC_WCR3 0x05ffffA6 /* short */
#define BSC_DCR 0x05ffffA8 /* short */
#define BSC_PCR 0x05ffffAA /* short */
#define BSC_RCR 0x05ffffAC /* short */
#define BSC_RTCSR 0x05ffffAE /* short */
#define BSC_RTCNT 0x05ffffB0 /* short */
#define BSC_RTCOR 0x05ffffB2 /* short */
/*WDT*/
#define WDT_TCSR 0x05ffffB8 /* char */
#define WDT_TCNT 0x05ffffB9 /* char */
#define WDT_RSTCSR 0x05ffffBB /* char */
/*POWER DOWN STATE*/
#define PDT_SBYCR 0x05ffffBC /* char */
/*PORT A*/
#define PADR 0x05ffffC0 /* short */
/*PORT B*/
#define PBDR 0x05ffffC2 /* short */
/*PORT C*/
#define PCDR 0x05ffffD0 /* short */
/*PFC*/
#define PFC_PAIOR 0x05ffffC4 /* short */
#define PFC_PBIOR 0x05ffffC6 /* short */
#define PFC_PACR1 0x05ffffC8 /* short */
#define PFC_PACR2 0x05ffffCA /* short */
#define PFC_PBCR1 0x05ffffCC /* short */
#define PFC_PBCR2 0x05ffffCE /* short */
#define PFC_CASCR 0x05ffffEE /* short */
/*TPC*/
#define TPC_TPMR 0x05ffffF0 /* short */
#define TPC_TPCR 0x05ffffF1 /* short */
#define TPC_NDERH 0x05ffffF2 /* short */
#define TPC_NDERL 0x05ffffF3 /* short */
#define TPC_NDRB 0x05ffffF4 /* char */
#define TPC_NDRA 0x05ffffF5 /* char */
#define TPC_NDRB1 0x05ffffF6 /* char */
#define TPC_NDRA1 0x05ffffF7 /* char */
#endif

160
bsps/sh/gensh1/include/rtems/score/ispsh7032.h
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@@ -1,160 +0,0 @@
/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef __CPU_ISPS_H
#define __CPU_ISPS_H
#ifdef __cplusplus
extern "C" {
#endif
extern void __ISR_Handler( uint32_t vector );
/*
* interrupt vector table offsets
*/
#define NMI_ISP_V 11
#define USB_ISP_V 12
#define IRQ0_ISP_V 64
#define IRQ1_ISP_V 65
#define IRQ2_ISP_V 66
#define IRQ3_ISP_V 67
#define IRQ4_ISP_V 68
#define IRQ5_ISP_V 69
#define IRQ6_ISP_V 70
#define IRQ7_ISP_V 71
#define DMA0_ISP_V 72
#define DMA1_ISP_V 74
#define DMA2_ISP_V 76
#define DMA3_ISP_V 78
#define IMIA0_ISP_V 80
#define IMIB0_ISP_V 81
#define OVI0_ISP_V 82
#define IMIA1_ISP_V 84
#define IMIB1_ISP_V 85
#define OVI1_ISP_V 86
#define IMIA2_ISP_V 88
#define IMIB2_ISP_V 89
#define OVI2_ISP_V 90
#define IMIA3_ISP_V 92
#define IMIB3_ISP_V 93
#define OVI3_ISP_V 94
#define IMIA4_ISP_V 96
#define IMIB4_ISP_V 97
#define OVI4_ISP_V 98
#define ERI0_ISP_V 100
#define RXI0_ISP_V 101
#define TXI0_ISP_V 102
#define TEI0_ISP_V 103
#define ERI1_ISP_V 104
#define RXI1_ISP_V 105
#define TXI1_ISP_V 106
#define TEI1_ISP_V 107
#define PRT_ISP_V 108
#define ADU_ISP_V 109
#define WDT_ISP_V 112
#define DREF_ISP_V 113
/* dummy ISP */
extern void _dummy_isp( void );
/* Non Maskable Interrupt */
extern void _nmi_isp( void );
/* User Break Controller */
extern void _usb_isp( void );
/* External interrupts 0-7 */
extern void _irq0_isp( void );
extern void _irq1_isp( void );
extern void _irq2_isp( void );
extern void _irq3_isp( void );
extern void _irq4_isp( void );
extern void _irq5_isp( void );
extern void _irq6_isp( void );
extern void _irq7_isp( void );
/* DMA - Controller */
extern void _dma0_isp( void );
extern void _dma1_isp( void );
extern void _dma2_isp( void );
extern void _dma3_isp( void );
/* Interrupt Timer Unit */
/* Timer 0 */
extern void _imia0_isp( void );
extern void _imib0_isp( void );
extern void _ovi0_isp( void );
/* Timer 1 */
extern void _imia1_isp( void );
extern void _imib1_isp( void );
extern void _ovi1_isp( void );
/* Timer 2 */
extern void _imia2_isp( void );
extern void _imib2_isp( void );
extern void _ovi2_isp( void );
/* Timer 3 */
extern void _imia3_isp( void );
extern void _imib3_isp( void );
extern void _ovi3_isp( void );
/* Timer 4 */
extern void _imia4_isp( void );
extern void _imib4_isp( void );
extern void _ovi4_isp( void );
/* seriell interfaces */
extern void _eri0_isp( void );
extern void _rxi0_isp( void );
extern void _txi0_isp( void );
extern void _tei0_isp( void );
extern void _eri1_isp( void );
extern void _rxi1_isp( void );
extern void _txi1_isp( void );
extern void _tei1_isp( void );
/* Parity Control Unit of the Bus State Controllers */
extern void _prt_isp( void );
/* ADC */
extern void _adu_isp( void );
/* Watchdog Timer */
extern void _wdt_isp( void );
/* DRAM refresh control unit of bus state controller */
extern void _dref_isp( void );
#ifdef __cplusplus
}
#endif
#endif

82
bsps/sh/gensh1/include/sh/sci.h
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@@ -1,82 +0,0 @@
/*
* Driver for the sh1 703x on-chip serial devices (sci)
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef _sh_sci_h
#define _sh_sci_h
#ifdef __cplusplus
extern "C" {
#endif
/*
* Devices are set to 9600 bps, 8 databits, 1 stopbit, no
* parity and asynchronous mode by default.
*
* NOTE:
* The onboard serial devices of the SH do not support hardware
* handshake.
*/
#define DEVSCI_DRIVER_TABLE_ENTRY \
{ sh_sci_initialize, sh_sci_open, sh_sci_close, sh_sci_read, \
sh_sci_write, sh_sci_control }
extern rtems_device_driver sh_sci_initialize(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
extern rtems_device_driver sh_sci_open(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
extern rtems_device_driver sh_sci_close(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
extern rtems_device_driver sh_sci_read(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
extern rtems_device_driver sh_sci_write(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
extern rtems_device_driver sh_sci_control(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
#ifdef __cplusplus
}
#endif
#endif

115
bsps/sh/gensh1/include/sh/sh7_pfc.h
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@@ -1,115 +0,0 @@
/*
* Bit values for the pin function controller of the Hitachi SH703X
*
* From Hitachi tutorials
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef _sh7_pfc_h
#define _sh7_pfc_h
#include <rtems/score/iosh7032.h>
/*
* Port B IO Register (PBIOR)
*/
#define PBIOR PFC_PBIOR
#define PB15IOR 0x8000
#define PB14IOR 0x4000
#define PB13IOR 0x2000
#define PB12IOR 0x1000
#define PB11IOR 0x0800
#define PB10IOR 0x0400
#define PB9IOR 0x0200
#define PB8IOR 0x0100
#define PB7IOR 0x0080
#define PB6IOR 0x0040
#define PB5IOR 0x0020
#define PB4IOR 0x0010
#define PB3IOR 0x0008
#define PB2IOR 0x0004
#define PB1IOR 0x0002
#define PB0IOR 0x0001
/*
* Port B Control Register (PBCR1)
*/
#define PBCR1 PFC_PBCR1
#define PB15MD1 0x8000
#define PB15MD0 0x4000
#define PB14MD1 0x2000
#define PB14MD0 0x1000
#define PB13MD1 0x0800
#define PB13MD0 0x0400
#define PB12MD1 0x0200
#define PB12MD0 0x0100
#define PB11MD1 0x0080
#define PB11MD0 0x0040
#define PB10MD1 0x0020
#define PB10MD0 0x0010
#define PB9MD1 0x0008
#define PB9MD0 0x0004
#define PB8MD1 0x0002
#define PB8MD0 0x0001
#define PB15MD PB15MD1|PB14MD0
#define PB14MD PB14MD1|PB14MD0
#define PB13MD PB13MD1|PB13MD0
#define PB12MD PB12MD1|PB12MD0
#define PB11MD PB11MD1|PB11MD0
#define PB10MD PB10MD1|PB10MD0
#define PB9MD PB9MD1|PB9MD0
#define PB8MD PB8MD1|PB8MD0
#define PB_TXD1 PB11MD1
#define PB_RXD1 PB10MD1
#define PB_TXD0 PB9MD1
#define PB_RXD0 PB8MD1
/*
* Port B Control Register (PBCR2)
*/
#define PBCR2 PFC_PBCR2
#define PB7MD1 0x8000
#define PB7MD0 0x4000
#define PB6MD1 0x2000
#define PB6MD0 0x1000
#define PB5MD1 0x0800
#define PB5MD0 0x0400
#define PB4MD1 0x0200
#define PB4MD0 0x0100
#define PB3MD1 0x0080
#define PB3MD0 0x0040
#define PB2MD1 0x0020
#define PB2MD0 0x0010
#define PB1MD1 0x0008
#define PB1MD0 0x0004
#define PB0MD1 0x0002
#define PB0MD0 0x0001
#define PB7MD PB7MD1|PB7MD0
#define PB6MD PB6MD1|PB6MD0
#define PB5MD PB5MD1|PB5MD0
#define PB4MD PB4MD1|PB4MD0
#define PB3MD PB3MD1|PB3MD0
#define PB2MD PB2MD1|PB2MD0
#define PB1MD PB1MD1|PB1MD0
#define PB0MD PB0MD1|PB0MD0
#endif /* _sh7_pfc_h */

79
bsps/sh/gensh1/include/sh/sh7_sci.h
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@@ -1,79 +0,0 @@
/*
* Bit values for the serial control registers of the Hitachi SH703X
*
* From Hitachi tutorials
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef _sh7_sci_h
#define _sh7_sci_h
#include <rtems/score/iosh7032.h>
/*
* Serial mode register bits
*/
#define SCI_SYNC_MODE 0x80
#define SCI_SEVEN_BIT_DATA 0x40
#define SCI_PARITY_ON 0x20
#define SCI_ODD_PARITY 0x10
#define SCI_STOP_BITS_2 0x08
#define SCI_ENABLE_MULTIP 0x04
#define SCI_PHI_64 0x03
#define SCI_PHI_16 0x02
#define SCI_PHI_4 0x01
#define SCI_PHI_0 0x00
/*
* Serial register offsets, relative to SCI0_SMR or SCI1_SMR
*/
#define SCI_SMR 0x00
#define SCI_BRR 0x01
#define SCI_SCR 0x02
#define SCI_TDR 0x03
#define SCI_SSR 0x04
#define SCI_RDR 0x05
/*
* Serial control register bits
*/
#define SCI_TIE 0x80 /* Transmit interrupt enable */
#define SCI_RIE 0x40 /* Receive interrupt enable */
#define SCI_TE 0x20 /* Transmit enable */
#define SCI_RE 0x10 /* Receive enable */
#define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */
#define SCI_TEIE 0x04 /* Transmit end interrupt enable */
#define SCI_CKE1 0x02 /* Clock enable 1 */
#define SCI_CKE0 0x01 /* Clock enable 0 */
/*
* Serial status register bits
*/
#define SCI_TDRE 0x80 /* Transmit data register empty */
#define SCI_RDRF 0x40 /* Receive data register full */
#define SCI_ORER 0x20 /* Overrun error */
#define SCI_FER 0x10 /* Framing error */
#define SCI_PER 0x08 /* Parity error */
#define SCI_TEND 0x04 /* Transmit end */
#define SCI_MPB 0x02 /* Multiprocessor bit */
#define SCI_MPBT 0x01 /* Multiprocessor bit transfer */
#endif /* _sh7_sci_h */

1
bsps/sh/gensh1/include/tm27.h
View File

@@ -1 +0,0 @@
#include <rtems/tm27-default.h>

169
bsps/sh/gensh1/start/cpu_asm.c
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@@ -1,169 +0,0 @@
/*
* This file contains the basic algorithms for all assembly code used
* in an specific CPU port of RTEMS. These algorithms must be implemented
* in assembly language
*
* NOTE: This port uses a C file with inline assembler instructions
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
*/
/*
* This is supposed to be an assembly file. This means that system.h
* and cpu.h should not be included in a "real" cpu_asm file. An
* implementation in assembly should include "cpu_asm.h"
*/
#include <rtems/score/percpu.h>
#include <rtems/score/isr.h>
#include <rtems/score/threaddispatch.h>
#include <rtems/score/sh.h>
#include <rtems/score/ispsh7032.h>
#include <rtems/score/ispsh7032.h>
#include <rtems/score/iosh7032.h>
#include <rtems/score/sh_io.h>
unsigned long *_old_stack_ptr;
register unsigned long *stack_ptr __asm__ ("r15");
/*
* sh_set_irq_priority
*
* this function sets the interrupt level of the specified interrupt
*
* parameters:
* - irq : interrupt number
* - prio: priority to set for this interrupt number
*
* returns: 0 if ok
* -1 on error
*/
unsigned int sh_set_irq_priority(
unsigned int irq,
unsigned int prio )
{
uint32_t shiftcount;
uint32_t prioreg;
uint16_t temp16;
ISR_Level level;
/*
* first check for valid interrupt
*/
if (( irq > 113) || (_Hardware_isr_Table[irq] == _dummy_isp))
return -1;
/*
* check for valid irq priority
*/
if ( prio > 15 )
return -1;
/*
* look up appropriate interrupt priority register
*/
if ( irq > 71)
{
irq = irq - 72;
shiftcount = 12 - ((irq & ~0x03) % 16);
switch( irq / 16)
{
case 0: { prioreg = INTC_IPRC; break;}
case 1: { prioreg = INTC_IPRD; break;}
case 2: { prioreg = INTC_IPRE; break;}
default: return -1;
}
}
else
{
shiftcount = 12 - 4 * ( irq % 4);
if ( irq > 67)
prioreg = INTC_IPRB;
else
prioreg = INTC_IPRA;
}
/*
* Set the interrupt priority register
*/
_ISR_Local_disable( level );
temp16 = read16( prioreg);
temp16 &= ~( 15 << shiftcount);
temp16 |= prio << shiftcount;
write16( temp16, prioreg);
_ISR_Local_enable( level );
return 0;
}
/*
* This routine provides the RTEMS interrupt management.
*/
void __ISR_Handler( uint32_t vector)
{
ISR_Level level;
_ISR_Local_disable( level );
_Thread_Dispatch_disable();
if ( _ISR_Nest_level == 0 )
{
/* Install irq stack */
_old_stack_ptr = stack_ptr;
stack_ptr = _CPU_Interrupt_stack_high;
}
_ISR_Nest_level++;
_ISR_Local_enable( level );
/* call isp */
if ( _ISR_Vector_table[ vector])
(*_ISR_Vector_table[ vector ])( vector );
_ISR_Local_disable( level );
_Thread_Dispatch_unnest( _Per_CPU_Get() );
_ISR_Nest_level--;
if ( _ISR_Nest_level == 0 )
/* restore old stack pointer */
stack_ptr = _old_stack_ptr;
_ISR_Local_enable( level );
if ( _ISR_Nest_level )
return;
if ( !_Thread_Dispatch_is_enabled() ) {
return;
}
if ( _Thread_Dispatch_necessary ) {
_Thread_Dispatch();
}
}

248
bsps/sh/gensh1/start/ispsh7032.c
View File

@@ -1,248 +0,0 @@
/*
* This file contains the isp frames for the user interrupts.
* From these procedures __ISR_Handler is called with the vector number
* as argument.
*
* __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
* some releases of gcc doesn't properly handle #pragma interrupt, if a
* file contains both isrs and normal functions.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems/score/cpu.h>
#include <rtems/score/ispsh7032.h>
/*
* This is an exception vector table
*
* It has the same structure like the actual vector table (vectab)
*/
CPU_ISR_raw_handler _Hardware_isr_Table[256]={
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp,
_nmi_isp, _usb_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp,
/* trapa 0 -31 */
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
/* irq 64 ... */
_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp,
_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
_dma0_isp, _dummy_isp, _dma1_isp, _dummy_isp,
_dma2_isp, _dummy_isp, _dma3_isp, _dummy_isp,
_imia0_isp, _imib0_isp, _ovi0_isp, _dummy_isp,
_imia1_isp, _imib1_isp, _ovi1_isp, _dummy_isp,
_imia2_isp, _imib2_isp, _ovi2_isp, _dummy_isp,
_imia3_isp, _imib3_isp, _ovi3_isp, _dummy_isp,
_imia4_isp, _imib4_isp, _ovi4_isp, _dummy_isp,
_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp,
_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
_prt_isp, _adu_isp, _dummy_isp, _dummy_isp,
_wdt_isp,
/* 113 */ _dref_isp
};
#define Str(a)#a
/*
* Some versions of gcc and all version of egcs at least until egcs-1.1b
* are not able to handle #pragma interrupt correctly if more than 1 isr is
* contained in a file and when optimizing.
* We try to work around this problem by using the macro below.
*/
#define isp( name, number, func)\
__asm__ (".global _"Str(name)"\n\t" \
"_"Str(name)": \n\t" \
" mov.l r0,@-r15 \n\t" \
" mov.l r1,@-r15 \n\t" \
" mov.l r2,@-r15 \n\t" \
" mov.l r3,@-r15 \n\t" \
" mov.l r4,@-r15 \n\t" \
" mov.l r5,@-r15 \n\t" \
" mov.l r6,@-r15 \n\t" \
" mov.l r7,@-r15 \n\t" \
" mov.l r14,@-r15 \n\t" \
" sts.l pr,@-r15 \n\t" \
" sts.l mach,@-r15 \n\t" \
" sts.l macl,@-r15 \n\t" \
" mov r15,r14 \n\t" \
" mov.l "Str(name)"_k, r1\n\t" \
" jsr @r1 \n\t" \
" mov #"Str(number)", r4\n\t" \
" mov r14,r15 \n\t" \
" lds.l @r15+,macl \n\t" \
" lds.l @r15+,mach \n\t" \
" lds.l @r15+,pr \n\t" \
" mov.l @r15+,r14 \n\t" \
" mov.l @r15+,r7 \n\t" \
" mov.l @r15+,r6 \n\t" \
" mov.l @r15+,r5 \n\t" \
" mov.l @r15+,r4 \n\t" \
" mov.l @r15+,r3 \n\t" \
" mov.l @r15+,r2 \n\t" \
" mov.l @r15+,r1 \n\t" \
" mov.l @r15+,r0 \n\t" \
" rte \n\t" \
" nop \n\t" \
" .align 2 \n\t" \
#name"_k: \n\t" \
".long "Str(func));
/************************************************
* Dummy interrupt service procedure for
* interrupts being not allowed --> Trap 34
************************************************/
__asm__ (" .section .text\n\
.global __dummy_isp\n\
__dummy_isp:\n\
mov.l r14,@-r15\n\
mov r15, r14\n\
trapa #34\n\
mov.l @r15+,r14\n\
rte\n\
nop");
/*****************************
* Non maskable interrupt
*****************************/
isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
/*****************************
* User break controller
*****************************/
isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
/*****************************
* External interrupts 0-7
*****************************/
isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler);
isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler);
isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler);
isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler);
isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
/*****************************
* DMA - controller
*****************************/
isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
/*****************************
* Interrupt timer unit
*****************************/
/*****************************
* Timer 0
*****************************/
isp( _imia0_isp, IMIA0_ISP_V, ___ISR_Handler);
isp( _imib0_isp, IMIB0_ISP_V, ___ISR_Handler);
isp( _ovi0_isp, OVI0_ISP_V, ___ISR_Handler);
/*****************************
* Timer 1
*****************************/
isp( _imia1_isp, IMIA1_ISP_V, ___ISR_Handler);
isp( _imib1_isp, IMIB1_ISP_V, ___ISR_Handler);
isp( _ovi1_isp, OVI1_ISP_V, ___ISR_Handler);
/*****************************
* Timer 2
*****************************/
isp( _imia2_isp, IMIA2_ISP_V, ___ISR_Handler);
isp( _imib2_isp, IMIB2_ISP_V, ___ISR_Handler);
isp( _ovi2_isp, OVI2_ISP_V, ___ISR_Handler);
/*****************************
* Timer 3
*****************************/
isp( _imia3_isp, IMIA3_ISP_V, ___ISR_Handler);
isp( _imib3_isp, IMIB3_ISP_V, ___ISR_Handler);
isp( _ovi3_isp, OVI3_ISP_V, ___ISR_Handler);
/*****************************
* Timer 4
*****************************/
isp( _imia4_isp, IMIA4_ISP_V, ___ISR_Handler);
isp( _imib4_isp, IMIB4_ISP_V, ___ISR_Handler);
isp( _ovi4_isp, OVI4_ISP_V, ___ISR_Handler);
/*****************************
* Serial interfaces
*****************************/
/*****************************
* Serial interface 0
*****************************/
isp( _eri0_isp, ERI0_ISP_V, ___ISR_Handler);
isp( _rxi0_isp, RXI0_ISP_V, ___ISR_Handler);
isp( _txi0_isp, TXI0_ISP_V, ___ISR_Handler);
isp( _tei0_isp, TEI0_ISP_V, ___ISR_Handler);
/*****************************
* Serial interface 1
*****************************/
isp( _eri1_isp, ERI1_ISP_V, ___ISR_Handler);
isp( _rxi1_isp, RXI1_ISP_V, ___ISR_Handler);
isp( _txi1_isp, TXI1_ISP_V, ___ISR_Handler);
isp( _tei1_isp, TEI1_ISP_V, ___ISR_Handler);
/*****************************
* Parity control unit of
* the bus state controller
*****************************/
isp( _prt_isp, PRT_ISP_V, ___ISR_Handler);
/******************************
* Analog digital converter
* ADC
******************************/
isp( _adu_isp, ADU_ISP_V, ___ISR_Handler);
/******************************
* Watchdog timer
******************************/
isp( _wdt_isp, WDT_ISP_V, ___ISR_Handler);
/******************************
* DRAM refresh control unit
* of bus state controller
******************************/
isp( _dref_isp, DREF_ISP_V, ___ISR_Handler);

241
bsps/sh/gensh1/start/linkcmds
View File

@@ -1,241 +0,0 @@
/*
* This is an adapted linker script from egcs-1.0.1
*
* Memory layout for an SH 7032 with main memory in area 2
* This memory layout it very similar to that used for Hitachi's
* EVB with CMON in rom
*
* NOTE: The ram start address may vary, all other start addresses are fixed
* Not suiteable for gdb's simulator
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
OUTPUT_ARCH(sh)
ENTRY(_start)
STARTUP(start.o)
_RamBase = DEFINED(_RamBase) ? _RamBase : 0x0a040000;
_RamSize = DEFINED(_RamSize) ? _RamSize : 512K;
_RamEnd = _RamBase + _RamSize;
_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
MEMORY
{
rom : o = 0x00000000, l = 128k
onchip_peri : o = 0x05000000, l = 512
ram : o = 0x0A040000, l = 512k /* enough to link all tests */
onchip_ram : o = 0x0f000000, l = 8k
}
SECTIONS
{
/* boot vector table */
.monvects 0x00000000 (NOLOAD): {
_monvects = . ;
} > rom
/* monitor play area */
.monram 0x0A040000 (NOLOAD) :
{
_ramstart = .;
} > ram
/* monitor vector table */
.vects 0x0A042000 (NOLOAD) : {
_vectab = . ;
*(.vects);
}
/* Read-only sections, merged into text segment: */
. = 0x0a044000 ;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.gnu.version : { *(.gnu.version) }
.gnu.version_d : { *(.gnu.version_d) }
.gnu.version_r : { *(.gnu.version_r) }
.rela.dyn :
{
*(.rela.init)
*(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
*(.rela.fini)
*(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
*(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
*(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
*(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
*(.rela.ctors)
*(.rela.dtors)
*(.rela.got)
*(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
*(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
*(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
*(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
*(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
} >ram
.rel.text :
{ *(.rel.text) *(.rel.gnu.linkonce.t*) }
.rel.data :
{ *(.rel.data) *(.rel.gnu.linkonce.d*) }
.rel.rodata :
{ *(.rel.rodata*) *(.rel.gnu.linkonce.r*) }
.rel.got : { *(.rel.got) }
.rel.ctors : { *(.rel.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rel.init : { *(.rel.init) }
.rel.fini : { *(.rel.fini) }
.rel.bss : { *(.rel.bss) }
.rel.plt : { *(.rel.plt) }
.plt : { *(.plt) }
.text . :
{
_start = .;
*(.text*)
*(.stub)
/*
* Special FreeBSD sysctl sections.
*/
. = ALIGN (16);
__start_set_sysctl_set = .;
___start_set_sysctl_set = .;
*(set_sysc*); /* set_sysctl_* but name is truncated by SH-coff */
__stop_set_sysctl_set = ABSOLUTE(.);
___stop_set_sysctl_set = ABSOLUTE(.);
*(set_doma*); /* set_domain_* but name is truncated by SH-coff */
*(set_pseu*); /* set_pseudo_* but name is truncated by SH-coff */
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
*(.gnu.linkonce.t*)
} > ram
_etext = .;
PROVIDE (etext = .);
.init . : { KEEP(*(.init)) } > ram =0
.fini . : { KEEP(*(.fini)) } > ram =0
.ctors . : { KEEP(*(.ctors)) } > ram =0
.dtors . : { KEEP(*(.dtors)) } > ram =0
.rodata . : { *(.rodata*) KEEP (*(SORT(.rtemsroset.*))) *(.gnu.linkonce.r*) } > ram
.rodata1 . : { *(.rodata1) } > ram
.tdata : {
__TLS_Data_begin = .;
*(.tdata .tdata.* .gnu.linkonce.td.*)
__TLS_Data_end = .;
} > ram
.tbss : {
__TLS_BSS_begin = .;
*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
__TLS_BSS_end = .;
} > ram
__TLS_Data_size = __TLS_Data_end - __TLS_Data_begin;
__TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin;
__TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin;
__TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin;
__TLS_Size = __TLS_BSS_end - __TLS_Data_begin;
__TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. */
. = ALIGN(128) + (. & (128 - 1));
.data . :
{
*(.data*)
KEEP (*(SORT(.rtemsrwset.*)))
*(.gcc_exc*)
___EH_FRAME_BEGIN__ = .;
*(.eh_fram*)
___EH_FRAME_END__ = .;
LONG(0);
*(.gcc_except_table*)
*(.gnu.linkonce.d*)
CONSTRUCTORS
} > ram
.data1 . : { *(.data1) }
.got . : { *(.got.plt) *(.got) }
.dynamic . : { *(.dynamic) }
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
.sdata . : { *(.sdata) }
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.sbss . : { *(.sbss*) *(.scommon) }
.bss . :
{
*(.dynbss)
*(.bss .bss* .gnu.linkonce.b*)
*(COMMON)
} > ram
_end = . ;
PROVIDE (end = .);
.noinit (NOLOAD) : {
*(SORT_BY_NAME (SORT_BY_ALIGNMENT (.noinit*)))
} > ram
.rtemsstackinterrupt (NOLOAD) : {
*(.rtemsstack.interrupt)
} > onchip_ram
.rtemsstack (NOLOAD) : {
*(SORT(.rtemsstack.*))
} > ram
_WorkAreaBase = . ;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* These must appear regardless of . */
/* Addition to let linker know about custom section for GDB pretty-printing support. */
.debug_gdb_scripts 0 : { *(.debug_gdb_scripts) }
}

82
bsps/sh/gensh1/start/start.S
View File

@@ -1,82 +0,0 @@
/*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems/asm.h>
BEGIN_CODE
PUBLIC(start)
SYM (start):
! install the stack pointer
mov.l stack_k,r15
! zero out bss
mov.l edata_k,r0
mov.l end_k,r1
mov #0,r2
0:
mov.l r2,@r0
add #4,r0
cmp/ge r0,r1
bt 0b
! copy the vector table from rom to ram
mov.l vects_k,r0 ! vectab
mov #0,r1 ! address of boot vector table
mov #0,r2 ! number of bytes copied
mov.w vects_size,r3 ! size of entries in vectab
1:
mov.l @r1+,r4
mov.l r4,@r0
add #4,r0
add #1,r2
cmp/hi r3,r2
bf 1b
mov.l vects_k,r0 ! update vbr to point to vectab
ldc r0,vbr
! call the mainline
mov #0,r4 ! command line
mov.l main_k,r0
jsr @r0
! call exit
mov r0,r4
mov.l exit_k,r0
jsr @r0
or r0,r0
END_CODE
.align 2
stack_k:
.long SYM(_ISR_Stack_area_end)
edata_k:
.long SYM(edata)
end_k:
.long SYM(end)
main_k:
.long SYM(boot_card)
exit_k:
.long SYM(exit)
vects_k:
.long SYM(vectab)
vects_size:
.word 255

224
bsps/sh/gensh2/README.md
View File

@@ -1,224 +0,0 @@
gensh2
======
Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
Adapted by: John Mills (jmills@tga.com)
Corrections: Radzislaw Galler (rgaller@et.put.poznan.pl)
```
BSP NAME: generic SH2 (gensh2)
BOARD: EVB7045F (note 2)
BUS: n/a
CPU FAMILY: Hitachi SH
CPU: SH 7045F
COPROCESSORS: none
MODE: n/a
DEBUG MONITOR: gdb
```
PERIPHERALS
-----------
```
TIMERS: on-chip
RESOLUTION: cf. Hitachi SH 704X Hardware Manual (Phi/16)
SERIAL PORTS: on-chip (with 2 ports)
REAL-TIME CLOCK: none
DMA: not used
VIDEO: none
SCSI: none
NETWORKING: none
```
DRIVER INFORMATION
------------------
```
CLOCK DRIVER: on-chip timer
IOSUPP DRIVER: default
SHMSUPP: default
TIMER DRIVER: on-chip timer
TTY DRIVER: /dev/console
```
STDIO
-----
```
PORT: /dev/sci0
ELECTRICAL: SCI0
BAUD: 9600
BITS PER CHARACTER: 8
PARITY: NONE
STOP BITS: 1
```
NOTES
-----
(1) The present 'hw_init.c' file provides 'early_hw_init'(void) which
is normally called from 'start.S' to provide such minimal HW setup
as is conveniently written in 'C' and can make use of global
symbols for 7045F processor elements. It also provides
'void bsp_hw_init (void)' normally called from 'bspstart.c', shortly
before RTEMS itself is started.
These are both minimal functions intended to support the RTEMS test
suites.
(2) See README.EVB7045F
Getting started with EVB7045F and gensh2
----------------------------------------
Author: Radzislaw Galler (rgaller@et.put.poznan.pl)
This is a capture of success path to put a RTEMS sample
'hello.exe' on the evaluation board EVB7045F.
What you need
-------------
* Computer with two operating systems: Linux and Wndows 2000 (tm) -
that was in my case (see section 'Variations')
* Flash Development Toolkit (FDT) - available on HMSE homepage
(http://www.hmse.com/products/fdt/support.htm)
* 'gdbstubs' - available on SourceForge
(http://sourceforge.net/projects/gdbstubs/)
* working GNU C compiler for Hitach SH processors; do-it-yourself
(on Linux) or download ready stuff for Windows'9x/NT/2k from
(http://www.hitachi-eu.com/hel/ecg/) or from Hitach Databook 2001
CD-ROM (if no luck try to search on the net for gnu99r1p1.zip)
* GDB compiled for target sh-rtems - do-it-yourself or download
from ftp://ftp.oarcorp.com:21/pub/rtems/snapshots/c_tools/
* RTEMS (ofcourse) you probably already have if you are reading this
document
Instalation of 'gdbstubs'
-------------------------
Once you downladed and unzipped gdbstubs you have to compile
it. First modify the Makefile to use the compiler installed on your
machine. Then issue the command:
$ make
This should produce the default target sh2-7045edk.out. This is the
S-record file which should be added to FDT project (renaming it to
*.mot extension helps a bit).
If you are lucky you will be able to put the file into the FLASH
following the instuctions in FDT and EVB manuals.
Well I wasn't lucky so I had to bypass the Universal Programming
Board (see EVB7045F User Manual) and manually put the processor into
BOOT mode. This can be done by shortening the capacitor C8 (or C108
on schematics) which puts the UPB into permanent reset state, and by
removing jumper JP4 (or JP104 on schematics) and connecting its
middle pin to the ground. After pressing CRES button the processor
is in BOOT mode. In FDT select "direct connection":
Menu Project->Properties->Device->Select Interface
After that there should be no problem in putting the program into the
FLASH.
Loading 'hello.exe' on board
----------------------------
I assume you are able to compile RTEMS with 'gensh2' BSP and
necessary tools. If not please refer to 'started.pdf' document which
describes the procedure (http://www.oarcorp.com/).
At the time of writing this document 'gdbstubs' default
communication port was SCI1. So it was the default port for
/dev/console in RTEMS. To avoid problems I had check these settings
both in 'gdbstubs' and $RTEMS_ROOT/c/src/lib/libbsp/sh/gensh2/include/bsp.h
After changing the line
```c
#define BSP_CONSOLE_DEVNAME "/dev/sci1"
```
to
```c
#define BSP_CONSOLE_DEVNAME "/dev/sci0"
```
in 'bsp.h' and rebuilding RTEMS there should no problem in running
'hello.exe' and other samples.
For downloading connect a serial cable to computer and EVB. You will
also need a second cable and second serial port to see the effects
of your work.
Assuming you are working in Linux and Xwindows fire up two terminal
windows. In the first one run sh-rtems-gdb, in the second run a
serial port terminal (for example 'minicom'). Set up the serial
terminal to a port connected to SCI0 and leave the window in a
visible place on the desktop. The debugger should be invoked best
from the directory where 'hello.exe' is placed. Assuming that here
is a GDB session:
--------start------
```shell
$ sh-rtems-gdb hello.exe
GNU gdb 5.0
Copyright 2000 Free Software Foundation, Inc.
GDB is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
Type "show copying" to see the conditions.
There is absolutely no warranty for GDB. Type "show warranty" for details.
This GDB was configured as "--host=i686-pc-linux-gnu --target=sh-rtems"...
(gdb) set remotebaud 115200
(gdb) target remote /dev/ttyS0
Remote debugging using /dev/ttyS0
0x0 in ?? ()
(gdb) load
Loading section .text, size 0x12d70 lma 0x444000
Loading section .data, size 0xb80 lma 0x456df0
Loading section .stack, size 0x10 lma 0xfffffec0
Start address 0x444000 , load size 80128
Transfer rate: 58274 bits/sec, 153 bytes/write.
(gdb) continue
Continuing.
Program received signal 0, Signal 0.
0x44ec36 in exit (code=0) at exit.c:70
70 exit.c: No such file or directory.
(gdb)
--------end-------
```
And here is a capture from the serial terminal window:
```shell
*** HELLO WORLD TEST ***
Hello World
*** END OF HELLO WORLD TEST ***
Beautiful, isn't it? That's all!
```
Variations
----------
I'm sure that not every one can afford having two operating systems
on one computer. I believe there will be a day that nobody will need
an MS stuff anymore... ;)
It is possible to repeat the success on MS Windows only. To do the
same on Linux only you need a tool to downlad 'gdbstubs' on the
board. This should be no problem to find it on the net but right now
I don't know about it.
For your convenience there are several graphical interfaces for GDB
available on the net. I just name two of them:
DDD - stands for Data Display Debugger
(http://www.gnu.org/software/ddd/)
Insight - a Tcl/Tk interface available both for MS Windows and
Xwindows (http://sources.redhat.com/insight/)

191
bsps/sh/gensh2/btimer/btimer.c
View File

@@ -1,191 +0,0 @@
/**
* @file
* @brief Timer for the Hitachi SH 704X
*/
/*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <rtems/btimer.h>
#include <rtems/score/sh_io.h>
#include <rtems/score/iosh7045.h>
extern uint32_t bsp_clicks_per_second;
/*
* We use a Phi/4 timer
*/
#define SCALE (Timer_MHZ/4)
#define MTU1_STARTMASK 0xfd
#define MTU1_SYNCMASK 0xfd
#define MTU1_MODEMASK 0xc0
#define MTU1_TCRMASK 0x01
#define MTU1_TIORMASK 0x88
#define MTU1_STAT_MASK 0xf8
#define MTU1_TIERMASK 0xfc
#define IPRC_MTU1_MASK 0xfff0
#ifndef MTU1_PRIO
#define MTU1_PRIO 15
#endif
#define MTU1_VECTOR 86
extern rtems_isr timerisr(void);
static uint32_t Timer_interrupts;
bool benchmark_timer_find_average_overhead;
static uint32_t Timer_MHZ ;
void benchmark_timer_initialize( void )
{
uint8_t temp8;
uint16_t temp16;
rtems_interrupt_level level;
rtems_isr *ignored;
Timer_MHZ = bsp_clicks_per_second / 1000000 ;
/*
* Timer has never overflowed. This may not be necessary on some
* implemenations of timer but ....
*/
Timer_interrupts /* .i */ = 0;
rtems_interrupt_disable( level );
/*
* Somehow start the timer
*/
/* stop Timer 1 */
temp8 = read8(MTU_TSTR) & MTU1_STARTMASK;
write8( temp8, MTU_TSTR );
/* initialize counter 1 */
write16( 0, MTU_TCNT1);
/* Timer 1 is independent of other timers */
temp8 = read8(MTU_TSYR) & MTU1_SYNCMASK;
write8( temp8, MTU_TSYR );
/* Timer 1, normal mode */
temp8 = read8(MTU_TMDR1) & MTU1_MODEMASK;
write8( temp8, MTU_TMDR1 );
/* x0000000
* |||||+++--- Internal Clock
* |||++------ Count on rising edge
* |++-------- disable TCNT clear
* +---------- don`t care
*/
write8( MTU1_TCRMASK, MTU_TCR1 );
/* gra and grb are not used */
write8( MTU1_TIORMASK, MTU_TIOR1 );
/* reset all status flags */
temp8 = read8(MTU_TSR1) & MTU1_STAT_MASK;
write8( temp8, MTU_TSR1 );
/* enable overflow interrupt */
write8( MTU1_TIERMASK, MTU_TIER1 );
/* set interrupt priority */
temp16 = read16(INTC_IPRC) & IPRC_MTU1_MASK;
temp16 |= MTU1_PRIO;
write16( temp16, INTC_IPRC);
/* initialize ISR */
_CPU_ISR_install_raw_handler( MTU1_VECTOR, timerisr, &ignored );
rtems_interrupt_enable( level );
/* start timer 1 */
temp8 = read8(MTU_TSTR) | ~MTU1_STARTMASK;
write8( temp8, MTU_TSTR );
}
/*
* The following controls the behavior of benchmark_timer_read().
*
* AVG_OVERHEAD is the overhead for starting and stopping the timer. It
* is usually deducted from the number returned.
*
* LEAST_VALID is the lowest number this routine should trust. Numbers
* below this are "noise" and zero is returned.
*/
#define AVG_OVERHEAD 1 /* It typically takes X.X microseconds */
/* (Y countdowns) to start/stop the timer. */
/* This value is in microseconds. */
#define LEAST_VALID 0 /* 20 */ /* Don't trust a clicks value lower than this */
benchmark_timer_t benchmark_timer_read( void )
{
uint32_t clicks;
uint32_t total ;
/*
* Read the timer and see how many clicks it has been since we started.
*/
clicks = read16( MTU_TCNT1 ); /* XXX: read some HW here */
/*
* Total is calculated by taking into account the number of timer overflow
* interrupts since the timer was initialized and clicks since the last
* interrupts.
*/
total = clicks + Timer_interrupts * 65536;
if ( benchmark_timer_find_average_overhead )
return total / SCALE; /* in XXX microsecond units */
else
{
if ( total < LEAST_VALID )
return 0; /* below timer resolution */
/*
* Somehow convert total into microseconds
*/
return (total / SCALE - AVG_OVERHEAD) ;
}
}
void benchmark_timer_disable_subtracting_average_overhead(bool find_flag)
{
benchmark_timer_find_average_overhead = find_flag;
}
/* Timer 1 is used */
#pragma interrupt
void timerisr( void )
{
uint8_t temp8;
/* reset the flags of the status register */
temp8 = read8(MTU_TSR1) & MTU1_STAT_MASK;
write8( temp8, MTU_TSR1 );
Timer_interrupts += 1;
}

234
bsps/sh/gensh2/clock/ckinit.c
View File

@@ -1,234 +0,0 @@
/*
* This file contains the clock driver the Hitachi SH 704X
*/
/*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* Modified to reflect registers of sh7045 processor:
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
* August, 1999
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <stdlib.h>
#include <rtems/clockdrv.h>
#include <rtems/score/sh_io.h>
#include <rtems/score/sh.h>
#include <rtems/score/ispsh7045.h>
#include <rtems/score/iosh7045.h>
static void Clock_exit( void );
extern uint32_t bsp_clicks_per_second;
#define _MTU_COUNTER0_MICROSECOND (Clock_MHZ/16)
#ifndef CLOCKPRIO
#define CLOCKPRIO 10
#endif
#define MTU0_STARTMASK 0xfe
#define MTU0_SYNCMASK 0xfe
#define MTU0_MODEMASK 0xc0
#define MTU0_TCRMASK 0x22 /* bit 7 also used, vs 703x */
#define MTU0_STAT_MASK 0xc0
#define MTU0_IRQMASK 0xfe
#define MTU0_TIERMASK 0x01
#define IPRC_MTU0_MASK 0xff0f
#define MTU0_TIORVAL 0x08
/*
* The interrupt vector number associated with the clock tick device
* driver.
*/
#define CLOCK_VECTOR MTUA0_ISP_V
/*
* Clock_driver_ticks is a monotonically increasing counter of the
* number of clock ticks since the driver was initialized.
*/
volatile uint32_t Clock_driver_ticks;
static rtems_isr Clock_isr( rtems_vector_number vector );
static uint32_t Clock_MHZ ;
/*
* Clock_isrs is the number of clock ISRs until the next invocation of
* the RTEMS clock tick routine. The clock tick device driver
* gets an interrupt once a millisecond and counts down until the
* length of time between the user configured microseconds per tick
* has passed.
*/
uint32_t Clock_isrs; /* ISRs until next tick */
static uint32_t Clock_isrs_const; /* only calculated once */
/*
* The previous ISR on this clock tick interrupt vector.
*/
rtems_isr_entry Old_ticker;
/*
* Isr Handler
*/
static rtems_isr Clock_isr(
rtems_vector_number vector
)
{
/*
* bump the number of clock driver ticks since initialization
*
* determine if it is time to announce the passing of tick as configured
* to RTEMS through the rtems_clock_tick directive
*
* perform any timer dependent tasks
*/
uint8_t temp;
/* reset the flags of the status register */
temp = read8( MTU_TSR0) & MTU0_STAT_MASK;
write8( temp, MTU_TSR0);
Clock_driver_ticks++ ;
if( Clock_isrs == 1)
{
rtems_clock_tick();
Clock_isrs = Clock_isrs_const;
}
else
{
Clock_isrs-- ;
}
}
/*
* Install_clock
*
* Install a clock tick handler and reprograms the chip. This
* is used to initially establish the clock tick.
*/
static void Install_clock(
rtems_isr_entry clock_isr
)
{
uint8_t temp8 = 0;
uint32_t factor = 1000000;
/*
* Initialize the clock tick device driver variables
*/
Clock_driver_ticks = 0;
Clock_isrs_const = rtems_configuration_get_microseconds_per_tick() / 10000;
Clock_isrs = Clock_isrs_const;
factor /= rtems_configuration_get_microseconds_per_tick(); /* minimalization of integer division error */
Clock_MHZ = bsp_clicks_per_second / factor ;
rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker );
/*
* Hardware specific initialize goes here
*/
/* stop Timer 0 */
temp8 = read8( MTU_TSTR) & MTU0_STARTMASK;
write8( temp8, MTU_TSTR);
/* set initial counter value to 0 */
write16( 0, MTU_TCNT0);
/* Timer 0 runs independent */
temp8 = read8( MTU_TSYR) & MTU0_SYNCMASK;
write8( temp8, MTU_TSYR);
/* Timer 0 normal mode */
temp8 = read8( MTU_TMDR0) & MTU0_MODEMASK;
write8( temp8, MTU_TMDR0);
/* TCNT is cleared by GRA ; internal clock /16 */
write8( MTU0_TCRMASK , MTU_TCR0);
/* use GRA without I/O - pins */
write8( MTU0_TIORVAL, MTU_TIORL0);
/* reset flags of the status register */
temp8 = read8( MTU_TSR0) & MTU0_STAT_MASK;
write8( temp8, MTU_TSR0);
/* Irq if is equal GRA */
temp8 = read8( MTU_TIER0) | MTU0_TIERMASK;
write8( temp8, MTU_TIER0);
/* set interrupt priority */
if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
/* set counter limits */
write16( _MTU_COUNTER0_MICROSECOND, MTU_GR0A);
/* start counter */
temp8 = read8( MTU_TSTR) |~MTU0_STARTMASK;
write8( temp8, MTU_TSTR);
/*
* Schedule the clock cleanup routine to execute if the application exits.
*/
atexit( Clock_exit );
}
/*
* Clean up before the application exits
*/
void Clock_exit( void )
{
uint8_t temp8 = 0;
/* turn off the timer interrupts */
/* set interrupt priority to 0 */
if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred( RTEMS_UNSATISFIED);
/*
* temp16 = read16( MTU_TIER0) & IPRC_MTU0_IRQMASK;
* write16( temp16, MTU_TIER0);
*/
/* stop counter */
temp8 = read8( MTU_TSTR) & MTU0_STARTMASK;
write8( temp8, MTU_TSTR);
/* old vector shall not be installed */
}
void _Clock_Initialize( void )
{
Install_clock( Clock_isr );
}

13
bsps/sh/gensh2/config/gensh2-testsuite.tcfg
View File

@@ -1,13 +0,0 @@
#
# gensh2 RTEMS Test Database.
#
# Format is one line per test that is _NOT_ built.
#
include: testdata/disable-iconv-tests.tcfg
exclude: fileio
exclude: fsdosfsname01
exclude: iostream
exclude: linpack
exclude: record02
exclude: utf8proc01

21
bsps/sh/gensh2/config/gensh2.cfg
View File

@@ -1,21 +0,0 @@
#
# gensh2.cfg
#
# default configuration for Hitachi sh1 processors
#
# Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
#
include $(RTEMS_ROOT)/make/custom/default.cfg
RTEMS_CPU=sh
# This contains the compiler options necessary to select the CPU model
# and (hopefully) optimize for it.
CPU_CFLAGS = -m2
# optimize flag: typically -O2
CFLAGS_OPTIMIZE_V = -O2 -g
CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections
LDFLAGS = -Wl,--gc-sections

149
bsps/sh/gensh2/console/config.c
View File

@@ -1,149 +0,0 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* This file contains the TTY driver table. The implementation is
* based on libchip/serial drivers, but it uses internal SHx SCI so
* the implementation of the driver is placed in
* lib/libcpu/sh/sh7045/sci instead of libchip/serial.
*
* COPYRIGHT (c) 1989-2001.
* On-Line Applications Research Corporation (OAR).
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <bsp.h>
#include <libchip/serial.h>
#include <libchip/sersupp.h>
#include <sh/sci_termios.h>
#include <rtems/score/sh_io.h>
#include <rtems/score/ispsh7045.h>
#include <rtems/score/iosh7045.h>
#include <rtems/termiostypes.h>
/*
* Function set for interrupt enabled termios console
*/
const console_fns sh_sci_fns =
{
libchip_serial_default_probe, /* deviceProbe */
sh_sci_first_open, /* deviceFirstOpen */
NULL, /* deviceLastClose */
NULL, /* deviceRead */
sh_sci_write_support_int, /* deviceWrite */
sh_sci_initialize_interrupts, /* deviceInitialize */
sh_sci_write_polled, /* deviceWritePolled */
sh_sci_set_attributes, /* deviceSetAttributes */
true /* deviceOutputUsesInterrupts */
};
/*
* Function set for polled termios console
*/
const console_fns sh_sci_fns_polled =
{
libchip_serial_default_probe, /* deviceProbe */
sh_sci_first_open, /* deviceFirstOpen */
sh_sci_last_close, /* deviceLastClose */
sh_sci_inbyte_nonblocking_polled, /* deviceRead */
sh_sci_write_support_polled, /* deviceWrite */
sh_sci_init, /* deviceInitialize */
sh_sci_write_polled, /* deviceWritePolled */
sh_sci_set_attributes, /* deviceSetAttributes */
false /* deviceOutputUsesInterrupts */
};
#if 1 /* (CONSOLE_USE_INTERRUPTS) */
#define SCI_FUNCTIONS &sh_sci_fns
#else
#define SCI_FUNCTIONS &sh_sci_fns_polled
#endif
static const struct termios term1 = {
0,
0,
0,
0,
{0},
B9600 | CS8,
B9600 | CS8
};
static const struct termios term2 = {
0,
0,
0,
0,
{0},
B115200 | CS8,
B115200 | CS8
};
console_tbl Console_Configuration_Ports[] = {
{
"/dev/sci0", /* sDeviceName */
SERIAL_CUSTOM, /* deviceType */
SCI_FUNCTIONS, /* pDeviceFns */
NULL, /* deviceProbe */
NULL, /* pDeviceFlow */
16, /* ulMargin */
8, /* ulHysteresis */
(void *)&term1, /* baud rate */ /* pDeviceParams */
SCI_SMR0, /* ulCtrlPort1 */
3, /* ulCtrlPort2 as IRQ priority level*/
TXI0_ISP_V, /* ulDataPort as TX end vector number*/
NULL, /* unused */ /* getRegister */
NULL, /* unused */ /* setRegister */
NULL, /* unused */ /* getData */
NULL, /* unused */ /* setData */
0, /* ulClock */
RXI0_ISP_V, /* ulIntVector as RX end vector number*/
},
{
"/dev/sci1", /* sDeviceName */
SERIAL_CUSTOM, /* deviceType */
SCI_FUNCTIONS, /* pDeviceFns */
NULL, /* deviceProbe */
NULL, /* pDeviceFlow */
16, /* ulMargin */
8, /* ulHysteresis */
(void *)&term2, /* baud rate */ /* pDeviceParams */
SCI_SMR1, /* ulCtrlPort1 */
3, /* ulCtrlPort2 as IRQ priority level*/
TXI1_ISP_V, /* ulDataPort as TX end vector number*/
NULL, /* unused */ /* getRegister */
NULL, /* unused */ /* setRegister */
NULL, /* unused */ /* getData */
NULL, /* unused */ /* setData */
0, /* ulClock */
RXI1_ISP_V, /* ulIntVector as RX end vector number*/
}
};
/*
* Declare some information used by the console driver
*/
#define NUM_CONSOLE_PORTS (sizeof(Console_Configuration_Ports)/sizeof(console_tbl))
unsigned long Console_Configuration_Count = NUM_CONSOLE_PORTS;

553
bsps/sh/gensh2/console/sci.c
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468
bsps/sh/gensh2/console/sci_termios.c
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/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Termios console serial driver.
*/
/*
* Based on SCI driver by Ralf Corsepius and John M. Mills
*
* Author: Radzislaw Galler <rgaller@et.put.poznan.pl>
*
* COPYRIGHT (c) 1989-2001.
* On-Line Applications Research Corporation (OAR).
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <bsp.h>
#include <stdlib.h>
#include <libchip/serial.h>
#include <libchip/sersupp.h>
#include <rtems/libio.h>
#include <rtems/iosupp.h>
#include <rtems/score/sh_io.h>
#include <rtems/score/ispsh7045.h>
#include <rtems/score/iosh7045.h>
#include <sh/sh7_sci.h>
#include <sh/sh7_pfc.h>
#include <sh/sci_termios.h>
/*
* Some handy macros
*/
#define SH_SCI_REG_DATA(_data, _minor, _register) \
(write8(_data, Console_Port_Tbl[_minor]->ulCtrlPort1 + (_register)))
#define SH_SCI_REG_FLAG(_flag, _minor, _register) \
(write8(read8(Console_Port_Tbl[_minor]->ulCtrlPort1 + (_register)) | (_flag), \
Console_Port_Tbl[_minor]->ulCtrlPort1 + (_register)))
#define SH_SCI_REG_MASK(_flag, _minor, _register) \
(write8(read8(Console_Port_Tbl[_minor]->ulCtrlPort1 + (_register)) & ~(_flag),\
Console_Port_Tbl[_minor]->ulCtrlPort1 + (_register)))
/*
* NOTE: Some SH variants have 3 sci devices
*/
#define SCI_MINOR_DEVICES 2
/*
* Automatically generated function imported from scitab.rel
*/
extern int _sci_get_brparms(
speed_t spd,
unsigned char *smr,
unsigned char *brr
);
/*
* Translate termios flags into SCI settings
*/
int sh_sci_set_attributes(
int minor,
const struct termios *t
)
{
uint8_t smr;
uint8_t brr;
int a;
tcflag_t c_cflag = t->c_cflag;
speed_t spd = t->c_ospeed;
if ( spd ) {
if ( _sci_get_brparms( spd, &smr, &brr ) != 0 )
return -1 ;
}
if ( c_cflag & CSIZE ) {
if ( c_cflag & CS8 )
smr &= ~SCI_SEVEN_BIT_DATA;
else if ( c_cflag & CS7 )
smr |= SCI_SEVEN_BIT_DATA;
else
return -1 ;
}
if ( c_cflag & CSTOPB )
smr |= SCI_STOP_BITS_2;
else
smr &= ~SCI_STOP_BITS_2;
if ( c_cflag & PARENB )
smr |= SCI_PARITY_ON ;
else
smr &= ~SCI_PARITY_ON ;
if ( c_cflag & PARODD )
smr |= SCI_ODD_PARITY ;
else
smr &= ~SCI_ODD_PARITY;
SH_SCI_REG_MASK((SCI_RE | SCI_TE), minor, SCI_SCR);
SH_SCI_REG_DATA(smr, minor, SCI_SMR);
SH_SCI_REG_DATA(brr, minor, SCI_BRR);
for (a=0; a < 10000L; a++) { /* Delay one bit */
__asm__ volatile ("nop");
}
SH_SCI_REG_FLAG((SCI_RE | SCI_TE), minor, SCI_SCR);
return 0;
}
/*
* Receive-data-full ISR
*
* The same routine for all interrupt sources of the same type.
*/
static rtems_isr sh_sci_rx_isr(rtems_vector_number vector)
{
int minor;
for (minor = 0; minor < Console_Port_Count; minor++) {
if (Console_Port_Tbl[minor]->ulIntVector == vector) {
char temp8;
/*
* FIXME: error handling should be added
*/
temp8 = read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_RDR);
rtems_termios_enqueue_raw_characters(
Console_Port_Data[minor].termios_data, &temp8, 1);
SH_SCI_REG_MASK(SCI_RDRF, minor, SCI_SSR);
break;
}
}
}
/*
* Transmit-data-empty ISR
*
* The same routine for all interrupt sources of the same type.
*/
static rtems_isr sh_sci_tx_isr(rtems_vector_number vector)
{
int minor;
for (minor = 0; minor < Console_Port_Count; minor++) {
if (Console_Port_Tbl[minor]->ulDataPort == vector) {
/*
* FIXME: Error handling should be added
*/
/*
* Mask end-of-transmission interrupt
*/
SH_SCI_REG_MASK(SCI_TIE, minor, SCI_SCR);
if (rtems_termios_dequeue_characters(
Console_Port_Data[minor].termios_data, 1)) {
/*
* More characters to be received - interrupt must be enabled
*/
SH_SCI_REG_FLAG(SCI_TIE, minor, SCI_SCR);
}
break;
}
}
}
/*
* Initialization of serial port
*/
void sh_sci_init(int minor)
{
uint16_t temp16;
/*
* set PFC registers to enable I/O pins
*/
if ((minor == 0)) {
temp16 = read16(PFC_PACRL2); /* disable SCK0, DMA, IRQ */
temp16 &= ~(PA2MD1 | PA2MD0);
temp16 |= (PA_TXD0 | PA_RXD0); /* enable pins for Tx0, Rx0 */
write16(temp16, PFC_PACRL2);
} else if (minor == 1) {
temp16 = read16(PFC_PACRL2); /* disable SCK1, DMA, IRQ */
temp16 &= ~(PA5MD1 | PA5MD0);
temp16 |= (PA_TXD1 | PA_RXD1); /* enable pins for Tx1, Rx1 */
write16(temp16, PFC_PACRL2);
}
/*
* Non-default hardware setup occurs in sh_sci_first_open
*/
}
/*
* Initialization of interrupts
*
* Interrupts can be started only after opening a device, so interrupt
* flags are set up in sh_sci_first_open function
*/
void sh_sci_initialize_interrupts(int minor)
{
rtems_isr_entry old_isr;
rtems_status_code status;
sh_sci_init(minor);
/*
* Disable IRQ of SCIx
*/
status = sh_set_irq_priority( Console_Port_Tbl[minor]->ulIntVector, 0);
if (status != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred(status);
SH_SCI_REG_MASK(SCI_RIE, minor, SCI_SCR);
/*
* Catch apropriate vectors
*/
status = rtems_interrupt_catch(
sh_sci_rx_isr,
Console_Port_Tbl[minor]->ulIntVector,
&old_isr);
if (status != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred(status);
status = rtems_interrupt_catch(
sh_sci_tx_isr,
Console_Port_Tbl[minor]->ulDataPort,
&old_isr);
if (status != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred(status);
/*
* Enable IRQ of SCIx
*/
SH_SCI_REG_FLAG(SCI_RIE, minor, SCI_SCR);
status = sh_set_irq_priority(
Console_Port_Tbl[minor]->ulIntVector,
Console_Port_Tbl[minor]->ulCtrlPort2);
if (status != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred(status);
}
/*
* Open entry point
* Sets up port and pins for selected sci.
*/
int sh_sci_first_open(
int major,
int minor,
void *arg
)
{
char temp8;
unsigned int a ;
/*
* check for valid minor number
*/
if (( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 )) {
return RTEMS_INVALID_NUMBER;
}
/*
* set up SCI registers
*/
/* Clear SCR - disable Tx and Rx */
SH_SCI_REG_DATA(0x00, minor, SCI_SCR);
/* set SMR and BRR - baudrate and format */
sh_sci_set_attributes(minor, Console_Port_Tbl[minor]->pDeviceParams);
for (a=0; a < 10000L; a++) { /* Delay */
__asm__ volatile ("nop");
}
write8((SCI_RE | SCI_TE), /* enable async. Tx and Rx */
Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SCR);
/*
* clear error flags
*/
temp8 = read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SSR);
while(temp8 & (SCI_RDRF | SCI_ORER | SCI_FER | SCI_PER)) {
/* flush input */
temp8 = read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_RDR);
/* clear some flags */
SH_SCI_REG_FLAG((SCI_RDRF|SCI_ORER|SCI_FER|SCI_PER), minor, SCI_SSR);
/* check if everything is OK */
temp8 = read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SSR);
}
/* Clear RDRF flag */
SH_SCI_REG_DATA(0x00, minor, SCI_TDR); /* force output */
/* Clear the TDRE bit */
SH_SCI_REG_FLAG(SCI_TDRE, minor, SCI_SSR);
/*
* Interrupt setup
*/
if (Console_Port_Tbl[minor]->pDeviceFns->deviceOutputUsesInterrupts) {
SH_SCI_REG_FLAG(SCI_RIE, minor, SCI_SCR);
}
return RTEMS_SUCCESSFUL ;
}
/*
* Close entry point
*/
int sh_sci_last_close(
int major,
int minor,
void *arg
)
{
/* FIXME: Incomplete */
/* Shutdown interrupts if necessary */
if (Console_Port_Tbl[minor]->pDeviceFns->deviceOutputUsesInterrupts)
{
SH_SCI_REG_MASK((SCI_TIE | SCI_RIE), minor, SCI_SCR);
}
return RTEMS_SUCCESSFUL ;
}
/*
* Interrupt aware write routine
*/
ssize_t sh_sci_write_support_int(
int minor,
const char *buf,
size_t len
)
{
if (!len)
return 0;
/*
* Put data into TDR and clear transmission-end-flag
*/
SH_SCI_REG_DATA(*buf, minor, SCI_TDR);
SH_SCI_REG_MASK(SCI_TDRE, minor, SCI_SSR);
/*
* Enable interrupt
*/
SH_SCI_REG_FLAG(SCI_TIE, minor, SCI_SCR);
return 1;
}
/*
* Polled write method
*/
ssize_t sh_sci_write_support_polled(
int minor,
const char *buf,
size_t len
)
{
int count = 0;
while(count < len) {
sh_sci_write_polled(minor, buf[count]);
count++;
}
/*
* Return number of bytes written
*/
return count;
}
/*
* Polled write of one character at a time
*/
void sh_sci_write_polled(
int minor,
char c
)
{
/*
* Wait for end of previous character
*/
while(!(read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SSR) & SCI_TDRE));
/*
* Send the character
*/
SH_SCI_REG_DATA(c, minor, SCI_TDR);
/*
* Clear TDRE flag
*/
SH_SCI_REG_MASK(SCI_TDRE, minor, SCI_SSR);
}
/*
* Non-blocking read
*/
int sh_sci_inbyte_nonblocking_polled(int minor)
{
char inbyte;
/*
* Check if input buffer is full
*/
if (read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SSR) & SCI_RDRF) {
inbyte = read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_RDR);
SH_SCI_REG_MASK(SCI_RDRF, minor, SCI_SSR);
/*
* Check for errors
*/
if (read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SSR) &
(SCI_ORER | SCI_FER | SCI_PER)) {
SH_SCI_REG_MASK((SCI_ORER | SCI_FER | SCI_PER), minor, SCI_SSR);
return -1;
}
return (int)inbyte;
}
return -1;
}

51
bsps/sh/gensh2/console/scitab.c
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@@ -1,51 +0,0 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (c) 2018 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* The content of this file was previously generated by the GPL licensed shgen
* tool during the BSP build for a configured clock frequency
* (CPU_CLOCK_RATE_HZ). All tools were removed from the RTEMS source repository
* at some point in time. Tools with a BSD-style license were moved to the
* RTEMS tools repository.
*/
#include <bsp.h>
int _sci_get_brparms(
unsigned int spd,
unsigned char *smr,
unsigned char *brr
)
{
if (spd != 9600) {
return -1;
}
*smr = 0x00;
*brr = 0x5f;
return 0;
}

100
bsps/sh/gensh2/include/bsp.h
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@@ -1,100 +0,0 @@
/**
* @file
*
* @ingroup RTEMSBSPsSH2
*
* @brief Global BSP definitions.
*/
/*
* generic sh2
*
* This include file contains all board IO definitions.
*/
/*
* Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Minor adaptations for sh2 by:
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*/
#ifndef LIBBSP_SH_GENSH2_BSP_H
#define LIBBSP_SH_GENSH2_BSP_H
/**
* @defgroup RTEMSBSPsSH2 SH-2
*
* @ingroup RTEMSBSPsSH
*
* @brief SH-2 Board Support Package.
*
* @{
*/
#include <rtems.h>
#include <bspopts.h>
#include <bsp/default-initial-extension.h>
#include <termios.h> /* for tcflag_t */
#include <sh/sci.h>
#ifdef __cplusplus
extern "C" {
#endif
#if 1
/* FIXME:
* These definitions will be no longer necessary if the old
* implementation of SCI driver will be droped
*/
#define BSP_CONSOLE_DEVNAME "/dev/sci0"
#define BSP_CONSOLE_MINOR_NUMBER ((rtems_device_minor_number) 0)
#define BSP_CONSOLE_DRIVER_TABLE_ENTRY DEVSCI_DRIVER_TABLE_ENTRY
#define BSP_CONSOLE_DEVICE_TERMIOS_HANDLERS (sh_sci_get_termios_handlers(TRUE))
#endif
/* Constants */
/*
* BSP methods that cross file boundaries.
*/
void bsp_hw_init(void);
int _sci_get_brparms(
unsigned int spd,
unsigned char *smr,
unsigned char *brr
);
#ifdef __cplusplus
}
#endif
/** @} */
#endif

1
bsps/sh/gensh2/include/bsp/irq.h
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#include <bsp/irq-default.h>

322
bsps/sh/gensh2/include/rtems/score/iosh7045.h
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@@ -1,322 +0,0 @@
/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
* contained no copyright notice.
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Modified to reflect on-chip registers for sh7045 processor, based on
* "Register.h" distributed with Hitachi's EVB7045F tutorials, and which
* contained no copyright notice:
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
* August, 1999
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*/
#ifndef __IOSH7045_H
#define __IOSH7045_H
/*
* After each line is explained whether the access is char short or long.
* The functions read/writeb, w, l, 8, 16, 32 can be found
* in exec/score/cpu/sh/sh_io.h
*
* 8 bit == char ( readb, writeb, read8, write8)
* 16 bit == short ( readw, writew, read16, write16 )
* 32 bit == long ( readl, writel, read32, write32 )
* JMM: Addresses noted "[char, ]short,word" are per Hitachi _SuperH_RISC_
* ENGINE_..Hardware_Manual; alignment access-restrictions may apply
*/
#define REG_BASE 0xFFFF8000
/* SCI0 Registers */
#define SCI_SMR0 (REG_BASE + 0x01a0) /*char: Serial mode ch 0 */
#define SCI_BRR0 (REG_BASE + 0x01a1) /*char: Bit rate ch 0 */
#define SCI_SCR0 (REG_BASE + 0x01a2) /*char: Serial control ch 0 */
#define SCI_TDR0 (REG_BASE + 0x01a3) /*char: Transmit data ch 0 */
#define SCI_SSR0 (REG_BASE + 0x01a4) /*char: Serial status ch 0 */
#define SCI_RDR0 (REG_BASE + 0x01a5) /*char: Receive data ch 0 */
#define SCI0_SMR SCI_SMR0
/* SCI1 Registers */
#define SCI_SMR1 (REG_BASE + 0x01b0) /* char: Serial mode ch 1 */
#define SCI_BRR1 (REG_BASE + 0x01b1) /* char: Bit rate ch 1 */
#define SCI_SCR1 (REG_BASE + 0x01b2) /* char: Serial control ch 1 */
#define SCI_TDR1 (REG_BASE + 0x01b3) /* char: Transmit data ch 1 */
#define SCI_SSR1 (REG_BASE + 0x01b4) /* char: Serial status ch 1 */
#define SCI_RDR1 (REG_BASE + 0x01b5) /* char: Receive data ch 1 */
#define SCI1_SMR SCI_SMR1
/* ADI */
/* High Speed A/D (Excluding A-Mask Part)*/
#define ADDRA (REG_BASE + 0x03F0) /* short */
#define ADDRB (REG_BASE + 0x03F2) /* short */
#define ADDRC (REG_BASE + 0x03F4) /* short */
#define ADDRD (REG_BASE + 0x03F6) /* short */
#define ADDRE (REG_BASE + 0x03F8) /* short */
#define ADDRF (REG_BASE + 0x03FA) /* short */
#define ADDRG (REG_BASE + 0x03FC) /* short */
#define ADDRH (REG_BASE + 0x03FE) /* short */
#define ADCSR (REG_BASE + 0x03E0) /* char */
#define ADCR (REG_BASE + 0x03E1) /* char */
/* Mid-Speed A/D (A-Mask part)*/
#define ADDRA0 (REG_BASE + 0x0400) /* char, short */
#define ADDRA0H (REG_BASE + 0x0400) /* char, short */
#define ADDRA0L (REG_BASE + 0x0401) /* char */
#define ADDRB0 (REG_BASE + 0x0402) /* char, short */
#define ADDRB0H (REG_BASE + 0x0402) /* char, short */
#define ADDRB0L (REG_BASE + 0x0403) /* char */
#define ADDRC0 (REG_BASE + 0x0404) /* char, short */
#define ADDRC0H (REG_BASE + 0x0404) /* char, short */
#define ADDRC0L (REG_BASE + 0x0405) /* char */
#define ADDRD0 (REG_BASE + 0x0406) /* char, short */
#define ADDRD0H (REG_BASE + 0x0406) /* char, short */
#define ADDRD0L (REG_BASE + 0x0407) /* char */
#define ADCSR0 (REG_BASE + 0x0410) /* char */
#define ADCR0 (REG_BASE + 0x0412) /* char */
#define ADDRA1 (REG_BASE + 0x0408) /* char, short */
#define ADDRA1H (REG_BASE + 0x0408) /* char, short */
#define ADDRA1L (REG_BASE + 0x0409) /* char */
#define ADDRB1 (REG_BASE + 0x040A) /* char, short */
#define ADDRB1H (REG_BASE + 0x040A) /* char, short */
#define ADDRB1L (REG_BASE + 0x040B) /* char */
#define ADDRC1 (REG_BASE + 0x040C) /* char, short */
#define ADDRC1H (REG_BASE + 0x040C) /* char, short */
#define ADDRC1L (REG_BASE + 0x040D) /* char */
#define ADDRD1 (REG_BASE + 0x040E) /* char, short */
#define ADDRD1H (REG_BASE + 0x040E) /* char, short */
#define ADDRD1L (REG_BASE + 0x040F) /* char */
#define ADCSR1 (REG_BASE + 0x0411) /* char */
#define ADCR1 (REG_BASE + 0x0413) /* char */
/*MTU SHARED*/
#define MTU_TSTR (REG_BASE + 0x0240) /* char, short, word */
#define MTU_TSYR (REG_BASE + 0x0241) /* char, short, word */
#define MTU_ICSR (REG_BASE + 0x03C0) /* input lev. CSR */
#define MTU_OCSR (REG_BASE + 0x03C0) /* output lev. CSR */
/*MTU CHANNEL 0*/
#define MTU_TCR0 (REG_BASE + 0x0260) /* char, short, word */
#define MTU_TMDR0 (REG_BASE + 0x0261) /* char, short, word */
#define MTU_TIORH0 (REG_BASE + 0x0262) /* char, short, word */
#define MTU_TIORL0 (REG_BASE + 0x0263) /* char, short, word */
#define MTU_TIER0 (REG_BASE + 0x0264) /* char, short, word */
#define MTU_TSR0 (REG_BASE + 0x0265) /* char, short, word */
#define MTU_TCNT0 (REG_BASE + 0x0266) /* short, word */
#define MTU_GR0A (REG_BASE + 0x0268) /* short, word */
#define MTU_GR0B (REG_BASE + 0x026A) /* short, word */
#define MTU_GR0C (REG_BASE + 0x026C) /* short, word */
#define MTU_GR0D (REG_BASE + 0x026E) /* short, word */
/*MTU CHANNEL 1*/
#define MTU_TCR1 (REG_BASE + 0x0280) /* char, short, word */
#define MTU_TMDR1 (REG_BASE + 0x0281) /* char, short, word */
#define MTU_TIOR1 (REG_BASE + 0x0282) /* char, short, word */
#define MTU_TIER1 (REG_BASE + 0x0284) /* char, short, word */
#define MTU_TSR1 (REG_BASE + 0x0285) /* char, short, word */
#define MTU_TCNT1 (REG_BASE + 0x0286) /* short, word */
#define MTU_GR1A (REG_BASE + 0x0288) /* short, word */
#define MTU_GR1B (REG_BASE + 0x028A) /* short, word */
/*MTU CHANNEL 2*/
#define MTU_TCR2 (REG_BASE + 0x02A0) /* char, short, word */
#define MTU_TMDR2 (REG_BASE + 0x02A1) /* char, short, word */
#define MTU_TIOR2 (REG_BASE + 0x02A2) /* char, short, word */
#define MTU_TIER2 (REG_BASE + 0x02A4) /* char, short, word */
#define MTU_TSR2 (REG_BASE + 0x02A5) /* char, short, word */
#define MTU_TCNT2 (REG_BASE + 0x02A6) /* short, word */
#define MTU_GR2A (REG_BASE + 0x02A8) /* short, word */
#define MTU_GR2B (REG_BASE + 0x02AA) /* short, word */
/*MTU CHANNELS 3-4 SHARED*/
#define MTU_TOER (REG_BASE + 0x020A) /* char, short, word */
#define MTU_TOCR (REG_BASE + 0x020B) /* char, short, word */
#define MTU_TGCR (REG_BASE + 0x020D) /* char, short, word */
#define MTU_TCDR (REG_BASE + 0x0214) /* short, word */
#define MTU_TDDR (REG_BASE + 0x0216) /* short, word */
#define MTU_TCNTS (REG_BASE + 0x0220) /* short, word */
#define MTU_TCBR (REG_BASE + 0x0222) /* short, word */
/*MTU CHANNEL 3*/
#define MTU_TCR3 (REG_BASE + 0x0200) /* char, short, word */
#define MTU_TMDR3 (REG_BASE + 0x0202) /* char, short, word */
#define MTU_TIORH3 (REG_BASE + 0x0204) /* char, short, word */
#define MTU_TIORL3 (REG_BASE + 0x0205) /* char, short, word */
#define MTU_TIER3 (REG_BASE + 0x0208) /* char, short, word */
#define MTU_TSR3 (REG_BASE + 0x022C) /* char, short, word */
#define MTU_TCNT3 (REG_BASE + 0x0210) /* short, word */
#define MTU_GR3A (REG_BASE + 0x0218) /* short, word */
#define MTU_GR3B (REG_BASE + 0x021A) /* short, word */
#define MTU_GR3C (REG_BASE + 0x0224) /* short, word */
#define MTU_GR3D (REG_BASE + 0x0226) /* short, word */
/*MTU CHANNEL 4*/
#define MTU_TCR4 (REG_BASE + 0x0201) /* char, short, word */
#define MTU_TMDR4 (REG_BASE + 0x0203) /* char, short, word */
#define MTU_TIOR4 (REG_BASE + 0x0206) /* char, short, word */
#define MTU_TIORH4 (REG_BASE + 0x0206) /* char, short, word */
#define MTU_TIORL4 (REG_BASE + 0x0207) /* char, short, word */
#define MTU_TIER4 (REG_BASE + 0x0209) /* char, short, word */
#define MTU_TSR4 (REG_BASE + 0x022D) /* char, short, word */
#define MTU_TCNT4 (REG_BASE + 0x0212) /* short, word */
#define MTU_GR4A (REG_BASE + 0x021C) /* short, word */
#define MTU_GR4B (REG_BASE + 0x021E) /* short, word */
#define MTU_GR4C (REG_BASE + 0x0228) /* short, word */
#define MTU_GR4D (REG_BASE + 0x022A) /* short, word */
/*DMAC CHANNELS 0-3 SHARED*/
#define DMAOR (REG_BASE + 0x06B0) /* short */
/*DMAC CHANNEL 0*/
#define DMA_SAR0 (REG_BASE + 0x06C0) /* short, word */
#define DMA_DAR0 (REG_BASE + 0x06C4) /* short, word */
#define DMA_DMATCR0 (REG_BASE + 0x06C8) /* short, word */
#define DMA_CHCR0 (REG_BASE + 0x06CC) /* short, word */
/*DMAC CHANNEL 1*/
#define DMA_SAR1 (REG_BASE + 0x06D0) /* short, word */
#define DMA_DAR1 (REG_BASE + 0x06D4) /* short, word */
#define DMA_DMATCR1 (REG_BASE + 0x06D8) /* short, wordt */
#define DMA_CHCR1 (REG_BASE + 0x06DC) /* short, word */
/*DMAC CHANNEL 3*/
#define DMA_SAR3 (REG_BASE + 0x06E0) /* short, word */
#define DMA_DAR3 (REG_BASE + 0x06E4) /* short, word */
#define DMA_DMATCR3 (REG_BASE + 0x06E8) /* short, word */
#define DMA_CHCR3 (REG_BASE + 0x06EC) /* short, word */
/*DMAC CHANNEL 4*/
#define DMA_SAR4 (REG_BASE + 0x06F0) /* short, word */
#define DMA_DAR4 (REG_BASE + 0x06F4) /* short, word */
#define DMA_DMATCR4 (REG_BASE + 0x06F8) /* short, word */
#define DMA_CHCR4 (REG_BASE + 0x06FC) /* short, word */
/*Data Transfer Controller*/
#define DTC_DTEA (REG_BASE + 0x0700) /* char, short, word */
#define DTC_DTEB (REG_BASE + 0x0701) /* char, short(?), word(?) */
#define DTC_DTEC (REG_BASE + 0x0702) /* char, short(?), word(?) */
#define DTC_DTED (REG_BASE + 0x0703) /* char, short(?), word(?) */
#define DTC_DTEE (REG_BASE + 0x0704) /* char, short(?), word(?) */
#define DTC_DTCSR (REG_BASE + 0x0706) /* char, short, word */
#define DTC_DTBR (REG_BASE + 0x0708) /* short, word */
/*Cache Memory*/
#define CAC_CCR (REG_BASE + 0x0740) /* char, short, word */
/*INTC*/
#define INTC_IPRA (REG_BASE + 0x0348) /* char, short, word */
#define INTC_IPRB (REG_BASE + 0x034A) /* char, short, word */
#define INTC_IPRC (REG_BASE + 0x034C) /* char, short, word */
#define INTC_IPRD (REG_BASE + 0x034E) /* char, short, word */
#define INTC_IPRE (REG_BASE + 0x0350) /* char, short, word */
#define INTC_IPRF (REG_BASE + 0x0352) /* char, short, word */
#define INTC_IPRG (REG_BASE + 0x0354) /* char, short, word */
#define INTC_IPRH (REG_BASE + 0x0356) /* char, short, word */
#define INTC_ICR (REG_BASE + 0x0358) /* char, short, word */
#define INTC_ISR (REG_BASE + 0x035A) /* char, short, word */
/*Flash (F-ZTAT)*/
#define FL_FLMCR1 (REG_BASE + 0x0580) /* Fl.Mem.Contr.Reg 1: char */
#define FL_FLMCR2 (REG_BASE + 0x0581) /* Fl.Mem.Contr.Reg 2: char */
#define FL_EBR1 (REG_BASE + 0x0582) /* Fl.Mem.Erase Blk.1: char */
#define FL_EBR2 (REG_BASE + 0x0584) /* Fl.Mem.Erase Blk.2: char */
#define FL_RAMER (REG_BASE + 0x0628) /* Ram Emul.Reg.- char,short,word */
/*UBC*/
#define UBC_BARH (REG_BASE + 0x0600) /* char, short, word */
#define UBC_BARL (REG_BASE + 0x0602) /* char, short, word */
#define UBC_BAMRH (REG_BASE + 0x0604) /* char, short, word */
#define UBC_BAMRL (REG_BASE + 0x0606) /* char, short, word */
#define UBC_BBR (REG_BASE + 0x0608) /* char, short, word */
/*BSC*/
#define BSC_BCR1 (REG_BASE + 0x0620) /* short */
#define BSC_BCR2 (REG_BASE + 0x0622) /* short */
#define BSC_WCR1 (REG_BASE + 0x0624) /* short */
#define BSC_WCR2 (REG_BASE + 0x0626) /* short */
#define BSC_DCR (REG_BASE + 0x062A) /* short */
#define BSC_RTCSR (REG_BASE + 0x062C) /* short */
#define BSC_RTCNT (REG_BASE + 0x062E) /* short */
#define BSC_RTCOR (REG_BASE + 0x0630) /* short */
/*WDT*/
#define WDT_R_TCSR (REG_BASE + 0x0610) /* rd: char */
#define WDT_R_TCNT (REG_BASE + 0x0611) /* rd: char */
#define WDT_R_RSTCSR (REG_BASE + 0x0613) /* rd: char */
#define WDT_W_TCSR (REG_BASE + 0x0610) /* wrt: short */
#define WDT_W_TCNT (REG_BASE + 0x0610) /* wrt: short */
#define WDT_W_RSTCSR (REG_BASE + 0x0612) /* wrt: short */
/*POWER DOWN STATE*/
#define PDT_SBYCR (REG_BASE + 0x0614) /* char */
/* Port I/O Control Registers */
#define IO_PADRH (REG_BASE + 0x0380) /* Port A Data Register */
#define IO_PADRL (REG_BASE + 0x0382) /* Port A Data Register */
#define IO_PBDR (REG_BASE + 0x0390) /* Port B Data Register */
#define IO_PCDR (REG_BASE + 0x0392) /* Port C Data Register */
#define IO_PDDRH (REG_BASE + 0x03A0) /* Port D Data Register */
#define IO_PDDRL (REG_BASE + 0x03A2) /* Port D Data Register */
#define IO_PEDR (REG_BASE + 0x03B0) /* Port E Data Register */
#define IO_PFDR (REG_BASE + 0x03B2) /* Port F Data Register */
/*Pin Function Control Register*/
#define PFC_PAIORH (REG_BASE + 0x0384) /* Port A I/O Reg. H */
#define PFC_PAIORL (REG_BASE + 0x0386) /* Port A I/O Reg. L */
#define PFC_PACRH (REG_BASE + 0x0388) /* Port A Ctr. Reg. H */
#define PFC_PACRL1 (REG_BASE + 0x038C) /* Port A Ctr. Reg. L1 */
#define PFC_PACRL2 (REG_BASE + 0x038E) /* Port A Ctr. Reg. L2 */
#define PFC_PBIOR (REG_BASE + 0x0394) /* Port B I/O Register */
#define PFC_PBCR1 (REG_BASE + 0x0398) /* Port B Ctr. Reg. R1 */
#define PFC_PBCR2 (REG_BASE + 0x039A) /* Port B Ctr. Reg. R2 */
#define PFC_PCIOR (REG_BASE + 0x0396) /* Port C I/O Register */
#define PFC_PCCR (REG_BASE + 0x039C) /* Port C Ctr. Reg. */
#define PFC_PDIORH (REG_BASE + 0x03A4) /* Port D I/O Reg. H */
#define PFC_PDIORL (REG_BASE + 0x03A6) /* Port D I/O Reg. L */
#define PFC_PDCRH1 (REG_BASE + 0x03A8) /* Port D Ctr. Reg. H1 */
#define PFC_PDCRH2 (REG_BASE + 0x03AA) /* Port D Ctr. Reg. H2 */
#define PFC_PDCRL (REG_BASE + 0x03AC) /* Port D Ctr. Reg. L */
#define PFC_PEIOR (REG_BASE + 0x03B4) /* Port E I/O Register */
#define PFC_PECR1 (REG_BASE + 0x03B8) /* Port E Ctr. Reg. 1 */
#define PFC_PECR2 (REG_BASE + 0x03BA) /* Port E Ctr. Reg. 2 */
#define PFC_IFCR (REG_BASE + 0x03C8) /* short */
/*Compare/Match Timer*/
#define CMT_CMSTR (REG_BASE + 0x3D0) /* Start Reg. char, short, word */
#define CMT_CMCSR0 (REG_BASE + 0x3D2) /* C0 SCR short, word */
#define CMT_CMCNT0 (REG_BASE + 0x3D4) /* C0 Counter char, short, word */
#define CMT_CMCOR0 (REG_BASE + 0x3D6) /* C0 Const.Reg. char, short, word */
#define CMT_CMCSR1 (REG_BASE + 0x3D8) /* C1 SCR short, word */
#define CMT_CMCNT1 (REG_BASE + 0x3DA) /* C1 Counter char, short, word */
#define CMT_CMCOR1 (REG_BASE + 0x3DC) /* C1 Const.Reg. char, short, word */
#endif

206
bsps/sh/gensh2/include/rtems/score/ispsh7045.h
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@@ -1,206 +0,0 @@
/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Modified to reflect isp entries for sh7045 processor:
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
*
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*/
#ifndef __CPU_ISPS_H
#define __CPU_ISPS_H
#ifdef __cplusplus
extern "C" {
#endif
extern void __ISR_Handler( uint32_t vector );
/*
* interrupt vector table offsets
*/
#define NMI_ISP_V 11
#define USB_ISP_V 12
#define IRQ0_ISP_V 64
#define IRQ1_ISP_V 65
#define IRQ2_ISP_V 66
#define IRQ3_ISP_V 67
#define IRQ4_ISP_V 68
#define IRQ5_ISP_V 69
#define IRQ6_ISP_V 70
#define IRQ7_ISP_V 71
#define DMA0_ISP_V 72
#define DMA1_ISP_V 76
#define DMA2_ISP_V 80
#define DMA3_ISP_V 84
#define MTUA0_ISP_V 88
#define MTUB0_ISP_V 89
#define MTUC0_ISP_V 90
#define MTUD0_ISP_V 91
#define MTUV0_ISP_V 92
#define MTUA1_ISP_V 96
#define MTUB1_ISP_V 97
#define MTUV1_ISP_V 100
#define MTUU1_ISP_V 101
#define MTUA2_ISP_V 104
#define MTUB2_ISP_V 105
#define MTUV2_ISP_V 108
#define MTUU2_ISP_V 109
#define MTUA3_ISP_V 112
#define MTUB3_ISP_V 113
#define MTUC3_ISP_V 114
#define MTUD3_ISP_V 115
#define MTUV3_ISP_V 116
#define MTUA4_ISP_V 120
#define MTUB4_ISP_V 121
#define MTUC4_ISP_V 122
#define MTUD4_ISP_V 123
#define MTUV4_ISP_V 124
#define ERI0_ISP_V 128
#define RXI0_ISP_V 129
#define TXI0_ISP_V 130
#define TEI0_ISP_V 131
#define ERI1_ISP_V 132
#define RXI1_ISP_V 133
#define TXI1_ISP_V 134
#define TEI1_ISP_V 135
#define ADI0_ISP_V 136
#define ADI1_ISP_V 137
#define DTC_ISP_V 140 /* Data Transfer Controller */
#define CMT0_ISP_V 144 /* Compare Match Timer */
#define CMT1_ISP_V 148
#define WDT_ISP_V 152 /* Wtachdog Timer */
#define CMI_ISP_V 153 /* BSC RAS interrupt */
#define OEI_ISP_V 156 /* I/O Port */
#define DREF_ISP_V CMI_ISP_V /* DRAM Refresh from BSC */
#if 0
#define PRT_ISP_V /* parity error - no equivalent */
#endif
/* dummy ISP */
extern void _dummy_isp( void );
/* Non Maskable Interrupt */
extern void _nmi_isp( void );
/* User Break Controller */
extern void _usb_isp( void );
/* External interrupts 0-7 */
extern void _irq0_isp( void );
extern void _irq1_isp( void );
extern void _irq2_isp( void );
extern void _irq3_isp( void );
extern void _irq4_isp( void );
extern void _irq5_isp( void );
extern void _irq6_isp( void );
extern void _irq7_isp( void );
/* DMA - Controller */
extern void _dma0_isp( void );
extern void _dma1_isp( void );
extern void _dma2_isp( void );
extern void _dma3_isp( void );
/* Interrupt Timer Unit */
/* Timer 0 */
extern void _mtua0_isp( void );
extern void _mtub0_isp( void );
extern void _mtuc0_isp( void );
extern void _mtud0_isp( void );
extern void _mtuv0_isp( void );
/* Timer 1 */
extern void _mtua1_isp( void );
extern void _mtub1_isp( void );
extern void _mtuv1_isp( void );
extern void _mtuu1_isp( void );
/* Timer 2 */
extern void _mtua2_isp( void );
extern void _mtub2_isp( void );
extern void _mtuv2_isp( void );
extern void _mtuu2_isp( void );
/* Timer 3 */
extern void _mtua3_isp( void );
extern void _mtub3_isp( void );
extern void _mtuc3_isp( void );
extern void _mtud3_isp( void );
extern void _mtuv3_isp( void );
/* Timer 4 */
extern void _mtua4_isp( void );
extern void _mtub4_isp( void );
extern void _mtuc4_isp( void );
extern void _mtud4_isp( void );
extern void _mtuv4_isp( void );
/* serial interfaces */
extern void _eri0_isp( void );
extern void _rxi0_isp( void );
extern void _txi0_isp( void );
extern void _tei0_isp( void );
extern void _eri1_isp( void );
extern void _rxi1_isp( void );
extern void _txi1_isp( void );
extern void _tei1_isp( void );
/* ADC */
extern void _adi0_isp( void );
extern void _adi1_isp( void );
/* Data Transfer Controller */
extern void _dtci_isp( void );
/* Compare Match Timer */
extern void _cmt0_isp( void );
extern void _cmt1_isp( void );
/* Watchdog Timer */
extern void _wdt_isp( void );
/* DRAM refresh control unit of bus state controller */
extern void _bsc_isp( void );
/* I/O Port */
extern void _oei_isp( void );
/* Parity Control Unit of the Bus State Controllers */
/* extern void _prt_isp( void ); */
#ifdef __cplusplus
}
#endif
#endif

84
bsps/sh/gensh2/include/sh/io_types.h
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@@ -1,84 +0,0 @@
/************************************************************************
*
* Data types and constants for Hitachi SH704X on-chip peripherals
*
* Author: John M.Mills (jmills@tga.com)
*
* COPYRIGHT (c) 1999, TGA Technologies, Norcross, GA, USA
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
* This file may be distributed as part of the RTEMS software item.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*
*
************************************************************************/
#ifndef _sh_io_types_h
#define _sh_io_types_h
#include <rtems/score/iosh7045.h>
#include <termios.h>
typedef enum {SCI0, SCI1} portNo;
typedef enum {eight, seven} dataBits;
typedef enum {one, two} stopBits;
typedef enum {even, odd} parity;
typedef struct {
portNo line;
int speed_ix;
dataBits dBits;
int parEn;
parity par;
int mulPro;
stopBits sBits;
} sci_setup_t;
typedef union{
unsigned char Reg; /* By Register */
struct { /* By Field */
unsigned char Sync :1; /* Async/Sync */
unsigned char DBts :1; /* Char.Length */
unsigned char ParEn :1; /* Parity En.*/
unsigned char Odd :1; /* Even/Odd */
unsigned char SBts :1; /* No.Stop Bits */
unsigned char MulP :1; /* Multi-Proc. */
unsigned char Dvsr :2; /* Clock Sel. */
} Fld;
} sci_smr_t;
typedef union {
unsigned char Reg; /* By Register */
struct { /* By Field */
unsigned char TIE :1; /* Tx.Int.En. */
unsigned char RIE :1; /* Rx.Int.En. */
unsigned char TE :1; /* Tx.En. */
unsigned char RE :1; /* Rx.En. */
unsigned char MPIE:1; /* Mult.Pro.Int.En. */
unsigned char TEIE:1; /* Tx.End Int.En. */
unsigned char CkSrc :2; /* Clock Src. */
} Fld;
} sci_scr_t;
typedef struct {
unsigned char n ;
unsigned char N ;
} sci_bitrate_t;
#endif /* _sh_io_types_h */

89
bsps/sh/gensh2/include/sh/sci.h
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@@ -1,89 +0,0 @@
/*
* Driver for the sh2 704x on-chip serial devices (sci)
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef _sh_sci_h
#define _sh_sci_h
#include <rtems/libio.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
* Devices are set to 9600 bps, 8 databits, 1 stopbit, no
* parity and asynchronous mode by default.
*
* NOTE:
* The onboard serial devices of the SH do not support hardware
* handshake.
*/
#define DEVSCI_DRIVER_TABLE_ENTRY \
{ sh_sci_initialize, sh_sci_open, sh_sci_close, sh_sci_read, \
sh_sci_write, sh_sci_control }
extern rtems_device_driver sh_sci_initialize(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
extern rtems_device_driver sh_sci_open(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
extern rtems_device_driver sh_sci_close(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
extern rtems_device_driver sh_sci_read(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
extern rtems_device_driver sh_sci_write(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
extern rtems_device_driver sh_sci_control(
rtems_device_major_number,
rtems_device_minor_number,
void *
);
extern const rtems_termios_callbacks * sh_sci_get_termios_handlers(
bool poll
);
#ifdef __cplusplus
}
#endif
#endif

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bsps/sh/gensh2/include/sh/sci_termios.h
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@@ -1,84 +0,0 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* COPYRIGHT (c) 1989-2001.
* On-Line Applications Research Corporation (OAR).
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef _SH_SCI_TERMIOS_H_
#define _SH_SCI_TERMIOS_H_
#ifdef __cplusplus
extern "C"{
#endif
int sh_sci_set_attributes(
int minor,
const struct termios *t
);
void sh_sci_initialize_interrupts(int minor);
void sh_sci_init(int minor);
ssize_t sh_sci_write_support_int(
int minor,
const char *buf,
size_t len
);
ssize_t sh_sci_write_support_polled(
int minor,
const char *buf,
size_t len
);
void sh_sci_write_polled(
int minor,
char c
);
int sh_sci_inbyte_nonblocking_polled(int minor);
int sh_sci_first_open(
int major,
int minor,
void *arg
);
int sh_sci_last_close(
int major,
int minor,
void *arg
);
#ifdef __cplusplus
}
#endif
#endif /* _SH_SCI_TERMIOS_H_ */

202
bsps/sh/gensh2/include/sh/sh7_pfc.h
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@@ -1,202 +0,0 @@
/*
* Bit values for the pin function controller of the Hitachi SH704x
*
* From Hitachi tutorials
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef _sh7_pfc_h
#define _sh7_pfc_h
#include <rtems/score/iosh7045.h>
/*
* Port A IO Registers (PAIORH, PAIORL)
* 1 => OUTPUT
* 0 => INPUT
*/
#define PAIORH PFC_PAIORH
#define PAIORL PFC_PAIORL
/* PAIORH */
#define PA23IOR 0x0080
#define PA22IOR 0x0040
#define PA21IOR 0x0020
#define PA20IOR 0x0010
#define PA19IOR 0x0008
#define PA18IOR 0x0004
#define PA17IOR 0x0002
#define PA16IOR 0x0001
/* PAIORL */
#define PA15IOR 0x8000
#define PA14IOR 0x4000
#define PA13IOR 0x2000
#define PA12IOR 0x1000
#define PA11IOR 0x0800
#define PA10IOR 0x0400
#define PA9IOR 0x0200
#define PA8IOR 0x0100
#define PA7IOR 0x0080
#define PA6IOR 0x0040
#define PA5IOR 0x0020
#define PA4IOR 0x0010
#define PA3IOR 0x0008
#define PA2IOR 0x0004
#define PA1IOR 0x0002
#define PA0IOR 0x0001
/*
* Port A Control Registers (PACRH, PACRL1, PACRL2)
* and mode bits
*/
#define PACRH PFC_PACRH
#define PACRL1 PFC_PACRL1
#define PACRL2 PFC_PACRL2
/* PACRH */
#define PA23MD0 0x4000
#define PA22MD0 0x1000
#define PA21MD0 0x0400
#define PA20MD0 0x0100
#define PA19MD1 0x0080
#define PA19MD0 0x0040
#define PA18MD1 0x0020
#define PA18MD0 0x0010
#define PA17MD0 0x0004
#define PA16MD0 0x0001
/* PACRL1 */
#define PA15MD0 0x4000
#define PA14MD0 0x1000
#define PA13MD0 0x0400
#define PA12MD0 0x0100
#define PA11MD0 0x0040
#define PA10MD0 0x0010
#define PA9MD1 0x0008
#define PA9MD0 0x0004
#define PA8MD1 0x0002
#define PA8MD0 0x0001
/* PACRL2 */
#define PA7MD1 0x8000
#define PA7MD0 0x4000
#define PA6MD1 0x2000
#define PA6MD0 0x1000
#define PA5MD1 0x0800
#define PA5MD0 0x0400
#define PA4MD0 0x0100
#define PA3MD0 0x0040
#define PA2MD1 0x0020
#define PA2MD0 0x0010
#define PA1MD0 0x0004
#define PA0MD0 0x0001
#define PA_TXD1 PA4MD0
#define PA_RXD1 PA3MD0
#define PA_TXD0 PA1MD0
#define PA_RXD0 PA0MD0
/*
* Port B IO Register (PBIOR)
*/
#define PBIOR PFC_PBIOR
#define PB15IOR 0x8000
#define PB14IOR 0x4000
#define PB13IOR 0x2000
#define PB12IOR 0x1000
#define PB11IOR 0x0800
#define PB10IOR 0x0400
#define PB9IOR 0x0200
#define PB8IOR 0x0100
#define PB7IOR 0x0080
#define PB6IOR 0x0040
#define PB5IOR 0x0020
#define PB4IOR 0x0010
#define PB3IOR 0x0008
#define PB2IOR 0x0004
#define PB1IOR 0x0002
#define PB0IOR 0x0001
/*
* Port B Control Register (PBCR1)
*/
#define PBCR1 PFC_PBCR1
#define PB15MD1 0x8000
#define PB15MD0 0x4000
#define PB14MD1 0x2000
#define PB14MD0 0x1000
#define PB13MD1 0x0800
#define PB13MD0 0x0400
#define PB12MD1 0x0200
#define PB12MD0 0x0100
#define PB11MD1 0x0080
#define PB11MD0 0x0040
#define PB10MD1 0x0020
#define PB10MD0 0x0010
#define PB9MD1 0x0008
#define PB9MD0 0x0004
#define PB8MD1 0x0002
#define PB8MD0 0x0001
#define PB15MD PB15MD1|PB14MD0
#define PB14MD PB14MD1|PB14MD0
#define PB13MD PB13MD1|PB13MD0
#define PB12MD PB12MD1|PB12MD0
#define PB11MD PB11MD1|PB11MD0
#define PB10MD PB10MD1|PB10MD0
#define PB9MD PB9MD1|PB9MD0
#define PB8MD PB8MD1|PB8MD0
#define PB_TXD1 PB11MD1
#define PB_RXD1 PB10MD1
#define PB_TXD0 PB9MD1
#define PB_RXD0 PB8MD1
/*
* Port B Control Register (PBCR2)
*/
#define PBCR2 PFC_PBCR2
#define PB7MD1 0x8000
#define PB7MD0 0x4000
#define PB6MD1 0x2000
#define PB6MD0 0x1000
#define PB5MD1 0x0800
#define PB5MD0 0x0400
#define PB4MD1 0x0200
#define PB4MD0 0x0100
#define PB3MD1 0x0080
#define PB3MD0 0x0040
#define PB2MD1 0x0020
#define PB2MD0 0x0010
#define PB1MD1 0x0008
#define PB1MD0 0x0004
#define PB0MD1 0x0002
#define PB0MD0 0x0001
#define PB7MD PB7MD1|PB7MD0
#define PB6MD PB6MD1|PB6MD0
#define PB5MD PB5MD1|PB5MD0
#define PB4MD PB4MD1|PB4MD0
#define PB3MD PB3MD1|PB3MD0
#define PB2MD PB2MD1|PB2MD0
#define PB1MD PB1MD1|PB1MD0
#define PB0MD PB0MD1|PB0MD0
#endif /* _sh7_pfc_h */

88
bsps/sh/gensh2/include/sh/sh7_sci.h
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/*
* Bit values for the serial control registers of the Hitachi SH704X
*
* From Hitachi tutorials
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef _sh7_sci_h
#define _sh7_sci_h
#include <rtems/score/iosh7045.h>
/*
* Serial mode register bits
*/
#define SCI_SYNC_MODE 0x80
#define SCI_SEVEN_BIT_DATA 0x40
#define SCI_PARITY_ON 0x20
#define SCI_ODD_PARITY 0x10
#define SCI_STOP_BITS_2 0x08
#define SCI_ENABLE_MULTIP 0x04
#define SCI_PHI_64 0x03
#define SCI_PHI_16 0x02
#define SCI_PHI_4 0x01
#define SCI_PHI_0 0x00
/*
* Serial register offsets, relative to SCI0_SMR or SCI1_SMR
*/
#define SCI_SMR 0x00
#define SCI_BRR 0x01
#define SCI_SCR 0x02
#define SCI_TDR 0x03
#define SCI_SSR 0x04
#define SCI_RDR 0x05
/*
* Serial control register bits
*/
#define SCI_TIE 0x80 /* Transmit interrupt enable */
#define SCI_RIE 0x40 /* Receive interrupt enable */
#define SCI_TE 0x20 /* Transmit enable */
#define SCI_RE 0x10 /* Receive enable */
#define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */
#define SCI_TEIE 0x04 /* Transmit end interrupt enable */
#define SCI_CKE1 0x02 /* Clock enable 1 */
#define SCI_CKE0 0x01 /* Clock enable 0 */
/*
* Serial status register bits
*/
#define SCI_TDRE 0x80 /* Transmit data register empty */
#define SCI_RDRF 0x40 /* Receive data register full */
#define SCI_ORER 0x20 /* Overrun error */
#define SCI_FER 0x10 /* Framing error */
#define SCI_PER 0x08 /* Parity error */
#define SCI_TEND 0x04 /* Transmit end */
#define SCI_MPB 0x02 /* Multiprocessor bit */
#define SCI_MPBT 0x01 /* Multiprocessor bit transfer */
/*
* INTC Priority Settings
*/
#define SCI0_IPMSK 0x00F0
#define SCI0_LOWIP 0x0010
#define SCI1_IPMSK 0x000F
#define SCI1_LOWIP 0x0001
#endif /* _sh7_sci_h */

1
bsps/sh/gensh2/include/tm27.h
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@@ -1 +0,0 @@
#include <rtems/tm27-default.h>

170
bsps/sh/gensh2/start/cpu_asm.c
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@@ -1,170 +0,0 @@
/*
* This file contains the basic algorithms for all assembly code used
* in an specific CPU port of RTEMS. These algorithms must be implemented
* in assembly language
*
* NOTE: This port uses a C file with inline assembler instructions
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
/*
* This is supposed to be an assembly file. This means that system.h
* and cpu.h should not be included in a "real" cpu_asm file. An
* implementation in assembly should include "cpu_asm.h"
*/
#include <rtems/score/cpu.h>
#include <rtems/score/isr.h>
#include <rtems/score/threaddispatch.h>
#include <rtems/score/sh.h>
#include <rtems/score/ispsh7045.h>
#include <rtems/score/iosh7045.h>
#include <rtems/score/sh_io.h>
unsigned long *_old_stack_ptr;
register unsigned long *stack_ptr __asm__ ("r15");
/*
* sh_set_irq_priority
*
* this function sets the interrupt level of the specified interrupt
*
* parameters:
* - irq : interrupt number
* - prio: priority to set for this interrupt number
*
* returns: 0 if ok
* -1 on error
*/
unsigned int sh_set_irq_priority(
unsigned int irq,
unsigned int prio )
{
uint32_t shiftcount;
uint32_t prioreg;
uint16_t temp16;
ISR_Level level;
/*
* first check for valid interrupt
*/
if (( irq > 156) || (irq < 64) || (_Hardware_isr_Table[irq] == _dummy_isp))
return -1;
/*
* check for valid irq priority
*/
if ( prio > 15 )
return -1;
/*
* look up appropriate interrupt priority register
*/
if ( irq > 71)
{
irq = irq - 72;
shiftcount = 12 - ((irq & ~0x03) % 16);
switch( irq / 16)
{
case 0: { prioreg = INTC_IPRC; break;}
case 1: { prioreg = INTC_IPRD; break;}
case 2: { prioreg = INTC_IPRE; break;}
case 3: { prioreg = INTC_IPRF; break;}
case 4: { prioreg = INTC_IPRG; break;}
case 5: { prioreg = INTC_IPRH; break;}
default: return -1;
}
}
else
{
shiftcount = 12 - 4 * ( irq % 4);
if ( irq > 67)
prioreg = INTC_IPRB;
else
prioreg = INTC_IPRA;
}
/*
* Set the interrupt priority register
*/
_ISR_Local_disable( level );
temp16 = read16( prioreg);
temp16 &= ~( 15 << shiftcount);
temp16 |= prio << shiftcount;
write16( temp16, prioreg);
_ISR_Local_enable( level );
return 0;
}
/*
* This routine provides the RTEMS interrupt management.
*/
void __ISR_Handler( uint32_t vector)
{
ISR_Level level;
_ISR_Local_disable( level );
_Thread_Dispatch_disable();
if ( _ISR_Nest_level == 0 )
{
/* Install irq stack */
_old_stack_ptr = stack_ptr;
stack_ptr = _CPU_Interrupt_stack_high;
}
_ISR_Nest_level++;
_ISR_Local_enable( level );
/* call isp */
if ( _ISR_Vector_table[ vector])
(*_ISR_Vector_table[ vector ])( vector );
_ISR_Local_disable( level );
_Thread_Dispatch_unnest( _Per_CPU_Get() );
_ISR_Nest_level--;
if ( _ISR_Nest_level == 0 )
/* restore old stack pointer */
stack_ptr = _old_stack_ptr;
_ISR_Local_enable( level );
if ( _ISR_Nest_level )
return;
if ( !_Thread_Dispatch_is_enabled() ) {
return;
}
if ( _Thread_Dispatch_necessary ) {
_Thread_Dispatch();
}
}

112
bsps/sh/gensh2/start/hw_init.c
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@@ -1,112 +0,0 @@
/*
* hw_init.c: set up sh7045F internal subunits
* Pin and memory assignments assume
* target is Hitachi SH7045F EVB ("lcevb")
*
* Provides two initialization routines:
* A. 'void early_hw_init(void)' for 'start.S'
* sets up hw needed for early RTEMS boot, and
* B. 'void bsp_hw_init(void)' for 'bspstart.c'
* sets up hardware used by this BSP.
*
* Author: John M. Mills (jmills@tga.com)
* COPYRIGHT(c) 2000, TGA Technologies, Inc
* Norcross, GA 30071 U.S.A
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Adapted from Hitachi EVB7045F tutorial files by:
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
*
*
* This file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*/
#include <bsp.h>
#include <stdlib.h>
#include <rtems/libio.h>
#include <rtems/score/sh_io.h>
#include <rtems/score/iosh7045.h>
/* exported entries */
extern void bsp_hw_init (void);
extern void early_hw_init (void);
/* called from 'start.S' on "#ifdef START_HW_INIT" */
void early_hw_init (void)
{
#ifdef STANDALONE_EVB
/* STANDALONE_EVB minimally sets up bus and DRAM here */
/* no STANDALONE_EVB accepts defaults from debug monitor */
/* FIXME: replace 'magic numbers' with logical names */
write16(0x2020, BSC_BCR1); /* Bus width access - 32-bit on CS1 */
write16(0xF3DD, BSC_BCR2); /* Idle cycles CS3-CS0 - 0 idle cycles*/
write16(0xFF3F, BSC_WCR1); /* Waits for CS3-CS0 - 3 waits on CS1 */
write16(0x000F, BSC_WCR2); /* Waits for DRAM/DMA access - default */
write16(0x0000, BSC_DCR); /* DRAM control - default */
write16(0x0000, BSC_RTCSR); /* DRAM refresh - default */
write16(0x0000, BSC_RTCNT); /* DRAM refresh counter - default*/
write16(0x0000, BSC_RTCOR); /* DRAM refresh compare match - default */
#endif
/* add early-init functions here */
};
/* to be called from 'bspstart.c' */
void bsp_hw_init (void)
{
uint16_t temp16;
#ifdef STANDALONE_EVB
/* STANDALONE_EVB: sets up PFC */
/* no STANDALONE_EVB: accepts defaults, adds RESET */
/* FIXME: replace 'magic numbers' */
write16(0x5000, PFC_PACRH); /* Pin function controller - WRHH, WRHL */
write16(0x1550, PFC_PACRL1); /* Pin fun. controller - WRH,WRL,RD,CS1 */
write16(0x0000, PFC_PBCR1); /* Pin function controller - default */
write16(0x2005, PFC_PBCR2); /* Pin fcn. controller - A18,A17,A16 */
write16(0xFFFF, PFC_PCCR); /* Pin function controller - A15-A0 */
write16(0x5555, PFC_PDCRH1); /* Pin function controller - D31-D24 */
write16(0x5555, PFC_PDCRH2); /* Pin function controller - D23-D16 */
write16(0xFFFF, PFC_PDCRL); /* Pin function controller - D15-D0 */
write16(0x0000, PFC_IFCR); /* Pin function controller - default */
write16(0x0000, PFC_PACRL2); /* default disconnects all I/O pins;*/
/* [re-connected by DEVICE_open()] */
#endif
/* default hardware setup for SH7045F EVB */
/* PFC: General I/O except pin 13 (reset): */
temp16 = read16(PFC_PECR1);
temp16 |= 0x0800;
write16(temp16, PFC_PECR1);
/* All I/O lines bits 7-0: */
write16(0x00, PFC_PECR2);
/* P5 (LED) out, all other pins in: */
temp16 = read16(PFC_PEIOR);
temp16 |= 0x0020;
write16(temp16, PFC_PEIOR);
}

310
bsps/sh/gensh2/start/ispsh7045.c
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@@ -1,310 +0,0 @@
/*
* This file contains the isp frames for the user interrupts.
* From these procedures __ISR_Handler is called with the vector number
* as argument.
*
* __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
* some releases of gcc doesn't properly handle #pragma interrupt, if a
* file contains both isrs and normal functions.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Modified to reflect isp entries for sh7045 processor:
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
* August, 1999
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*/
#include <rtems/score/cpu.h>
/*
* This is a exception vector table
*
* It has the same structure as the actual vector table (vectab)
*/
/* SH-2 ISR Table */
#include <rtems/score/ispsh7045.h>
CPU_ISR_raw_handler _Hardware_isr_Table[256]={
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* PWRon Reset, Maual Reset,...*/
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp,
_nmi_isp, _usb_isp, /* irq 11, 12*/
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp,
/* trapa 0 -31 */
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp, /* external H/W: irq 64-71 */
_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
_dma0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DMAC: irq 72-87*/
_dma1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dma2_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dma3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_mtua0_isp, _mtub0_isp, _mtuc0_isp, _mtud0_isp, /* MTUs: irq 88-127 */
_mtuv0_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_mtua1_isp, _mtub1_isp, _dummy_isp, _dummy_isp,
_mtuv1_isp, _mtuu1_isp, _dummy_isp, _dummy_isp,
_mtua2_isp, _mtub2_isp, _dummy_isp, _dummy_isp,
_mtuv2_isp, _mtuu2_isp, _dummy_isp, _dummy_isp,
_mtua3_isp, _mtub3_isp, _mtuc3_isp, _mtud3_isp,
_mtuv3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_mtua4_isp, _mtub4_isp, _mtuc4_isp, _mtud4_isp,
_mtuv4_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp, /* SCI0-1: irq 128-135*/
_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
_adi0_isp, _adi1_isp, _dummy_isp, _dummy_isp, /* ADC0-1: irq 136-139*/
_dtci_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DTU: irq 140-143 */
_cmt0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* CMT0-1: irq 144-151 */
_cmt1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_wdt_isp, /* WDT: irq 152*/
_bsc_isp, _dummy_isp, _dummy_isp, /* BSC: irq 153-155*/
_oei_isp, /* I/O Port: irq 156*/
};
#define Str(a)#a
/*
* Some versions of gcc and all version of egcs at least until egcs-1.1b
* are not able to handle #pragma interrupt correctly if more than 1 isr is
* contained in a file and when optimizing.
* We try to work around this problem by using the macro below.
*/
#define isp( name, number, func)\
__asm__ (".global _"Str(name)"\n\t"\
"_"Str(name)": \n\t"\
" mov.l r0,@-r15 \n\t"\
" mov.l r1,@-r15 \n\t"\
" mov.l r2,@-r15 \n\t"\
" mov.l r3,@-r15 \n\t"\
" mov.l r4,@-r15 \n\t"\
" mov.l r5,@-r15 \n\t"\
" mov.l r6,@-r15 \n\t"\
" mov.l r7,@-r15 \n\t"\
" mov.l r14,@-r15 \n\t"\
" sts.l pr,@-r15 \n\t"\
" sts.l mach,@-r15 \n\t"\
" sts.l macl,@-r15 \n\t"\
" mov r15,r14 \n\t"\
" mov.l "Str(name)"_v, r2 \n\t"\
" mov.l "Str(name)"_k, r1\n\t"\
" jsr @r1 \n\t"\
" mov r2,r4 \n\t"\
" mov r14,r15 \n\t"\
" lds.l @r15+,macl \n\t"\
" lds.l @r15+,mach \n\t"\
" lds.l @r15+,pr \n\t"\
" mov.l @r15+,r14 \n\t"\
" mov.l @r15+,r7 \n\t"\
" mov.l @r15+,r6 \n\t"\
" mov.l @r15+,r5 \n\t"\
" mov.l @r15+,r4 \n\t"\
" mov.l @r15+,r3 \n\t"\
" mov.l @r15+,r2 \n\t"\
" mov.l @r15+,r1 \n\t"\
" mov.l @r15+,r0 \n\t"\
" rte \n\t"\
" nop \n\t"\
" .align 2 \n\t"\
#name"_k: \n\t"\
".long "Str(func)"\n\t"\
#name"_v: \n\t"\
".long "Str(number));
/************************************************
* Dummy interrupt service procedure for
* interrupts being not allowed --> Trap 34
************************************************/
__asm__ (" .section .text\n\
.global __dummy_isp\n\
__dummy_isp:\n\
mov.l r14,@-r15\n\
mov r15, r14\n\
trapa #34\n\
mov.l @r15+,r14\n\
rte\n\
nop");
/*******************************************************************
* ISP Vector Table for sh7045 family of processors *
*******************************************************************/
/*****************************
* Non maskable interrupt
*****************************/
isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
/*****************************
* User break controller
*****************************/
isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
/*****************************
* External interrupts 0-7
*****************************/
isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler);
isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler);
isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler);
isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler);
isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
/*****************************
* DMA - controller
*****************************/
isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
/*****************************
* Match timer unit
*****************************/
/*****************************
* Timer 0
*****************************/
isp( _mtua0_isp, MTUA0_ISP_V, ___ISR_Handler);
isp( _mtub0_isp, MTUB0_ISP_V, ___ISR_Handler);
isp( _mtuc0_isp, MTUC0_ISP_V, ___ISR_Handler);
isp( _mtud0_isp, MTUD0_ISP_V, ___ISR_Handler);
isp( _mtuv0_isp, MTUV0_ISP_V, ___ISR_Handler);
/*****************************
* Timer 1
*****************************/
isp( _mtua1_isp, MTUA1_ISP_V, ___ISR_Handler);
isp( _mtub1_isp, MTUB1_ISP_V, ___ISR_Handler);
isp( _mtuv1_isp, MTUV1_ISP_V, ___ISR_Handler);
isp( _mtuu1_isp, MTUU1_ISP_V, ___ISR_Handler);
/*****************************
* Timer 2
*****************************/
isp( _mtua2_isp, MTUA2_ISP_V, ___ISR_Handler);
isp( _mtub2_isp, MTUB2_ISP_V, ___ISR_Handler);
isp( _mtuv2_isp, MTUV2_ISP_V, ___ISR_Handler);
isp( _mtuu2_isp, MTUU2_ISP_V, ___ISR_Handler);
/*****************************
* Timer 3
*****************************/
isp( _mtua3_isp, MTUA3_ISP_V, ___ISR_Handler);
isp( _mtub3_isp, MTUB3_ISP_V, ___ISR_Handler);
isp( _mtuc3_isp, MTUC3_ISP_V, ___ISR_Handler);
isp( _mtud3_isp, MTUD3_ISP_V, ___ISR_Handler);
isp( _mtuv3_isp, MTUV3_ISP_V, ___ISR_Handler);
/*****************************
* Timer 4
*****************************/
isp( _mtua4_isp, MTUA4_ISP_V, ___ISR_Handler);
isp( _mtub4_isp, MTUB4_ISP_V, ___ISR_Handler);
isp( _mtuc4_isp, MTUC4_ISP_V, ___ISR_Handler);
isp( _mtud4_isp, MTUD4_ISP_V, ___ISR_Handler);
isp( _mtuv4_isp, MTUV4_ISP_V, ___ISR_Handler);
/*****************************
* Serial interfaces
*****************************/
/*****************************
* Serial interface 0
*****************************/
isp( _eri0_isp, ERI0_ISP_V, ___ISR_Handler);
isp( _rxi0_isp, RXI0_ISP_V, ___ISR_Handler);
isp( _txi0_isp, TXI0_ISP_V, ___ISR_Handler);
isp( _tei0_isp, TEI0_ISP_V, ___ISR_Handler);
/*****************************
* Serial interface 1
*****************************/
isp( _eri1_isp, ERI1_ISP_V, ___ISR_Handler);
isp( _rxi1_isp, RXI1_ISP_V, ___ISR_Handler);
isp( _txi1_isp, TXI1_ISP_V, ___ISR_Handler);
isp( _tei1_isp, TEI1_ISP_V, ___ISR_Handler);
/******************************
* A/D converters
* ADC0-1
******************************/
isp( _adi0_isp, ADI0_ISP_V, ___ISR_Handler);
isp( _adi1_isp, ADI1_ISP_V, ___ISR_Handler);
/******************************
* Data transfer controller
******************************/
isp( _dtci_isp, DTC_ISP_V, ___ISR_Handler);
/******************************
* Counter match timer
******************************/
isp( _cmt0_isp, CMT0_ISP_V, ___ISR_Handler);
isp( _cmt1_isp, CMT1_ISP_V, ___ISR_Handler);
/******************************
* Watchdog timer
******************************/
isp( _wdt_isp, WDT_ISP_V, ___ISR_Handler);
/******************************
* DRAM refresh control unit
* of bus state controller
******************************/
isp( _bsc_isp, CMI_ISP_V, ___ISR_Handler);
/******************************
* I/O port
******************************/
isp( _oei_isp, OEI_ISP_V, ___ISR_Handler);
/*****************************
* Parity control unit of
* the bus state controller
* NOT PROVIDED IN SH-2
*****************************/
/* isp( _prt_isp, PRT_ISP_V, ___ISR_Handler); */

252
bsps/sh/gensh2/start/linkcmds
View File

@@ -1,252 +0,0 @@
/*
* This is an adapted linker script from egcs-1.0.1
*
* Memory layout for an SH7045F with main memory in area 2
* This memory layout it very similar to that used for Hitachi's
* EVB with CMON in FLASH
*
* NOTE: The ram start address may vary, all other start addresses are fixed
* Not suiteable for gdb's simulator
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Modified to reflect SH7045F processor and EVB:
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*/
OUTPUT_ARCH(sh)
ENTRY(_start)
STARTUP(start.o)
/* These assignments load code into SH7045F EVB SRAM for monitor debugging */
_RamBase = DEFINED(_RamBase) ? _RamBase : 0x00440000;
_RamSize = DEFINED(_RamSize) ? _RamSize : 512K;
_RamEnd = _RamBase + _RamSize;
_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
MEMORY
{
rom : o = 0x00400000, l = 0x00040000
ram : o = 0x00440000, l = 0x00080000
onchip_peri : o = 0xFFFF8000, l = 0x00000800
onchip_ram : o = 0xFFFFF000, l = 0x00001000
}
/* Sections are defined for RAM loading and monitor debugging */
SECTIONS
{
/* boot vector table */
.monvects 0x00400000 (NOLOAD): {
_monvects = . ;
} > rom
/* monitor play area */
.monram 0x00440000 (NOLOAD) :
{
_ramstart = .;
} > ram
/* monitor vector table */
.vects 0x00442000 (NOLOAD) : {
_vectab = . ;
*(.vects);
}
/* Read-only sections, merged into text segment: */
. = 0x00444000 ;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.gnu.version : { *(.gnu.version) }
.gnu.version_d : { *(.gnu.version_d) }
.gnu.version_r : { *(.gnu.version_r) }
.rela.dyn :
{
*(.rela.init)
*(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
*(.rela.fini)
*(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
*(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
*(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
*(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
*(.rela.ctors)
*(.rela.dtors)
*(.rela.got)
*(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
*(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
*(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
*(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
*(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
} >ram
.rel.text :
{ *(.rel.text) *(.rel.gnu.linkonce.t*) }
.rel.data :
{ *(.rel.data) *(.rel.gnu.linkonce.d*) }
.rel.rodata :
{ *(.rel.rodata*) *(.rel.gnu.linkonce.r*) }
.rel.got : { *(.rel.got) }
.rel.ctors : { *(.rel.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rel.init : { *(.rel.init) }
.rel.fini : { *(.rel.fini) }
.rel.bss : { *(.rel.bss) }
.rel.plt : { *(.rel.plt) }
.plt : { *(.plt) }
.text . :
{
_start = .;
*(.text*)
*(.stub)
/*
* Special FreeBSD sysctl sections.
*/
. = ALIGN (16);
___start_set_sysctl_set = .;
*(set_sysc*); /* set_sysctl_* but name is truncated by SH-coff */
___stop_set_sysctl_set = ABSOLUTE(.);
*(set_doma*); /* set_domain_* but name is truncated by SH-coff */
*(set_pseu*); /* set_pseudo_* but name is truncated by SH-coff */
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
*(.gnu.linkonce.t*)
} > ram
_etext = .;
PROVIDE (etext = .);
.init . : { KEEP(*(.init)) } > ram =0
.fini . : { KEEP(*(.fini)) } > ram =0
.ctors . : { KEEP(*(.ctors)) } > ram =0
.dtors . : { KEEP(*(.dtors)) } > ram =0
.rodata . : { *(.rodata*) KEEP (*(SORT(.rtemsroset.*))) *(.gnu.linkonce.r*) } > ram
.rodata1 . : { *(.rodata1) } > ram
.tdata : {
__TLS_Data_begin = .;
*(.tdata .tdata.* .gnu.linkonce.td.*)
__TLS_Data_end = .;
} > ram
.tbss : {
__TLS_BSS_begin = .;
*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
__TLS_BSS_end = .;
} > ram
__TLS_Data_size = __TLS_Data_end - __TLS_Data_begin;
__TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin;
__TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin;
__TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin;
__TLS_Size = __TLS_BSS_end - __TLS_Data_begin;
__TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. */
. = ALIGN(128) + (. & (128 - 1));
.data . :
{
*(.data*)
KEEP (*(SORT(.rtemsrwset.*)))
*(.gcc_exc*)
___EH_FRAME_BEGIN__ = .;
*(.eh_fram*)
___EH_FRAME_END__ = .;
LONG(0);
*(.gcc_except_table*)
*(.gnu.linkonce.d*)
CONSTRUCTORS
} > ram
.data1 . : { *(.data1) }
.got . : { *(.got.plt) *(.got) }
.dynamic . : { *(.dynamic) }
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
.sdata . : { *(.sdata) }
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.sbss . : { *(.sbss*) *(.scommon) }
.bss . :
{
*(.dynbss)
*(.bss .bss* .gnu.linkonce.b*)
*(COMMON)
} > ram
_end = . ;
PROVIDE (end = .);
.noinit (NOLOAD) : {
*(SORT_BY_NAME (SORT_BY_ALIGNMENT (.noinit*)))
} > ram
.rtemsstackinterrupt (NOLOAD) : {
*(.rtemsstack.interrupt)
} > onchip_ram
.rtemsstack (NOLOAD) : {
*(SORT(.rtemsstack.*))
} > ram
_WorkAreaBase = . ;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* These must appear regardless of . */
/* Addition to let linker know about custom section for GDB pretty-printing support. */
.debug_gdb_scripts 0 : { *(.debug_gdb_scripts) }
}

251
bsps/sh/gensh2/start/linkcmds.ram
View File

@@ -1,251 +0,0 @@
/*
* This is an adapted linker script from egcs-1.0.1
*
* Memory layout for an SH7045F with main memory in area 2
* This memory layout it very similar to that used for Hitachi's
* EVB with CMON in FLASH
*
* NOTE: The ram start address may vary, all other start addresses are fixed
* Not suiteable for gdb's simulator
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Modified to reflect SH7045F processor and EVB:
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*/
OUTPUT_ARCH(sh)
ENTRY(_start)
STARTUP(start.o)
/* These assignments load code into SH7045F EVB SRAM for monitor debugging */
_RamBase = DEFINED(_RamBase) ? _RamBase : 0x00440000;
_RamSize = DEFINED(_RamSize) ? _RamSize : 512K;
_RamEnd = _RamBase + _RamSize;
_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
MEMORY
{
rom : o = 0x00400000, l = 0x00040000
ram : o = 0x00440000, l = 0x00080000
onchip_peri : o = 0xFFFF8000, l = 0x00000800
onchip_ram : o = 0xFFFFF000, l = 0x00001000
}
/* Sections are defined for RAM loading and monitor debugging */
SECTIONS
{
/* boot vector table */
.monvects 0x00400000 (NOLOAD): {
_monvects = . ;
} > rom
/* monitor play area */
.monram 0x00440000 (NOLOAD) :
{
_ramstart = .;
} > ram
/* monitor vector table */
.vects 0x00442000 (NOLOAD) : {
_vectab = . ;
*(.vects);
}
/* Read-only sections, merged into text segment: */
. = 0x00444000 ;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.gnu.version : { *(.gnu.version) }
.gnu.version_d : { *(.gnu.version_d) }
.gnu.version_r : { *(.gnu.version_r) }
.rela.dyn :
{
*(.rela.init)
*(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
*(.rela.fini)
*(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
*(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
*(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
*(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
*(.rela.ctors)
*(.rela.dtors)
*(.rela.got)
*(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
*(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
*(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
*(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
*(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
} >ram
.rel.text :
{ *(.rel.text) *(.rel.gnu.linkonce.t*) }
.rel.data :
{ *(.rel.data) *(.rel.gnu.linkonce.d*) }
.rel.rodata :
{ *(.rel.rodata) *(.rel.gnu.linkonce.r*) }
.rel.got : { *(.rel.got) }
.rel.ctors : { *(.rel.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rel.init : { *(.rel.init) }
.rel.fini : { *(.rel.fini) }
.rel.bss : { *(.rel.bss) }
.rel.plt : { *(.rel.plt) }
.init : { *(.init) } =0
.plt : { *(.plt) }
.text . :
{
*(.text*)
*(.stub)
/*
* Special FreeBSD sysctl sections.
*/
. = ALIGN (16);
___start_set_sysctl_set = .;
*(set_sysc*); /* set_sysctl_* but name is truncated by SH-coff */
___stop_set_sysctl_set = ABSOLUTE(.);
*(set_doma*); /* set_domain_* but name is truncated by SH-coff */
*(set_pseudo_*);
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
*(.gnu.linkonce.t*)
} > ram
_etext = .;
PROVIDE (etext = .);
.fini . : { *(.fini) } > ram =0
.rodata . : { *(.rodata) KEEP (*(SORT(.rtemsroset.*))) *(.gnu.linkonce.r*) } > ram
.rodata1 . : { *(.rodata1) } > ram
.tdata : {
__TLS_Data_begin = .;
*(.tdata .tdata.* .gnu.linkonce.td.*)
__TLS_Data_end = .;
} > ram
.tbss : {
__TLS_BSS_begin = .;
*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
__TLS_BSS_end = .;
} > ram
__TLS_Data_size = __TLS_Data_end - __TLS_Data_begin;
__TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin;
__TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin;
__TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin;
__TLS_Size = __TLS_BSS_end - __TLS_Data_begin;
__TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. */
. = ALIGN(128) + (. & (128 - 1));
.data . :
{
*(.data)
KEEP (*(SORT(.rtemsrwset.*)))
*(.gnu.linkonce.d*)
CONSTRUCTORS
} > ram
.data1 . : { *(.data1) }
.ctors . :
{
___ctors = .;
*(.ctors)
___ctors_end = .;
}
.dtors . :
{
___dtors = .;
*(.dtors)
___dtors_end = .;
}
.got . : { *(.got.plt) *(.got) }
.dynamic . : { *(.dynamic) }
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
.sdata . : { *(.sdata) }
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.sbss . : { *(.sbss*) *(.scommon) }
.bss . :
{
*(.dynbss)
*(.bss .bss* .gnu.linkonce.b*)
*(COMMON)
} > ram
_end = . ;
PROVIDE (end = .);
.noinit (NOLOAD) : {
*(SORT_BY_NAME (SORT_BY_ALIGNMENT (.noinit*)))
} > ram
.rtemsstackidle (NOLOAD) : {
*(SORT(.rtemsstack.idle*))
} > ram
_WorkAreaBase = . ;
.rtemsstack (NOLOAD) : {
*(SORT(.rtemsstack.*))
} > onchip_ram
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* These must appear regardless of . */
}

256
bsps/sh/gensh2/start/linkcmds.rom
View File

@@ -1,256 +0,0 @@
/*
* This is an adapted linker script from egcs-1.0.1
*
* Memory layout for an SH7045F with main memory in area 2
* This memory layout it very similar to that used for Hitachi's
* EVB with CMON in FLASH
*
* NOTE: The ram start address may vary, all other start addresses are fixed
* Not suiteable for gdb's simulator
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Modified to reflect SH7045F processor and EVB:
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*/
OUTPUT_ARCH(sh)
ENTRY(_start)
STARTUP(start.o)
/* These asignments represent actual SH7045F EVB architecture */
_RamBase = DEFINED(_RamBase) ? _RamBase : 0x00400000;
_RamSize = DEFINED(_RamSize) ? _RamSize : 0x0008000;
_RamEnd = _RamBase + _RamSize;
_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
MEMORY
{
rom : o = 0x00000000, l = 0x00040000
ram : o = 0x00400000, l = 0x00080000
onchip_peri : o = 0xFFFF8000, l = 0x00000800
onchip_ram : o = 0xFFFFF000, l = 0x00001000
}
/* Sections are defined for RAM loading and monitor debugging */
SECTIONS
{
/* boot vector table */
.monvects 0x00000000 (NOLOAD): {
_monvects = . ;
} > rom
/* monitor play area */
.monram 0x00400000 (NOLOAD) :
{
_ramstart = .;
} > ram
/* monitor vector table */
.vects 0x00402000 (NOLOAD) : {
_vectab = . ;
*(.vects);
}
/* Read-only sections, merged into text segment: */
. = 0x00404000 ;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.gnu.version : { *(.gnu.version) }
.gnu.version_d : { *(.gnu.version_d) }
.gnu.version_r : { *(.gnu.version_r) }
.rela.dyn :
{
*(.rela.init)
*(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
*(.rela.fini)
*(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
*(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
*(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
*(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
*(.rela.ctors)
*(.rela.dtors)
*(.rela.got)
*(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
*(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
*(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
*(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
*(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
} >ram
.rel.text :
{ *(.rel.text) *(.rel.gnu.linkonce.t*) }
.rel.data :
{ *(.rel.data) *(.rel.gnu.linkonce.d*) }
.rel.rodata :
{ *(.rel.rodata) *(.rel.gnu.linkonce.r*) }
.rel.got : { *(.rel.got) }
.rel.ctors : { *(.rel.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rel.init : { *(.rel.init) }
.rel.fini : { *(.rel.fini) }
.rel.bss : { *(.rel.bss) }
.rel.plt : { *(.rel.plt) }
.init : { *(.init) } =0
.plt : { *(.plt) }
.text . :
{
*(.text*)
*(.stub)
/*
* Special FreeBSD sysctl sections.
*/
. = ALIGN (16);
___start_set_sysctl_set = .;
*(set_sysc*); /* set_sysctl_* but name is truncated by SH-coff */
___stop_set_sysctl_set = ABSOLUTE(.);
*(set_doma*); /* set_domain_* but name is truncated by SH-coff */
*(set_pseudo_*);
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
*(.gnu.linkonce.t*)
} > ram
_etext = .;
PROVIDE (etext = .);
.fini . : { *(.fini) } > ram =0
.rodata . : { *(.rodata) KEEP (*(SORT(.rtemsroset.*))) *(.gnu.linkonce.r*) } > ram
.rodata1 . : { *(.rodata1) } > ram
.tdata : {
__TLS_Data_begin = .;
*(.tdata .tdata.* .gnu.linkonce.td.*)
__TLS_Data_end = .;
} > ram
.tbss : {
__TLS_BSS_begin = .;
*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
__TLS_BSS_end = .;
} > ram
__TLS_Data_size = __TLS_Data_end - __TLS_Data_begin;
__TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin;
__TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin;
__TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin;
__TLS_Size = __TLS_BSS_end - __TLS_Data_begin;
__TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. */
. = ALIGN(128) + (. & (128 - 1));
.data . :
{
*(.data)
KEEP (*(SORT(.rtemsrwset.*)))
*(.gnu.linkonce.d*)
CONSTRUCTORS
} > ram
.data1 . : { *(.data1) }
.ctors . :
{
___ctors = .;
*(.ctors)
___ctors_end = .;
}
.dtors . :
{
___dtors = .;
*(.dtors)
___dtors_end = .;
}
.got . : { *(.got.plt) *(.got) }
.dynamic . : { *(.dynamic) }
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
.sdata . : { *(.sdata) }
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.sbss . : { *(.sbss*) *(.scommon) }
.bss . :
{
*(.dynbss)
*(.bss .bss* .gnu.linkonce.b*)
*(COMMON)
} > ram
_end = . ;
PROVIDE (end = .);
.noinit (NOLOAD) : {
*(SORT_BY_NAME (SORT_BY_ALIGNMENT (.noinit*)))
} > ram
.rtemsstackidle (NOLOAD) : {
*(SORT(.rtemsstack.idle*))
} > ram
_HeapStart = . ;
. = . + 1024 * 20 ;
PROVIDE( _HeapEnd = . );
_WorkAreaBase = . ;
.rtemsstack (NOLOAD) : {
*(SORT(.rtemsstack.*))
} > onchip_ram
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* These must appear regardless of . */
}

184
bsps/sh/gensh2/start/start.S
View File

@@ -1,184 +0,0 @@
/*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
* Modified to reflect Hitachi EDK SH7045F:
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
*
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*
* COPYRIGHT (c) 1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems/asm.h>
BEGIN_CODE
PUBLIC(start)
SYM (start):
! install the stack pointer
mov.l stack_k,r15
#ifdef START_HW_INIT /* from $RTEMS_BSP.cfg */
! Initialize minimal hardware
mov.l hw_init_k, r0
jsr @r0
nop !dead slot
#endif /* START_HW_INIT */
! zero out bss
mov.l edata_k,r0
mov.l end_k,r1
mov #0,r2
0:
mov.l r2,@r0
add #4,r0
cmp/ge r0,r1
bt 0b
! copy the vector table from rom to ram
mov.l vects_k,r0 ! vectab
mov #0,r1 ! address of boot vector table
mov #0,r2 ! number of bytes copied
mov.w vects_size,r3 ! size of entries in vectab
1:
mov.l @r1+,r4
mov.l r4,@r0
add #4,r0
add #1,r2
cmp/hi r3,r2
bf 1b
#ifndef STANDALONE_EVB
! overlay monitor vectors onto RTEMS table template
! code adapted from Hitachi EDK7045F User Manual: "Copyvect.s"
mova vects_k,r0
mov.l @r0, r1 ! Shadow vect tbl addr
stc vbr, r2 ! Original vect tbl addr
and #0, r0
mov r0, r4 ! 0 in r4 and r0
!trapa #32
or #0x80, r0
mov.l @(r0,r2), r3
mov.l r3, @(r0, r1)
mov r4, r0
!cpu addr err
or #0x24, r0
mov.l @(r0, r2), r3
mov.l r3, @(r0, r1)
mov r4, r0
!ill slot
or #0x18, r0
mov.l @(r0, r2), r3
mov.l r3, @(r0, r1)
mov r4, r0
!ill inst
or #0x10, r0
mov.l @(r0, r2), r3
mov.l r3, @(r0, r1)
mov r4, r0
!nmi
or #0x2c, r0
mov.l @(r0, r2), r3
mov.l r3, @(r0, r1)
mov r4, r0
!User brk
or #0x30, r0
mov.l @(r0, r2), r3
mov.l r3, @(r0, r1)
mov r4, r0
!sci0 err
or #0x80, r0
rotl r0
rotl r0
mov.l @(r0, r2), r3
mov.l r3, @(r0, r1)
mov r4, r0
!sci rx
or #0x81, r0
rotl r0
rotl r0
mov.l @(r0, r2), r3
mov.l r3, @(r0, r1)
stc vbr,r3 ! capture copy of monitor vbr
mov.l vbrtemp_k,r0
mov.l r3, @r0
mov.l vects_k,r0 ! point vbr to vectab
ldc r0,vbr
#endif /* ! STANDALONE_EVB */
! call the mainline
mov #0,r4 ! command line
mov.l main_k,r0
jsr @r0
nop
! call exit
mov r0,r4
mov.l exit_k,r0
jsr @r0
or r0,r0
mov.l vbrtemp_k,r0 ! restore original vbr
mov.l @r0,r3
ldc r3, vbr
trapa #13 ! UBR capture by monitor
nop !debug dead-slot target
END_CODE
.align 2
stack_k:
.long SYM(_ISR_Stack_area_end)
edata_k:
.long SYM(edata)
end_k:
.long SYM(end)
main_k:
.long SYM(boot_card)
exit_k:
.long SYM(exit)
#ifdef START_HW_INIT /* from $RTEMS_BSP.cfg */
hw_init_k:
.long SYM(early_hw_init)
#endif /* START_HW_INIT */
vbrtemp_k:
.long SYM(vbrtemp)
vects_k:
.long SYM(vectab)
vects_size:
.word 255
#ifdef __ELF__
.section .bss,"aw"
#else
.section .bss
#endif
SYM(vbrtemp):
.long 0x0

188
bsps/sh/gensh2/start/start.ram
View File

@@ -1,188 +0,0 @@
/*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Modified to reflect Hitachi EDK SH7045F:
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
*
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*/
#include "asm.h"
BEGIN_CODE
PUBLIC(start)
SYM (start):
! install the stack pointer
mov.l stack_k,r15
#ifdef START_HW_INIT /* from $RTEMS_BSP.cfg */
! Initialize minimal hardware
mov.l hw_init_k, r0
jsr @r0
nop !debug dead-slot target
#endif /* START_HW_INIT */
! zero out bss
mov.l edata_k,r0
mov.l end_k,r1
mov #0,r2
0:
mov.l r2,@r0
add #4,r0
cmp/ge r0,r1
bt 0b
nop !debug dead-slot target
! copy the vector table from rom to ram
mov.l vects_k,r0 ! vectab
mov #0,r1 ! address of boot vector table
mov #0,r2 ! number of bytes copied
mov.w vects_size,r3 ! size of entries in vectab
1:
mov.l @r1+,r4
mov.l r4,@r0
add #4,r0
add #1,r2
cmp/hi r3,r2
bf 1b
nop !debug dead-slot target
! overlay monitor vectors onto RTEMS table template
! code adapted from Hitachi EDK7045F User Manual: "Copyvect.s"
mova vects_k,r0
mov.l @r0, r1 ! Shadow vect tbl addr
stc vbr, r2 ! Original vect tbl addr
and #0, r0
mov r0, r4 ! 0 in r4 and r0
!trapa #32
or #0x80, r0
mov.l @(r0,r2), r3
mov.l r3, @(r0, r1)
mov r4, r0
!cpu addr err
or #0x24, r0
mov.l @(r0, r2), r3
mov.l r3, @(r0, r1)
mov r4, r0
!ill slot
or #0x18, r0
mov.l @(r0, r2), r3
mov.l r3, @(r0, r1)
mov r4, r0
!ill inst
or #0x10, r0
mov.l @(r0, r2), r3
mov.l r3, @(r0, r1)
mov r4, r0
!nmi
or #0x2c, r0
mov.l @(r0, r2), r3
mov.l r3, @(r0, r1)
mov r4, r0
!User brk
or #0x30, r0
mov.l @(r0, r2), r3
mov.l r3, @(r0, r1)
mov r4, r0
!sci0 err
or #0x80, r0
rotl r0
rotl r0
mov.l @(r0, r2), r3
mov.l r3, @(r0, r1)
mov r4, r0
!sci rx
or #0x81, r0
rotl r0
rotl r0
mov.l @(r0, r2), r3
mov.l r3, @(r0, r1)
stc vbr,r3 ! capture copy of monitor vbr
mov.l vbrtemp_k,r0
mov.l r3, @r0
mov.l vects_k,r0 ! point vbr to vectab
ldc r0,vbr
! call the mainline
mov #0,r4 ! argc
mov #0,r5 ! argv - can place in dead slot
mov.l main_k,r0
jsr @r0
nop !debug dead-slot target
! call exit
mov r0,r4
mov.l exit_k,r0
or r0,r0
jsr @r0
nop !debug dead-slot target
mov.l vbrtemp_k,r0 ! restore original vbr
mov.l @r0,r3
ldc r3, vbr
trapa #13 ! UBR capture by monitor
nop !debug dead-slot target
END_CODE
.align 2
stack_k:
.long SYM(_ISR_Stack_area_end)
edata_k:
.long SYM(edata)
end_k:
.long SYM(end)
main_k:
.long SYM(boot_card)
exit_k:
.long SYM(exit)
#ifdef START_HW_INIT /* from $RTEMS_BSP.cfg */
hw_init_k:
.long SYM(hw_initialize)
#endif /* START_HW_INIT */
vbrtemp_k:
.long SYM(vbrtemp)
vects_k:
.long SYM(vectab)
vects_size:
.word 255
#ifdef __ELF__
.section .bss,"aw"
#else
.section .bss
#endif
SYM(vbrtemp):
.long 0x0

83
bsps/sh/gensh2/start/start.rom
View File

@@ -1,83 +0,0 @@
/*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include "asm.h"
BEGIN_CODE
PUBLIC(start)
SYM (start):
! install the stack pointer
mov.l stack_k,r15
! zero out bss
mov.l edata_k,r0
mov.l end_k,r1
mov #0,r2
0:
mov.l r2,@r0
add #4,r0
cmp/ge r0,r1
bt 0b
! copy the vector table from rom to ram
mov.l vects_k,r0 ! vectab
mov #0,r1 ! address of boot vector table
mov #0,r2 | number of bytes copied
mov.w vects_size,r3 ! size of entries in vectab
1:
mov.l @r1+,r4
mov.l r4,@r0
add #4,r0
add #1,r2
cmp/hi r3,r2
bf 1b
mov.l vects_k,r0 ! update vbr to point to vectab
ldc r0,vbr
! call the mainline
mov #0,r4 ! argc
mov.l main_k,r0
jsr @r0
mov #0,r5 ! argv
! call exit
mov r0,r4
mov.l exit_k,r0
jsr @r0
or r0,r0
END_CODE
.align 2
stack_k:
.long SYM(_ISR_Stack_area_end)
edata_k:
.long SYM(edata)
end_k:
.long SYM(end)
main_k:
.long SYM(boot_card)
exit_k:
.long SYM(exit)
vects_k:
.long SYM(vectab)
vects_size:
.word 255

100
bsps/sh/gensh4/README.md
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@@ -1,100 +0,0 @@
gensh4
======
Author: Alexandra Kossovsky <sasha@oktet.ru>
Victor Vengerov <vvv@oktet.ru>
OKTET Ltd, http://www.oktet.ru
```
BSP NAME: generic SH4 (gensh4)
BOARD: n/a
BUS: n/a
CPU FAMILY: Hitachi SH
CPU: SH 7750
COPROCESSORS: none
MODE: n/a
DEBUG MONITOR: gdb (sh-ipl-g+ loader/stub)
```
PERIPHERALS
-----------
```
TIMERS: on-chip
SERIAL PORTS: on-chip (with 2 ports)
REAL-TIME CLOCK: none
DMA: not used
VIDEO: none
SCSI: none
NETWORKING: none
```
DRIVER INFORMATION
------------------
```
CLOCK DRIVER: on-chip timer
IOSUPP DRIVER: default
SHMSUPP: n/a
TIMER DRIVER: on-chip timer
TTY DRIVER: /dev/console
```
STDIO
-----
```
PORT: /dev/console
ELECTRICAL: n/a
BAUD: n/a
BITS PER CHARACTER: n/a
PARITY: n/a
STOP BITS: n/a
```
NOTES
-----
(1) Driver for the on-chip serial devices is tested only with 1st serial
port. We cannot test it on serial port with FIFO.
Console driver has 4 modes -- 2 with termios (interrupt-driven &
poll-driven modes), one raw mode working with serial port directly,
without termios, and one mode working with gdb stub (using 'trapa'
handled by sh-ipl-g+).
(2) The present 'hw_init.c' file provides 'early_hw_init'(void) which
is normally called from 'start.S' to provide such minimal HW setup.
It is written in C, but it should be noted that any accesses to memory
(except hardware registers) are prohibited until hardware not
initialized. To avoid access to stack, hw_init.c should be compiled with
-fomit-frame-pointer.
hw_init.c also provides 'bsp_cache_on'(void) normally called from
'start.S' after copying all data from rom to ram.
(3) In 'configure.ac' you should properly set 'CPU_CLOCK_RATE_HZ'.
It is frequency fed to the CPU core (external clock frequency can be
multiplied by on-chip PLLs). Please note that it is not a frequency of
external oscillator! See Hardware Manual, section 10, for details.
Global variable 'SH4_CPU_HZ_Frequency' is declared in 'bsp.h' and
initilized in 'bspstart.c' to ${HZ}. It is used by sci driver,
which exists in 'libcpu/sh/sh7750'.
(4) There is SH4_WITH_IPL macro in console driver 'sh4_uart.h'.
When it is defined, the application works under
gdb-stub (it is able to turn cache on by 'trapa', use gdb mode in console
driver and get out from gdb to use other console modes).
(5) There are 3 likcmds:
- linkcmds: code and data loaded to RAM. No code/data moving required.
- linkcmds.rom: code executed from the ROM; .data section moved to the
RAM on initialization.
- linkcmds.rom2ram: execution started from the ROM (after reset); code
and data moved to the RAM and execution continued from RAM.
The same 'start.S' is used for all cases.
(6) You can get gdb stub from http://www.oktet.ru/download/sh4/sh-ipl.tar.gz.
It is based on 'sh-ipl-g+' package used in sh-linux project.
(7) This project was done in cooperation with Transas company
http://www.transas.com

269
bsps/sh/gensh4/btimer/btimer.c
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@@ -1,269 +0,0 @@
/**
* @file
* @brief Timer driver for the Hitachi SH 7750
*/
/*
* Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
* Author: Victor V. Vengerov <vvv@oktet.ru>
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <rtems/btimer.h>
#include <rtems/score/sh_io.h>
#include <rtems/score/iosh7750.h>
extern uint32_t bsp_clicks_per_second;
#ifndef TIMER_PRIO
#define TIMER_PRIO 15
#endif
/* Timer prescaler division ratio */
#define TIMER_PRESCALER 4
#define TCR1_TPSC SH7750_TCR_TPSC_DIV4
#define TIMER_VECTOR SH7750_EVT_TO_NUM(SH7750_EVT_TUNI1)
extern rtems_isr timerisr(void);
static uint32_t Timer_interrupts;
/* Counter should be divided to this value to obtain time in microseconds */
static uint32_t microseconds_divider;
/* Interrupt period in microseconds */
static uint32_t microseconds_per_int;
bool benchmark_timer_find_average_overhead;
/* benchmark_timer_initialize --
* Initialize Timer 1 to operate as a RTEMS benchmark timer:
* - determine timer clock frequency
* - install timer interrupt handler
* - configure the Timer 1 hardware
* - start the timer
*
* PARAMETERS:
* none
*
* RETURNS:
* none
*/
void
benchmark_timer_initialize(void)
{
uint8_t temp8;
uint16_t temp16;
rtems_interrupt_level level;
rtems_isr *ignored;
int cpudiv = 1;
int tidiv = 1;
Timer_interrupts = 0;
rtems_interrupt_disable(level);
/* Get CPU frequency divider from clock unit */
switch (read16(SH7750_FRQCR) & SH7750_FRQCR_IFC)
{
case SH7750_FRQCR_IFCDIV1:
cpudiv = 1;
break;
case SH7750_FRQCR_IFCDIV2:
cpudiv = 2;
break;
case SH7750_FRQCR_IFCDIV3:
cpudiv = 3;
break;
case SH7750_FRQCR_IFCDIV4:
cpudiv = 4;
break;
case SH7750_FRQCR_IFCDIV6:
cpudiv = 6;
break;
case SH7750_FRQCR_IFCDIV8:
cpudiv = 8;
break;
default:
rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
}
/* Get peripheral module frequency divider from clock unit */
switch (read16(SH7750_FRQCR) & SH7750_FRQCR_PFC)
{
case SH7750_FRQCR_PFCDIV2:
tidiv = 2 * TIMER_PRESCALER;
break;
case SH7750_FRQCR_PFCDIV3:
tidiv = 3 * TIMER_PRESCALER;
break;
case SH7750_FRQCR_PFCDIV4:
tidiv = 4 * TIMER_PRESCALER;
break;
case SH7750_FRQCR_PFCDIV6:
tidiv = 6 * TIMER_PRESCALER;
break;
case SH7750_FRQCR_PFCDIV8:
tidiv = 8 * TIMER_PRESCALER;
break;
default:
rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
}
microseconds_divider = bsp_clicks_per_second * cpudiv / (tidiv * 1000000);
microseconds_per_int = 0xFFFFFFFF / microseconds_divider;
/*
* Hardware specific initialization
*/
/* Stop the Timer 0 */
temp8 = read8(SH7750_TSTR);
temp8 &= ~SH7750_TSTR_STR1;
write8(temp8, SH7750_TSTR);
/* Establish interrupt handler */
_CPU_ISR_install_raw_handler( TIMER_VECTOR, timerisr, &ignored );
/* Reset timer constant and counter */
write32(0xFFFFFFFF, SH7750_TCOR1);
write32(0xFFFFFFFF, SH7750_TCNT1);
/* Select timer mode */
write16(
SH7750_TCR_UNIE | /* Enable Underflow Interrupt */
SH7750_TCR_CKEG_RAISE | /* Count on rising edge */
TCR1_TPSC, /* Timer prescaler ratio */
SH7750_TCR1);
/* Set timer interrupt priority */
temp16 = read16(SH7750_IPRA);
temp16 = (temp16 & ~SH7750_IPRA_TMU1) | (TIMER_PRIO << SH7750_IPRA_TMU1_S);
write16(temp16, SH7750_IPRA);
rtems_interrupt_enable(level);
/* Start the Timer 1 */
temp8 = read8(SH7750_TSTR);
temp8 |= SH7750_TSTR_STR1;
write8(temp8, SH7750_TSTR);
}
/*
* The following controls the behavior of benchmark_timer_read().
*
* AVG_OVERHEAD is the overhead for starting and stopping the timer. It
* is usually deducted from the number returned.
*
* LEAST_VALID is the lowest number this routine should trust. Numbers
* below this are "noise" and zero is returned.
*/
#define AVG_OVERHEAD 0 /* It typically takes X.X microseconds */
/* (Y countdowns) to start/stop the timer. */
/* This value is in microseconds. */
#define LEAST_VALID 0 /* 20 */ /* Don't trust a clicks value lower than this */
/* benchmark_timer_read --
* Read timer value in microsecond units since timer start.
*
* PARAMETERS:
* none
*
* RETURNS:
* number of microseconds since timer has been started
*/
benchmark_timer_t
benchmark_timer_read(void)
{
uint32_t clicks;
uint32_t ints;
uint32_t total;
rtems_interrupt_level level;
uint32_t tcr;
rtems_interrupt_disable(level);
clicks = 0xFFFFFFFF - read32(SH7750_TCNT1);
tcr = read32(SH7750_TCR1);
ints = Timer_interrupts;
rtems_interrupt_enable(level);
/* Handle the case when timer overflowed but interrupt was not processed */
if ((clicks > 0xFF000000) && ((tcr & SH7750_TCR_UNF) != 0))
{
ints++;
}
total = microseconds_per_int * ints + (clicks / microseconds_divider);
if ( benchmark_timer_find_average_overhead )
return total; /* in microsecond units */
else
{
if ( total < LEAST_VALID )
return 0; /* below timer resolution */
/*
* Somehow convert total into microseconds
*/
return (total - AVG_OVERHEAD) ;
}
}
/* benchmark_timer_disable_subtracting_average_overhead --
* This routine is invoked by the "Check Timer" (tmck) test in the
* RTEMS Timing Test Suite. It makes the benchmark_timer_read routine not
* subtract the overhead required to initialize and read the benchmark
* timer.
*
* PARAMETERS:
* find_flag - boolean flag, true if overhead must not be subtracted.
*
* RETURNS:
* none
*/
void
benchmark_timer_disable_subtracting_average_overhead(bool find_flag)
{
benchmark_timer_find_average_overhead = find_flag;
}
/* timerisr --
* Timer interrupt handler routine. This function invoked on timer
* underflow event; once per 2^32 clocks. It should reset the timer
* event and increment timer interrupts counter.
*/
void
timerisr(void)
{
uint8_t temp8;
/* reset the flags of the status register */
temp8 = read8(SH7750_TCR1) & ~SH7750_TCR_UNF;
write8(temp8, SH7750_TCR1);
Timer_interrupts += 1;
}

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