From 00b074b124ac667c735914b7720bf0a917dfc5ab Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Thu, 19 Dec 2024 16:24:06 -0600 Subject: [PATCH] SuperH (sh): Remove obsolete architecture Updates rtems/rtos/rtems#5022 --- bsps/sh/gensh1/README.md | 59 - bsps/sh/gensh1/btimer/btimer.c | 195 -- bsps/sh/gensh1/clock/ckinit.c | 294 --- bsps/sh/gensh1/clock/delay.c | 51 - bsps/sh/gensh1/config/gensh1-testsuite.tcfg | 13 - bsps/sh/gensh1/config/gensh1.cfg | 22 - bsps/sh/gensh1/console/sci.c | 352 ---- bsps/sh/gensh1/console/scitab.c | 51 - bsps/sh/gensh1/include/bsp.h | 86 - bsps/sh/gensh1/include/bsp/irq.h | 1 - bsps/sh/gensh1/include/rtems/score/iosh7032.h | 220 --- .../sh/gensh1/include/rtems/score/ispsh7032.h | 160 -- bsps/sh/gensh1/include/sh/sci.h | 82 - bsps/sh/gensh1/include/sh/sh7_pfc.h | 115 -- bsps/sh/gensh1/include/sh/sh7_sci.h | 79 - bsps/sh/gensh1/include/tm27.h | 1 - bsps/sh/gensh1/start/cpu_asm.c | 169 -- bsps/sh/gensh1/start/ispsh7032.c | 248 --- bsps/sh/gensh1/start/linkcmds | 241 --- bsps/sh/gensh1/start/start.S | 82 - bsps/sh/gensh2/README.md | 224 --- bsps/sh/gensh2/btimer/btimer.c | 191 -- bsps/sh/gensh2/clock/ckinit.c | 234 --- bsps/sh/gensh2/config/gensh2-testsuite.tcfg | 13 - bsps/sh/gensh2/config/gensh2.cfg | 21 - bsps/sh/gensh2/console/config.c | 149 -- bsps/sh/gensh2/console/sci.c | 553 ------ bsps/sh/gensh2/console/sci_termios.c | 468 ----- bsps/sh/gensh2/console/scitab.c | 51 - bsps/sh/gensh2/include/bsp.h | 100 - bsps/sh/gensh2/include/bsp/irq.h | 1 - bsps/sh/gensh2/include/rtems/score/iosh7045.h | 322 ---- .../sh/gensh2/include/rtems/score/ispsh7045.h | 206 --- bsps/sh/gensh2/include/sh/io_types.h | 84 - bsps/sh/gensh2/include/sh/sci.h | 89 - bsps/sh/gensh2/include/sh/sci_termios.h | 84 - bsps/sh/gensh2/include/sh/sh7_pfc.h | 202 --- bsps/sh/gensh2/include/sh/sh7_sci.h | 88 - bsps/sh/gensh2/include/tm27.h | 1 - bsps/sh/gensh2/start/cpu_asm.c | 170 -- bsps/sh/gensh2/start/hw_init.c | 112 -- bsps/sh/gensh2/start/ispsh7045.c | 310 ---- bsps/sh/gensh2/start/linkcmds | 252 --- bsps/sh/gensh2/start/linkcmds.ram | 251 --- bsps/sh/gensh2/start/linkcmds.rom | 256 --- bsps/sh/gensh2/start/start.S | 184 -- bsps/sh/gensh2/start/start.ram | 188 -- bsps/sh/gensh2/start/start.rom | 83 - bsps/sh/gensh4/README.md | 100 - bsps/sh/gensh4/btimer/btimer.c | 269 --- bsps/sh/gensh4/clock/ckinit.c | 235 --- bsps/sh/gensh4/config/gensh4.cfg | 28 - bsps/sh/gensh4/console/console.c | 469 ----- bsps/sh/gensh4/console/sh4uart.c | 910 ---------- bsps/sh/gensh4/include/bsp.h | 105 -- bsps/sh/gensh4/include/bsp/irq.h | 1 - bsps/sh/gensh4/include/rtems/score/iosh7750.h | 47 - bsps/sh/gensh4/include/rtems/score/ipl.h | 73 - .../sh/gensh4/include/rtems/score/ispsh7750.h | 60 - bsps/sh/gensh4/include/rtems/score/sh4_regs.h | 51 - .../gensh4/include/rtems/score/sh7750_regs.h | 1613 ----------------- bsps/sh/gensh4/include/sdram.h | 40 - bsps/sh/gensh4/include/sh/sh4uart.h | 174 -- bsps/sh/gensh4/include/tm27.h | 61 - bsps/sh/gensh4/start/cpu_asm.c | 94 - bsps/sh/gensh4/start/hw_init.c | 283 --- bsps/sh/gensh4/start/ispsh7750.c | 316 ---- bsps/sh/gensh4/start/linkcmds | 195 -- bsps/sh/gensh4/start/linkcmds.rom | 235 --- bsps/sh/gensh4/start/linkcmds.rom2ram | 239 --- bsps/sh/gensh4/start/start.S | 270 --- bsps/sh/shared/console/console.c | 123 -- bsps/sh/shared/doxygen.h | 15 - bsps/sh/shared/start/bsphwinit.c | 37 - bsps/sh/shared/start/bspstart.c | 55 - bsps/sh/shared/start/setvec.c | 55 - bsps/sh/shsim/README.md | 46 - bsps/sh/shsim/config/simsh1-testsuite.tcfg | 16 - bsps/sh/shsim/config/simsh1.cfg | 18 - bsps/sh/shsim/config/simsh2-testsuite.tcfg | 16 - bsps/sh/shsim/config/simsh2.cfg | 18 - bsps/sh/shsim/config/simsh2e-testsuite.tcfg | 15 - bsps/sh/shsim/config/simsh2e.cfg | 17 - bsps/sh/shsim/config/simsh4-testsuite.tcfg | 15 - bsps/sh/shsim/config/simsh4.cfg | 17 - bsps/sh/shsim/console/console-debugio.c | 52 - bsps/sh/shsim/console/console-io.c | 76 - bsps/sh/shsim/console/console-support.S | 18 - bsps/sh/shsim/include/bsp.h | 80 - bsps/sh/shsim/include/bsp/irq.h | 1 - bsps/sh/shsim/include/bsp/syscall.h | 32 - bsps/sh/shsim/include/tm27.h | 1 - bsps/sh/shsim/start/cpu_asm.c | 93 - bsps/sh/shsim/start/ispshgdb.c | 146 -- bsps/sh/shsim/start/linkcmds | 253 --- bsps/sh/shsim/start/start.S | 84 - bsps/sh/shsim/start/sysexit.c | 41 - cpukit/score/cpu/sh/context.c | 233 --- cpukit/score/cpu/sh/cpu.c | 177 -- cpukit/score/cpu/sh/include/rtems/asm.h | 147 -- cpukit/score/cpu/sh/include/rtems/score/cpu.h | 590 ------ .../cpu/sh/include/rtems/score/cpuimpl.h | 87 - cpukit/score/cpu/sh/include/rtems/score/sh.h | 277 --- .../score/cpu/sh/include/rtems/score/sh_io.h | 51 - .../score/cpu/sh/sh-exception-frame-print.c | 18 - spec/build/bsps/sh/gensh1/abi.yml | 18 - spec/build/bsps/sh/gensh1/bspgensh1.yml | 69 - spec/build/bsps/sh/gensh1/optcpuclk.yml | 17 - spec/build/bsps/sh/gensh1/optlowinit.yml | 16 - spec/build/bsps/sh/gensh1/start.yml | 14 - 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--git a/bsps/sh/gensh1/README.md b/bsps/sh/gensh1/README.md deleted file mode 100644 index baf1490b83..0000000000 --- a/bsps/sh/gensh1/README.md +++ /dev/null @@ -1,59 +0,0 @@ -gensh1 -====== -Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) - -``` -BSP NAME: generic SH1 (gensh1) -BOARD: n/a -BUS: n/a -CPU FAMILY: Hitachi SH -CPU: SH 7032 -COPROCESSORS: none -MODE: n/a - -DEBUG MONITOR: gdb -``` - -PERIPHERALS ------------ -``` -TIMERS: on-chip - RESOLUTION: cf. Hitachi SH 703X Hardware Manual (Phi/4) -SERIAL PORTS: on-chip (with 2 ports) -REAL-TIME CLOCK: none -DMA: not used -VIDEO: none -SCSI: none -NETWORKING: none -``` - -DRIVER INFORMATION ------------------- -``` -CLOCK DRIVER: on-chip timer -IOSUPP DRIVER: default -SHMSUPP: default -TIMER DRIVER: on-chip timer -TTY DRIVER: /dev/null (stub) -``` - -STDIO ------ -``` -PORT: /dev/null (stub) -ELECTRICAL: n/a -BAUD: n/a -BITS PER CHARACTER: n/a -PARITY: n/a -STOP BITS: n/a -``` - -NOTES ------ -(1) The stub console driver (null) is enabled by default. - -(2) The driver for the on-chip serial devices (sci) is still in its infancy - and not fully tested. It may even be non-functional and therefore is - disabled by default. Please let us know any problems you encounter with - it. - To activate it edit libbsp/sh/gensh1/include/bsp.h diff --git a/bsps/sh/gensh1/btimer/btimer.c b/bsps/sh/gensh1/btimer/btimer.c deleted file mode 100644 index 94a834cb1e..0000000000 --- a/bsps/sh/gensh1/btimer/btimer.c +++ /dev/null @@ -1,195 +0,0 @@ -/** - * @file - * @brief Timer for the Hitachi SH 703X - */ - -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include -#include - -#include -#include -#include - -extern uint32_t bsp_clicks_per_second; - -#define I_CLK_PHI_1 0 -#define I_CLK_PHI_2 1 -#define I_CLK_PHI_4 2 -#define I_CLK_PHI_8 3 - -/* - * Set I_CLK_PHI to one of the I_CLK_PHI_X values from above to choose - * a PHI/X clock rate. - */ - -#define I_CLK_PHI I_CLK_PHI_4 -#define CLOCK_SCALE (1< - -#include - -#include -#include -#include -#include -#include - -extern uint32_t bsp_clicks_per_second; - -#ifndef CLOCKPRIO -#define CLOCKPRIO 10 -#endif - -#define I_CLK_PHI_1 0 -#define I_CLK_PHI_2 1 -#define I_CLK_PHI_4 2 -#define I_CLK_PHI_8 3 - -/* - * Set I_CLK_PHI to one of the I_CLK_PHI_X values from above to choose - * a PHI/X clock rate. - */ - -#define I_CLK_PHI I_CLK_PHI_4 -#define CLOCK_SCALE (1< 0 ) - { - c /= 10 ; - d *= 10 ; - a = ( ( b / c ) * usec_per_tick ) / d ; - clicks_per_tick += a ; - } - return clicks_per_tick ; -#else - double fclicks_per_tick = - ((double) clicks_per_sec * (double) usec_per_tick) / 1000000.0 ; - return (uint32_t) fclicks_per_tick ; -#endif -} - -/* - * The interrupt vector number associated with the clock tick device - * driver. - */ - -#define CLOCK_VECTOR IMIA0_ISP_V - -/* - * Clock_driver_ticks is a monotonically increasing counter of the - * number of clock ticks since the driver was initialized. - */ - -volatile uint32_t Clock_driver_ticks; - -static void Clock_exit( void ); -static rtems_isr Clock_isr( rtems_vector_number vector ); - -/* - * Clock_isrs is the number of clock ISRs until the next invocation of - * the RTEMS clock tick routine. The clock tick device driver - * gets an interrupt once a millisecond and counts down until the - * length of time between the user configured microseconds per tick - * has passed. - */ - -uint32_t Clock_isrs; /* ISRs until next tick */ -static uint32_t Clock_isrs_const; /* only calculated once */ - -/* - * The previous ISR on this clock tick interrupt vector. - */ -rtems_isr_entry Old_ticker; - -/* - * Isr Handler - */ -static rtems_isr Clock_isr( - rtems_vector_number vector -) -{ - /* - * bump the number of clock driver ticks since initialization - * - * determine if it is time to announce the passing of tick as configured - * to RTEMS through the rtems_clock_tick directive - * - * perform any timer dependent tasks - */ - uint8_t temp; - - /* reset the flags of the status register */ - temp = read8( ITU_TSR0) & ITU_STAT_MASK; - write8( temp, ITU_TSR0); - - Clock_driver_ticks++ ; - - if( Clock_isrs == 1) - { - rtems_clock_tick(); - Clock_isrs = Clock_isrs_const; - } - else - { - Clock_isrs-- ; - } -} - -/* - * Install_clock - * - * Install a clock tick handler and reprograms the chip. This - * is used to initially establish the clock tick. - */ -static void Install_clock( - rtems_isr_entry clock_isr -) -{ - uint8_t temp8 = 0; - uint32_t microseconds_per_tick; - uint32_t cclicks_per_tick; - uint16_t Clock_limit; - - /* - * Initialize the clock tick device driver variables - */ - - Clock_driver_ticks = 0; - - if ( rtems_configuration_get_microseconds_per_tick() != 0 ) - microseconds_per_tick = rtems_configuration_get_microseconds_per_tick() ; - else - microseconds_per_tick = 10000 ; /* 10000 us */ - - /* clock clicks per tick */ - cclicks_per_tick = sh_clicks_per_tick( - bsp_clicks_per_second / CLOCK_SCALE, microseconds_per_tick ); - - Clock_isrs_const = cclicks_per_tick >> 16 ; - if ( ( cclicks_per_tick | 0xffff ) > 0 ) - Clock_isrs_const++ ; - Clock_limit = cclicks_per_tick / Clock_isrs_const ; - Clock_isrs = Clock_isrs_const; - - rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker ); - /* - * Hardware specific initialize goes here - */ - - /* stop Timer 0 */ - temp8 = read8( ITU_TSTR) & ITU0_STARTMASK; - write8( temp8, ITU_TSTR); - - /* set initial counter value to 0 */ - write16( 0, ITU_TCNT0); - - /* Timer 0 runs independent */ - temp8 = read8( ITU_TSNC) & ITU0_SYNCMASK; - write8( temp8, ITU_TSNC); - - /* Timer 0 normal mode */ - temp8 = read8( ITU_TMDR) & ITU0_MODEMASK; - write8( temp8, ITU_TMDR); - - /* TCNT is cleared by GRA ; internal clock /4 */ - write8( ITU0_TCRMASK , ITU_TCR0); - - /* use GRA without I/O - pins */ - write8( ITU0_TIORVAL, ITU_TIOR0); - - /* reset flags of the status register */ - temp8 = read8( ITU_TSR0) & ITU_STAT_MASK; - write8( temp8, ITU_TSR0); - - /* Irq if is equal GRA */ - temp8 = read8( ITU_TIER0) | ITU0_TIERMASK; - write8( temp8, ITU_TIER0); - - /* set interrupt priority */ - if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); - - /* set counter limits */ - write16( Clock_limit, ITU_GRA0); - - /* start counter */ - temp8 = read8( ITU_TSTR) |~ITU0_STARTMASK; - write8( temp8, ITU_TSTR); - - /* - * Schedule the clock cleanup routine to execute if the application exits. - */ - - atexit( Clock_exit ); -} - -/* - * Clean up before the application exits - */ -void Clock_exit( void ) -{ - uint8_t temp8 = 0; - - /* turn off the timer interrupts */ - /* set interrupt priority to 0 */ - if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred( RTEMS_UNSATISFIED); - -/* - * temp16 = read16( ITU_TIER0) & IPRC_ITU0_IRQMASK; - * write16( temp16, ITU_TIER0); - */ - - /* stop counter */ - temp8 = read8( ITU_TSTR) & ITU0_STARTMASK; - write8( temp8, ITU_TSTR); - - /* old vector shall not be installed */ -} - -void _Clock_Initialize( void ) -{ - Install_clock( Clock_isr ); -} diff --git a/bsps/sh/gensh1/clock/delay.c b/bsps/sh/gensh1/clock/delay.c deleted file mode 100644 index 085771f777..0000000000 --- a/bsps/sh/gensh1/clock/delay.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This routine is a simple spin delay - * - * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1999, Ralf Corsepius, Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -#include - -extern uint32_t bsp_clicks_per_second; - -/* - * Simple spin delay in microsecond units for device drivers. - * This is very dependent on the clock speed of the target. - * - * Since we don't have a real time clock, this is a very rough - * approximation, assuming that each cycle of the delay loop takes - * approx. 4 machine cycles. - * - * e.g.: clicks_per_second = 20MHz - * => 5e-8 secs per instruction - * => 4 * 5e-8 secs per delay loop - */ - -void CPU_delay( uint32_t microseconds ) -{ - register uint32_t clicks_per_usec = bsp_clicks_per_second / 1000000; - register uint32_t _delay = (microseconds) * (clicks_per_usec); - - __asm__ volatile ( -"0: add #-4,%0\n\ - nop\n\ - cmp/pl %0\n\ - bt 0b\n\ - nop" - :: "r" (_delay) ); -} diff --git a/bsps/sh/gensh1/config/gensh1-testsuite.tcfg b/bsps/sh/gensh1/config/gensh1-testsuite.tcfg deleted file mode 100644 index 9fa3c1aa6a..0000000000 --- a/bsps/sh/gensh1/config/gensh1-testsuite.tcfg +++ /dev/null @@ -1,13 +0,0 @@ -# -# gensh1 RTEMS Test Database. -# -# Format is one line per test that is _NOT_ built. -# - -include: testdata/disable-iconv-tests.tcfg -exclude: fileio -exclude: fsdosfsname01 -exclude: iostream -exclude: linpack -exclude: record02 -exclude: utf8proc01 diff --git a/bsps/sh/gensh1/config/gensh1.cfg b/bsps/sh/gensh1/config/gensh1.cfg deleted file mode 100644 index 16b61d222b..0000000000 --- a/bsps/sh/gensh1/config/gensh1.cfg +++ /dev/null @@ -1,22 +0,0 @@ -# -# gensh1.cfg -# -# default configuration for Hitachi sh1 processors -# -# Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) -# - -include $(RTEMS_ROOT)/make/custom/default.cfg - -RTEMS_CPU=sh - -# This contains the compiler options necessary to select the CPU model -# and (hopefully) optimize for it. -# -CPU_CFLAGS = -m1 - -# optimize flag: typically -O2 -CFLAGS_OPTIMIZE_V = -O2 -g -CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections - -LDFLAGS = -Wl,--gc-sections diff --git a/bsps/sh/gensh1/console/sci.c b/bsps/sh/gensh1/console/sci.c deleted file mode 100644 index fedfa30b51..0000000000 --- a/bsps/sh/gensh1/console/sci.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - * /dev/sci[0|1] for Hitachi SH 703X - * - * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1999, Ralf Corsepius, Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * NOTE: Some SH variants have 3 sci devices - */ - -#define SCI_MINOR_DEVICES 2 - -#define SH_SCI_BASE_0 SCI0_SMR -#define SH_SCI_BASE_1 SCI1_SMR - -struct scidev_t { - char * name ; - uint32_t addr ; - rtems_device_minor_number minor ; - unsigned short opened ; - tcflag_t cflags ; - speed_t spd ; -} sci_device[SCI_MINOR_DEVICES] = -{ - { "/dev/sci0", SH_SCI_BASE_0, 0, 0, CS8, B9600 }, - { "/dev/sci1", SH_SCI_BASE_1, 1, 0, CS8, B9600 } -} ; - -/* Translate termios' tcflag_t into sci settings */ -static int _sci_set_cflags( - struct scidev_t *sci_dev, - tcflag_t c_cflag, - speed_t spd ) -{ - uint8_t smr ; - uint8_t brr ; - - if ( spd ) - { - if ( _sci_get_brparms( spd, &smr, &brr ) != 0 ) - return -1 ; - } - - if ( c_cflag & CSIZE ) - { - if ( c_cflag & CS8 ) - smr &= ~SCI_SEVEN_BIT_DATA; - else if ( c_cflag & CS7 ) - smr |= SCI_SEVEN_BIT_DATA; - else - return -1 ; - } - - if ( c_cflag & CSTOPB ) - smr |= SCI_STOP_BITS_2; - else - smr &= ~SCI_STOP_BITS_2; - - if ( c_cflag & PARENB ) - smr |= SCI_PARITY_ON ; - else - smr &= ~SCI_PARITY_ON ; - - if ( c_cflag & PARODD ) - smr |= SCI_ODD_PARITY ; - else - smr &= ~SCI_ODD_PARITY; - - write8( smr, sci_dev->addr + SCI_SMR ); - write8( brr, sci_dev->addr + SCI_BRR ); - - return 0 ; -} - -static void _sci_init( - rtems_device_minor_number minor ) -{ - uint16_t temp16 ; - - /* Pin function controller initialisation for asynchronous mode */ - if( minor == 0) - { - temp16 = read16( PFC_PBCR1); - temp16 &= ~( PB8MD | PB9MD ); - temp16 |= (PB_TXD0 | PB_RXD0); - write16( temp16, PFC_PBCR1); - } - else - { - temp16 = read16( PFC_PBCR1); - temp16 &= ~( PB10MD | PB11MD); - temp16 |= (PB_TXD1 | PB_RXD1); - write16( temp16, PFC_PBCR1); - } - - /* disable sck-pin */ - if( minor == 0) - { - temp16 = read16( PFC_PBCR1); - temp16 &= ~(PB12MD); - write16( temp16, PFC_PBCR1); - } - else - { - temp16 = read16( PFC_PBCR1); - temp16 &= ~(PB13MD); - write16( temp16, PFC_PBCR1); - } -} - -static void _sci_tx_polled( - int minor, - const char buf ) -{ - struct scidev_t *scidev = &sci_device[minor] ; - int8_t ssr ; - - while ( !inb((scidev->addr + SCI_SSR) & SCI_TDRE )) - ; - write8(buf,scidev->addr+SCI_TDR); - - ssr = inb(scidev->addr+SCI_SSR); - ssr &= ~SCI_TDRE ; - write8(ssr,scidev->addr+SCI_SSR); -} - -static int _sci_rx_polled ( - int minor) -{ - struct scidev_t *scidev = &sci_device[minor] ; - - unsigned char c; - char ssr ; - ssr = read8(scidev->addr + SCI_SSR) ; - - if (ssr & (SCI_PER | SCI_FER | SCI_ORER)) - write8(ssr & ~(SCI_PER | SCI_FER | SCI_ORER), scidev->addr+SCI_SSR); - - if ( !(ssr & SCI_RDRF) ) - return -1; - - c = read8(scidev->addr + SCI_RDR) ; - - write8(ssr & ~SCI_RDRF,scidev->addr + SCI_SSR); - return c; -} - -/* - * sci_initialize - */ - -rtems_device_driver sh_sci_initialize( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg ) -{ - rtems_device_driver status ; - rtems_device_minor_number i; - - /* - * register all possible devices. - * the initialization of the hardware is done by sci_open - */ - - for ( i = 0 ; i < SCI_MINOR_DEVICES ; i++ ) - { - status = rtems_io_register_name( - sci_device[i].name, - major, - sci_device[i].minor ); - if (status != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred(status); - } - - /* default hardware setup */ - - return RTEMS_SUCCESSFUL; -} - - -/* - * Open entry point - */ - -rtems_device_driver sh_sci_open( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg ) -{ - uint8_t temp8; - - /* check for valid minor number */ - if(( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 )) - { - return RTEMS_INVALID_NUMBER; - } - - /* device already opened */ - if ( sci_device[minor].opened > 0 ) - { - sci_device[minor].opened++ ; - return RTEMS_SUCCESSFUL ; - } - - _sci_init( minor ); - - if (minor == 0) { - temp8 = read8(sci_device[minor].addr + SCI_SCR); - temp8 &= ~(SCI_TE | SCI_RE) ; - write8(temp8, sci_device[minor].addr + SCI_SCR); /* Clear SCR */ - _sci_set_cflags( &sci_device[minor], sci_device[minor].cflags, sci_device[minor].spd ); - -/* FIXME: Should be one bit delay */ - CPU_delay(50000); /* microseconds */ - - temp8 |= SCI_RE | SCI_TE; - write8(temp8, sci_device[minor].addr + SCI_SCR); /* Enable clock output */ - } else { - temp8 = read8(sci_device[minor].addr + SCI_SCR); - temp8 &= ~(SCI_TE | SCI_RE) ; - write8(temp8, sci_device[minor].addr + SCI_SCR); /* Clear SCR */ - _sci_set_cflags( &sci_device[minor], sci_device[minor].cflags, sci_device[minor].spd ); - -/* FIXME: Should be one bit delay */ - CPU_delay(50000); /* microseconds */ - - temp8 |= SCI_RE | SCI_TE; - write8(temp8, sci_device[minor].addr + SCI_SCR); /* Enable clock output */ - } - - sci_device[minor].opened++ ; - - return RTEMS_SUCCESSFUL ; -} - -/* - * Close entry point - */ - -rtems_device_driver sh_sci_close( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - if( sci_device[minor].opened == 0 ) - { - return RTEMS_INVALID_NUMBER; - } - - sci_device[minor].opened-- ; - - return RTEMS_SUCCESSFUL ; -} - -/* - * read bytes from the serial port. - */ - -rtems_device_driver sh_sci_read( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - int count = 0; - - rtems_libio_rw_args_t *rw_args = (rtems_libio_rw_args_t *) arg; - char * buffer = rw_args->buffer; - int maximum = rw_args->count; - - for (count = 0; count < maximum; count++) { - buffer[ count ] = _sci_rx_polled(minor); - if (buffer[ count ] == '\n' || buffer[ count ] == '\r') { - buffer[ count++ ] = '\n'; - break; - } - } - - rw_args->bytes_moved = count; - return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED; -} - -/* - * write bytes to the serial port. - */ - -rtems_device_driver sh_sci_write( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - int count; - - rtems_libio_rw_args_t *rw_args = (rtems_libio_rw_args_t *) arg; - char *buffer = rw_args->buffer; - int maximum = rw_args->count; - - for (count = 0; count < maximum; count++) { -#if 0 - if ( buffer[ count ] == '\n') { - outbyte(minor, '\r'); - } -#endif - _sci_tx_polled( minor, buffer[ count ] ); - } - - rw_args->bytes_moved = maximum; - return 0; -} - -/* - * IO Control entry point - */ - -rtems_device_driver sh_sci_control( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - /* Not yet supported */ - return RTEMS_SUCCESSFUL ; -} diff --git a/bsps/sh/gensh1/console/scitab.c b/bsps/sh/gensh1/console/scitab.c deleted file mode 100644 index 2dd36d55da..0000000000 --- a/bsps/sh/gensh1/console/scitab.c +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * Copyright (c) 2018 embedded brains GmbH & Co. KG - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * The content of this file was previously generated by the GPL licensed shgen - * tool during the BSP build for a configured clock frequency - * (CPU_CLOCK_RATE_HZ). All tools were removed from the RTEMS source repository - * at some point in time. Tools with a BSD-style license were moved to the - * RTEMS tools repository. - */ - -#include - -int _sci_get_brparms( - unsigned int spd, - unsigned char *smr, - unsigned char *brr -) -{ - if (spd != 9600) { - return -1; - } - - *smr = 0x00; - *brr = 0x40; - return 0; -} diff --git a/bsps/sh/gensh1/include/bsp.h b/bsps/sh/gensh1/include/bsp.h deleted file mode 100644 index 7fe7c3c0c5..0000000000 --- a/bsps/sh/gensh1/include/bsp.h +++ /dev/null @@ -1,86 +0,0 @@ -/** - * @file - * - * @ingroup RTEMSBSPsSH1 - * - * @brief Global BSP definitions. - */ - -/* - * generic sh1 - * - * This include file contains all board IO definitions. - */ - -/* - * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_SH_GENSH1_BSP_H -#define LIBBSP_SH_GENSH1_BSP_H - -/** - * @defgroup RTEMSBSPsSH1 SH-1 - * - * @ingroup RTEMSBSPsSH - * - * @brief SH-1 Board Support Package. - * - * @{ - */ - -#include -#include /* for tcflag_t */ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* EDIT: To activate the sci driver, change the define below */ -#if 1 -#include -#define BSP_CONSOLE_DEVNAME "/dev/null" -#define BSP_CONSOLE_DRIVER_TABLE_ENTRY DEVNULL_DRIVER_TABLE_ENTRY -#else -#include -#define BSP_CONSOLE_DEVNAME "/dev/sci0" -#define BSP_CONSOLE_DRIVER_TABLE_ENTRY DEVSCI_DRIVER_TABLE_ENTRY -#endif - -/* Constants */ - -/* - * BSP methods that cross file boundaries. - */ -void bsp_hw_init(void); - -int _sci_get_brparms( - unsigned int spd, - unsigned char *smr, - unsigned char *brr -); - -#ifdef __cplusplus -} -#endif - -/** @} */ - -#endif diff --git a/bsps/sh/gensh1/include/bsp/irq.h b/bsps/sh/gensh1/include/bsp/irq.h deleted file mode 100644 index 8a97d7a1b0..0000000000 --- a/bsps/sh/gensh1/include/bsp/irq.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/bsps/sh/gensh1/include/rtems/score/iosh7032.h b/bsps/sh/gensh1/include/rtems/score/iosh7032.h deleted file mode 100644 index 3750024a64..0000000000 --- a/bsps/sh/gensh1/include/rtems/score/iosh7032.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * This include file contains information pertaining to the Hitachi SH - * processor. - * - * NOTE: NOT ALL VALUES HAVE BEEN CHECKED !! - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which - * contained no copyright notice. - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __IOSH7030_H -#define __IOSH7030_H - -/* - * After each line is explained whether the access is char short or long. - * The functions read/writeb, w, l, 8, 16, 32 can be found - * in exec/score/cpu/sh/sh_io.h - * - * 8 bit == char ( readb, writeb, read8, write8) - * 16 bit == short ( readw, writew, read16, write16 ) - * 32 bit == long ( readl, writel, read32, write32 ) - */ - -#define SCI0_SMR 0x05fffec0 /* char */ -#define SCI0_BRR 0x05fffec1 /* char */ -#define SCI0_SCR 0x05fffec2 /* char */ -#define SCI0_TDR 0x05fffec3 /* char */ -#define SCI0_SSR 0x05fffec4 /* char */ -#define SCI0_RDR 0x05fffec5 /* char */ - -#define SCI1_SMR 0x05fffec8 /* char */ -#define SCI1_BRR 0x05fffec9 /* char */ -#define SCI1_SCR 0x05fffeca /* char */ -#define SCI1_TDR 0x05fffecb /* char */ -#define SCI1_SSR 0x05fffecc /* char */ -#define SCI1_RDR 0x05fffecd /* char */ - - -#define ADDRAH 0x05fffee0 /* char */ -#define ADDRAL 0x05fffee1 /* char */ -#define ADDRBH 0x05fffee2 /* char */ -#define ADDRBL 0x05fffee3 /* char */ -#define ADDRCH 0x05fffee4 /* char */ -#define ADDRCL 0x05fffee5 /* char */ -#define ADDRDH 0x05fffee6 /* char */ -#define ADDRDL 0x05fffee7 /* char */ -#define AD_DRA 0x05fffee0 /* short */ -#define AD_DRB 0x05fffee2 /* short */ -#define AD_DRC 0x05fffee4 /* short */ -#define AD_DRD 0x05fffee6 /* short */ -#define ADCSR 0x05fffee8 /* char */ -#define ADCR 0x05fffee9 /* char */ - -/*ITU SHARED*/ -#define ITU_TSTR 0x05ffff00 /* char */ -#define ITU_TSNC 0x05ffff01 /* char */ -#define ITU_TMDR 0x05ffff02 /* char */ -#define ITU_TFCR 0x05ffff03 /* char */ - -/*ITU CHANNEL 0*/ -#define ITU_TCR0 0x05ffff04 /* char */ -#define ITU_TIOR0 0x05ffff05 /* char */ -#define ITU_TIER0 0x05ffff06 /* char */ -#define ITU_TSR0 0x05ffff07 /* char */ -#define ITU_TCNT0 0x05ffff08 /* short */ -#define ITU_GRA0 0x05ffff0a /* short */ -#define ITU_GRB0 0x05ffff0c /* short */ - - /*ITU CHANNEL 1*/ -#define ITU_TCR1 0x05ffff0E /* char */ -#define ITU_TIOR1 0x05ffff0F /* char */ -#define ITU_TIER1 0x05ffff10 /* char */ -#define ITU_TSR1 0x05ffff11 /* char */ -#define ITU_TCNT1 0x05ffff12 /* short */ -#define ITU_GRA1 0x05ffff14 /* short */ -#define ITU_GRB1 0x05ffff16 /* short */ - - - /*ITU CHANNEL 2*/ -#define ITU_TCR2 0x05ffff18 /* char */ -#define ITU_TIOR2 0x05ffff19 /* char */ -#define ITU_TIER2 0x05ffff1A /* char */ -#define ITU_TSR2 0x05ffff1B /* char */ -#define ITU_TCNT2 0x05ffff1C /* short */ -#define ITU_GRA2 0x05ffff1E /* short */ -#define ITU_GRB2 0x05ffff20 /* short */ - - /*ITU CHANNEL 3*/ -#define ITU_TCR3 0x05ffff22 /* char */ -#define ITU_TIOR3 0x05ffff23 /* char */ -#define ITU_TIER3 0x05ffff24 /* char */ -#define ITU_TSR3 0x05ffff25 /* char */ -#define ITU_TCNT3 0x05ffff26 /* short */ -#define ITU_GRA3 0x05ffff28 /* short */ -#define ITU_GRB3 0x05ffff2A /* short */ -#define ITU_BRA3 0x05ffff2C /* short */ -#define ITU_BRB3 0x05ffff2E /* short */ - - /*ITU CHANNELS 0-4 SHARED*/ -#define ITU_TOCR 0x05ffff31 /* char */ - - /*ITU CHANNEL 4*/ -#define ITU_TCR4 0x05ffff32 /* char */ -#define ITU_TIOR4 0x05ffff33 /* char */ -#define ITU_TIER4 0x05ffff34 /* char */ -#define ITU_TSR4 0x05ffff35 /* char */ -#define ITU_TCNT4 0x05ffff36 /* short */ -#define ITU_GRA4 0x05ffff38 /* short */ -#define ITU_GRB4 0x05ffff3A /* short */ -#define ITU_BRA4 0x05ffff3C /* short */ -#define ITU_BRB4 0x05ffff3E /* short */ - - /*DMAC CHANNELS 0-3 SHARED*/ -#define DMAOR 0x05ffff48 /* short */ - - /*DMAC CHANNEL 0*/ -#define DMA_SAR0 0x05ffff40 /* long */ -#define DMA_DAR0 0x05ffff44 /* long */ -#define DMA_TCR0 0x05ffff4a /* short */ -#define DMA_CHCR0 0x05ffff4e /* short */ - - /*DMAC CHANNEL 1*/ -#define DMA_SAR1 0x05ffff50 /* long */ -#define DMA_DAR1 0x05ffff54 /* long */ -#define DMA_TCR1 0x05fffF5a /* short */ -#define DMA_CHCR1 0x05ffff5e /* short */ - - /*DMAC CHANNEL 3*/ -#define DMA_SAR3 0x05ffff60 /* long */ -#define DMA_DAR3 0x05ffff64 /* long */ -#define DMA_TCR3 0x05fffF6a /* short */ -#define DMA_CHCR3 0x05ffff6e /* short */ - -/*DMAC CHANNEL 4*/ -#define DMA_SAR4 0x05ffff70 /* long */ -#define DMA_DAR4 0x05ffff74 /* long */ -#define DMA_TCR4 0x05fffF7a /* short */ -#define DMA_CHCR4 0x05ffff7e /* short */ - -/*INTC*/ -#define INTC_IPRA 0x05ffff84 /* short */ -#define INTC_IPRB 0x05ffff86 /* short */ -#define INTC_IPRC 0x05ffff88 /* short */ -#define INTC_IPRD 0x05ffff8A /* short */ -#define INTC_IPRE 0x05ffff8C /* short */ -#define INTC_ICR 0x05ffff8E /* short */ - -/*UBC*/ -#define UBC_BARH 0x05ffff90 /* short */ -#define UBC_BARL 0x05ffff92 /* short */ -#define UBC_BAMRH 0x05ffff94 /* short */ -#define UBC_BAMRL 0x05ffff96 /* short */ -#define UBC_BBR 0x05ffff98 /* short */ - -/*BSC*/ -#define BSC_BCR 0x05ffffA0 /* short */ -#define BSC_WCR1 0x05ffffA2 /* short */ -#define BSC_WCR2 0x05ffffA4 /* short */ -#define BSC_WCR3 0x05ffffA6 /* short */ -#define BSC_DCR 0x05ffffA8 /* short */ -#define BSC_PCR 0x05ffffAA /* short */ -#define BSC_RCR 0x05ffffAC /* short */ -#define BSC_RTCSR 0x05ffffAE /* short */ -#define BSC_RTCNT 0x05ffffB0 /* short */ -#define BSC_RTCOR 0x05ffffB2 /* short */ - -/*WDT*/ -#define WDT_TCSR 0x05ffffB8 /* char */ -#define WDT_TCNT 0x05ffffB9 /* char */ -#define WDT_RSTCSR 0x05ffffBB /* char */ - -/*POWER DOWN STATE*/ -#define PDT_SBYCR 0x05ffffBC /* char */ - -/*PORT A*/ -#define PADR 0x05ffffC0 /* short */ - -/*PORT B*/ -#define PBDR 0x05ffffC2 /* short */ - - /*PORT C*/ -#define PCDR 0x05ffffD0 /* short */ - -/*PFC*/ -#define PFC_PAIOR 0x05ffffC4 /* short */ -#define PFC_PBIOR 0x05ffffC6 /* short */ -#define PFC_PACR1 0x05ffffC8 /* short */ -#define PFC_PACR2 0x05ffffCA /* short */ -#define PFC_PBCR1 0x05ffffCC /* short */ -#define PFC_PBCR2 0x05ffffCE /* short */ -#define PFC_CASCR 0x05ffffEE /* short */ - -/*TPC*/ -#define TPC_TPMR 0x05ffffF0 /* short */ -#define TPC_TPCR 0x05ffffF1 /* short */ -#define TPC_NDERH 0x05ffffF2 /* short */ -#define TPC_NDERL 0x05ffffF3 /* short */ -#define TPC_NDRB 0x05ffffF4 /* char */ -#define TPC_NDRA 0x05ffffF5 /* char */ -#define TPC_NDRB1 0x05ffffF6 /* char */ -#define TPC_NDRA1 0x05ffffF7 /* char */ - -#endif diff --git a/bsps/sh/gensh1/include/rtems/score/ispsh7032.h b/bsps/sh/gensh1/include/rtems/score/ispsh7032.h deleted file mode 100644 index 469a9deed6..0000000000 --- a/bsps/sh/gensh1/include/rtems/score/ispsh7032.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * This include file contains information pertaining to the Hitachi SH - * processor. - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __CPU_ISPS_H -#define __CPU_ISPS_H - -#ifdef __cplusplus -extern "C" { -#endif - -extern void __ISR_Handler( uint32_t vector ); - - -/* - * interrupt vector table offsets - */ -#define NMI_ISP_V 11 -#define USB_ISP_V 12 -#define IRQ0_ISP_V 64 -#define IRQ1_ISP_V 65 -#define IRQ2_ISP_V 66 -#define IRQ3_ISP_V 67 -#define IRQ4_ISP_V 68 -#define IRQ5_ISP_V 69 -#define IRQ6_ISP_V 70 -#define IRQ7_ISP_V 71 -#define DMA0_ISP_V 72 -#define DMA1_ISP_V 74 -#define DMA2_ISP_V 76 -#define DMA3_ISP_V 78 - -#define IMIA0_ISP_V 80 -#define IMIB0_ISP_V 81 -#define OVI0_ISP_V 82 - -#define IMIA1_ISP_V 84 -#define IMIB1_ISP_V 85 -#define OVI1_ISP_V 86 - -#define IMIA2_ISP_V 88 -#define IMIB2_ISP_V 89 -#define OVI2_ISP_V 90 - -#define IMIA3_ISP_V 92 -#define IMIB3_ISP_V 93 -#define OVI3_ISP_V 94 - -#define IMIA4_ISP_V 96 -#define IMIB4_ISP_V 97 -#define OVI4_ISP_V 98 - -#define ERI0_ISP_V 100 -#define RXI0_ISP_V 101 -#define TXI0_ISP_V 102 -#define TEI0_ISP_V 103 - -#define ERI1_ISP_V 104 -#define RXI1_ISP_V 105 -#define TXI1_ISP_V 106 -#define TEI1_ISP_V 107 - -#define PRT_ISP_V 108 -#define ADU_ISP_V 109 -#define WDT_ISP_V 112 -#define DREF_ISP_V 113 - - -/* dummy ISP */ -extern void _dummy_isp( void ); - -/* Non Maskable Interrupt */ -extern void _nmi_isp( void ); - -/* User Break Controller */ -extern void _usb_isp( void ); - -/* External interrupts 0-7 */ -extern void _irq0_isp( void ); -extern void _irq1_isp( void ); -extern void _irq2_isp( void ); -extern void _irq3_isp( void ); -extern void _irq4_isp( void ); -extern void _irq5_isp( void ); -extern void _irq6_isp( void ); -extern void _irq7_isp( void ); - -/* DMA - Controller */ -extern void _dma0_isp( void ); -extern void _dma1_isp( void ); -extern void _dma2_isp( void ); -extern void _dma3_isp( void ); - -/* Interrupt Timer Unit */ -/* Timer 0 */ -extern void _imia0_isp( void ); -extern void _imib0_isp( void ); -extern void _ovi0_isp( void ); -/* Timer 1 */ -extern void _imia1_isp( void ); -extern void _imib1_isp( void ); -extern void _ovi1_isp( void ); -/* Timer 2 */ -extern void _imia2_isp( void ); -extern void _imib2_isp( void ); -extern void _ovi2_isp( void ); -/* Timer 3 */ -extern void _imia3_isp( void ); -extern void _imib3_isp( void ); -extern void _ovi3_isp( void ); -/* Timer 4 */ -extern void _imia4_isp( void ); -extern void _imib4_isp( void ); -extern void _ovi4_isp( void ); - -/* seriell interfaces */ -extern void _eri0_isp( void ); -extern void _rxi0_isp( void ); -extern void _txi0_isp( void ); -extern void _tei0_isp( void ); -extern void _eri1_isp( void ); -extern void _rxi1_isp( void ); -extern void _txi1_isp( void ); -extern void _tei1_isp( void ); - -/* Parity Control Unit of the Bus State Controllers */ -extern void _prt_isp( void ); - -/* ADC */ -extern void _adu_isp( void ); - -/* Watchdog Timer */ -extern void _wdt_isp( void ); - -/* DRAM refresh control unit of bus state controller */ -extern void _dref_isp( void ); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsps/sh/gensh1/include/sh/sci.h b/bsps/sh/gensh1/include/sh/sci.h deleted file mode 100644 index 5653afca3c..0000000000 --- a/bsps/sh/gensh1/include/sh/sci.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Driver for the sh1 703x on-chip serial devices (sci) - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _sh_sci_h -#define _sh_sci_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Devices are set to 9600 bps, 8 databits, 1 stopbit, no - * parity and asynchronous mode by default. - * - * NOTE: - * The onboard serial devices of the SH do not support hardware - * handshake. - */ - -#define DEVSCI_DRIVER_TABLE_ENTRY \ - { sh_sci_initialize, sh_sci_open, sh_sci_close, sh_sci_read, \ - sh_sci_write, sh_sci_control } - -extern rtems_device_driver sh_sci_initialize( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -extern rtems_device_driver sh_sci_open( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -extern rtems_device_driver sh_sci_close( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -extern rtems_device_driver sh_sci_read( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -extern rtems_device_driver sh_sci_write( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -extern rtems_device_driver sh_sci_control( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsps/sh/gensh1/include/sh/sh7_pfc.h b/bsps/sh/gensh1/include/sh/sh7_pfc.h deleted file mode 100644 index 1045af6af8..0000000000 --- a/bsps/sh/gensh1/include/sh/sh7_pfc.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Bit values for the pin function controller of the Hitachi SH703X - * - * From Hitachi tutorials - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _sh7_pfc_h -#define _sh7_pfc_h - -#include - -/* - * Port B IO Register (PBIOR) - */ -#define PBIOR PFC_PBIOR -#define PB15IOR 0x8000 -#define PB14IOR 0x4000 -#define PB13IOR 0x2000 -#define PB12IOR 0x1000 -#define PB11IOR 0x0800 -#define PB10IOR 0x0400 -#define PB9IOR 0x0200 -#define PB8IOR 0x0100 -#define PB7IOR 0x0080 -#define PB6IOR 0x0040 -#define PB5IOR 0x0020 -#define PB4IOR 0x0010 -#define PB3IOR 0x0008 -#define PB2IOR 0x0004 -#define PB1IOR 0x0002 -#define PB0IOR 0x0001 - -/* - * Port B Control Register (PBCR1) - */ -#define PBCR1 PFC_PBCR1 -#define PB15MD1 0x8000 -#define PB15MD0 0x4000 -#define PB14MD1 0x2000 -#define PB14MD0 0x1000 -#define PB13MD1 0x0800 -#define PB13MD0 0x0400 -#define PB12MD1 0x0200 -#define PB12MD0 0x0100 -#define PB11MD1 0x0080 -#define PB11MD0 0x0040 -#define PB10MD1 0x0020 -#define PB10MD0 0x0010 -#define PB9MD1 0x0008 -#define PB9MD0 0x0004 -#define PB8MD1 0x0002 -#define PB8MD0 0x0001 - -#define PB15MD PB15MD1|PB14MD0 -#define PB14MD PB14MD1|PB14MD0 -#define PB13MD PB13MD1|PB13MD0 -#define PB12MD PB12MD1|PB12MD0 -#define PB11MD PB11MD1|PB11MD0 -#define PB10MD PB10MD1|PB10MD0 -#define PB9MD PB9MD1|PB9MD0 -#define PB8MD PB8MD1|PB8MD0 - -#define PB_TXD1 PB11MD1 -#define PB_RXD1 PB10MD1 -#define PB_TXD0 PB9MD1 -#define PB_RXD0 PB8MD1 - -/* - * Port B Control Register (PBCR2) - */ -#define PBCR2 PFC_PBCR2 -#define PB7MD1 0x8000 -#define PB7MD0 0x4000 -#define PB6MD1 0x2000 -#define PB6MD0 0x1000 -#define PB5MD1 0x0800 -#define PB5MD0 0x0400 -#define PB4MD1 0x0200 -#define PB4MD0 0x0100 -#define PB3MD1 0x0080 -#define PB3MD0 0x0040 -#define PB2MD1 0x0020 -#define PB2MD0 0x0010 -#define PB1MD1 0x0008 -#define PB1MD0 0x0004 -#define PB0MD1 0x0002 -#define PB0MD0 0x0001 - -#define PB7MD PB7MD1|PB7MD0 -#define PB6MD PB6MD1|PB6MD0 -#define PB5MD PB5MD1|PB5MD0 -#define PB4MD PB4MD1|PB4MD0 -#define PB3MD PB3MD1|PB3MD0 -#define PB2MD PB2MD1|PB2MD0 -#define PB1MD PB1MD1|PB1MD0 -#define PB0MD PB0MD1|PB0MD0 - -#endif /* _sh7_pfc_h */ diff --git a/bsps/sh/gensh1/include/sh/sh7_sci.h b/bsps/sh/gensh1/include/sh/sh7_sci.h deleted file mode 100644 index 0b80a485d3..0000000000 --- a/bsps/sh/gensh1/include/sh/sh7_sci.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Bit values for the serial control registers of the Hitachi SH703X - * - * From Hitachi tutorials - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _sh7_sci_h -#define _sh7_sci_h - -#include - -/* - * Serial mode register bits - */ - -#define SCI_SYNC_MODE 0x80 -#define SCI_SEVEN_BIT_DATA 0x40 -#define SCI_PARITY_ON 0x20 -#define SCI_ODD_PARITY 0x10 -#define SCI_STOP_BITS_2 0x08 -#define SCI_ENABLE_MULTIP 0x04 -#define SCI_PHI_64 0x03 -#define SCI_PHI_16 0x02 -#define SCI_PHI_4 0x01 -#define SCI_PHI_0 0x00 - -/* - * Serial register offsets, relative to SCI0_SMR or SCI1_SMR - */ - -#define SCI_SMR 0x00 -#define SCI_BRR 0x01 -#define SCI_SCR 0x02 -#define SCI_TDR 0x03 -#define SCI_SSR 0x04 -#define SCI_RDR 0x05 - -/* - * Serial control register bits - */ -#define SCI_TIE 0x80 /* Transmit interrupt enable */ -#define SCI_RIE 0x40 /* Receive interrupt enable */ -#define SCI_TE 0x20 /* Transmit enable */ -#define SCI_RE 0x10 /* Receive enable */ -#define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */ -#define SCI_TEIE 0x04 /* Transmit end interrupt enable */ -#define SCI_CKE1 0x02 /* Clock enable 1 */ -#define SCI_CKE0 0x01 /* Clock enable 0 */ - -/* - * Serial status register bits - */ -#define SCI_TDRE 0x80 /* Transmit data register empty */ -#define SCI_RDRF 0x40 /* Receive data register full */ -#define SCI_ORER 0x20 /* Overrun error */ -#define SCI_FER 0x10 /* Framing error */ -#define SCI_PER 0x08 /* Parity error */ -#define SCI_TEND 0x04 /* Transmit end */ -#define SCI_MPB 0x02 /* Multiprocessor bit */ -#define SCI_MPBT 0x01 /* Multiprocessor bit transfer */ - -#endif /* _sh7_sci_h */ diff --git a/bsps/sh/gensh1/include/tm27.h b/bsps/sh/gensh1/include/tm27.h deleted file mode 100644 index 0dfa7bf628..0000000000 --- a/bsps/sh/gensh1/include/tm27.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/bsps/sh/gensh1/start/cpu_asm.c b/bsps/sh/gensh1/start/cpu_asm.c deleted file mode 100644 index bd98602ee7..0000000000 --- a/bsps/sh/gensh1/start/cpu_asm.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * This file contains the basic algorithms for all assembly code used - * in an specific CPU port of RTEMS. These algorithms must be implemented - * in assembly language - * - * NOTE: This port uses a C file with inline assembler instructions - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -/* - * This is supposed to be an assembly file. This means that system.h - * and cpu.h should not be included in a "real" cpu_asm file. An - * implementation in assembly should include "cpu_asm.h" - */ - -#include -#include -#include -#include -#include - -#include -#include -#include - -unsigned long *_old_stack_ptr; - -register unsigned long *stack_ptr __asm__ ("r15"); - -/* - * sh_set_irq_priority - * - * this function sets the interrupt level of the specified interrupt - * - * parameters: - * - irq : interrupt number - * - prio: priority to set for this interrupt number - * - * returns: 0 if ok - * -1 on error - */ - -unsigned int sh_set_irq_priority( - unsigned int irq, - unsigned int prio ) -{ - uint32_t shiftcount; - uint32_t prioreg; - uint16_t temp16; - ISR_Level level; - - /* - * first check for valid interrupt - */ - if (( irq > 113) || (_Hardware_isr_Table[irq] == _dummy_isp)) - return -1; - /* - * check for valid irq priority - */ - if ( prio > 15 ) - return -1; - - /* - * look up appropriate interrupt priority register - */ - if ( irq > 71) - { - irq = irq - 72; - shiftcount = 12 - ((irq & ~0x03) % 16); - - switch( irq / 16) - { - case 0: { prioreg = INTC_IPRC; break;} - case 1: { prioreg = INTC_IPRD; break;} - case 2: { prioreg = INTC_IPRE; break;} - default: return -1; - } - } - else - { - shiftcount = 12 - 4 * ( irq % 4); - if ( irq > 67) - prioreg = INTC_IPRB; - else - prioreg = INTC_IPRA; - } - - /* - * Set the interrupt priority register - */ - _ISR_Local_disable( level ); - - temp16 = read16( prioreg); - temp16 &= ~( 15 << shiftcount); - temp16 |= prio << shiftcount; - write16( temp16, prioreg); - - _ISR_Local_enable( level ); - - return 0; -} - -/* - * This routine provides the RTEMS interrupt management. - */ - -void __ISR_Handler( uint32_t vector) -{ - ISR_Level level; - - _ISR_Local_disable( level ); - - _Thread_Dispatch_disable(); - - if ( _ISR_Nest_level == 0 ) - { - /* Install irq stack */ - _old_stack_ptr = stack_ptr; - stack_ptr = _CPU_Interrupt_stack_high; - } - - _ISR_Nest_level++; - - _ISR_Local_enable( level ); - - /* call isp */ - if ( _ISR_Vector_table[ vector]) - (*_ISR_Vector_table[ vector ])( vector ); - - _ISR_Local_disable( level ); - - _Thread_Dispatch_unnest( _Per_CPU_Get() ); - - _ISR_Nest_level--; - - if ( _ISR_Nest_level == 0 ) - /* restore old stack pointer */ - stack_ptr = _old_stack_ptr; - - _ISR_Local_enable( level ); - - if ( _ISR_Nest_level ) - return; - - if ( !_Thread_Dispatch_is_enabled() ) { - return; - } - - if ( _Thread_Dispatch_necessary ) { - _Thread_Dispatch(); - } -} diff --git a/bsps/sh/gensh1/start/ispsh7032.c b/bsps/sh/gensh1/start/ispsh7032.c deleted file mode 100644 index 9857b755ab..0000000000 --- a/bsps/sh/gensh1/start/ispsh7032.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * This file contains the isp frames for the user interrupts. - * From these procedures __ISR_Handler is called with the vector number - * as argument. - * - * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in - * some releases of gcc doesn't properly handle #pragma interrupt, if a - * file contains both isrs and normal functions. - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include -#include - -/* - * This is an exception vector table - * - * It has the same structure like the actual vector table (vectab) - */ -CPU_ISR_raw_handler _Hardware_isr_Table[256]={ -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, -_nmi_isp, _usb_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, -/* trapa 0 -31 */ -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -/* irq 64 ... */ -_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp, -_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp, -_dma0_isp, _dummy_isp, _dma1_isp, _dummy_isp, -_dma2_isp, _dummy_isp, _dma3_isp, _dummy_isp, -_imia0_isp, _imib0_isp, _ovi0_isp, _dummy_isp, -_imia1_isp, _imib1_isp, _ovi1_isp, _dummy_isp, -_imia2_isp, _imib2_isp, _ovi2_isp, _dummy_isp, -_imia3_isp, _imib3_isp, _ovi3_isp, _dummy_isp, -_imia4_isp, _imib4_isp, _ovi4_isp, _dummy_isp, -_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp, -_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp, -_prt_isp, _adu_isp, _dummy_isp, _dummy_isp, -_wdt_isp, -/* 113 */ _dref_isp -}; - -#define Str(a)#a - -/* - * Some versions of gcc and all version of egcs at least until egcs-1.1b - * are not able to handle #pragma interrupt correctly if more than 1 isr is - * contained in a file and when optimizing. - * We try to work around this problem by using the macro below. - */ -#define isp( name, number, func)\ -__asm__ (".global _"Str(name)"\n\t" \ - "_"Str(name)": \n\t" \ - " mov.l r0,@-r15 \n\t" \ - " mov.l r1,@-r15 \n\t" \ - " mov.l r2,@-r15 \n\t" \ - " mov.l r3,@-r15 \n\t" \ - " mov.l r4,@-r15 \n\t" \ - " mov.l r5,@-r15 \n\t" \ - " mov.l r6,@-r15 \n\t" \ - " mov.l r7,@-r15 \n\t" \ - " mov.l r14,@-r15 \n\t" \ - " sts.l pr,@-r15 \n\t" \ - " sts.l mach,@-r15 \n\t" \ - " sts.l macl,@-r15 \n\t" \ - " mov r15,r14 \n\t" \ - " mov.l "Str(name)"_k, r1\n\t" \ - " jsr @r1 \n\t" \ - " mov #"Str(number)", r4\n\t" \ - " mov r14,r15 \n\t" \ - " lds.l @r15+,macl \n\t" \ - " lds.l @r15+,mach \n\t" \ - " lds.l @r15+,pr \n\t" \ - " mov.l @r15+,r14 \n\t" \ - " mov.l @r15+,r7 \n\t" \ - " mov.l @r15+,r6 \n\t" \ - " mov.l @r15+,r5 \n\t" \ - " mov.l @r15+,r4 \n\t" \ - " mov.l @r15+,r3 \n\t" \ - " mov.l @r15+,r2 \n\t" \ - " mov.l @r15+,r1 \n\t" \ - " mov.l @r15+,r0 \n\t" \ - " rte \n\t" \ - " nop \n\t" \ - " .align 2 \n\t" \ - #name"_k: \n\t" \ - ".long "Str(func)); - -/************************************************ - * Dummy interrupt service procedure for - * interrupts being not allowed --> Trap 34 - ************************************************/ -__asm__ (" .section .text\n\ -.global __dummy_isp\n\ -__dummy_isp:\n\ - mov.l r14,@-r15\n\ - mov r15, r14\n\ - trapa #34\n\ - mov.l @r15+,r14\n\ - rte\n\ - nop"); - -/***************************** - * Non maskable interrupt - *****************************/ -isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler); - -/***************************** - * User break controller - *****************************/ -isp( _usb_isp, USB_ISP_V, ___ISR_Handler); - -/***************************** - * External interrupts 0-7 - *****************************/ -isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler); -isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler); -isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler); -isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler); -isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler); -isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler); -isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler); -isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler); - -/***************************** - * DMA - controller - *****************************/ -isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler); -isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler); -isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler); -isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler); - - -/***************************** - * Interrupt timer unit - *****************************/ - -/***************************** - * Timer 0 - *****************************/ -isp( _imia0_isp, IMIA0_ISP_V, ___ISR_Handler); -isp( _imib0_isp, IMIB0_ISP_V, ___ISR_Handler); -isp( _ovi0_isp, OVI0_ISP_V, ___ISR_Handler); - -/***************************** - * Timer 1 - *****************************/ -isp( _imia1_isp, IMIA1_ISP_V, ___ISR_Handler); -isp( _imib1_isp, IMIB1_ISP_V, ___ISR_Handler); -isp( _ovi1_isp, OVI1_ISP_V, ___ISR_Handler); - -/***************************** - * Timer 2 - *****************************/ -isp( _imia2_isp, IMIA2_ISP_V, ___ISR_Handler); -isp( _imib2_isp, IMIB2_ISP_V, ___ISR_Handler); -isp( _ovi2_isp, OVI2_ISP_V, ___ISR_Handler); - -/***************************** - * Timer 3 - *****************************/ -isp( _imia3_isp, IMIA3_ISP_V, ___ISR_Handler); -isp( _imib3_isp, IMIB3_ISP_V, ___ISR_Handler); -isp( _ovi3_isp, OVI3_ISP_V, ___ISR_Handler); - -/***************************** - * Timer 4 - *****************************/ -isp( _imia4_isp, IMIA4_ISP_V, ___ISR_Handler); -isp( _imib4_isp, IMIB4_ISP_V, ___ISR_Handler); -isp( _ovi4_isp, OVI4_ISP_V, ___ISR_Handler); - - -/***************************** - * Serial interfaces - *****************************/ - -/***************************** - * Serial interface 0 - *****************************/ -isp( _eri0_isp, ERI0_ISP_V, ___ISR_Handler); -isp( _rxi0_isp, RXI0_ISP_V, ___ISR_Handler); -isp( _txi0_isp, TXI0_ISP_V, ___ISR_Handler); -isp( _tei0_isp, TEI0_ISP_V, ___ISR_Handler); - -/***************************** - * Serial interface 1 - *****************************/ -isp( _eri1_isp, ERI1_ISP_V, ___ISR_Handler); -isp( _rxi1_isp, RXI1_ISP_V, ___ISR_Handler); -isp( _txi1_isp, TXI1_ISP_V, ___ISR_Handler); -isp( _tei1_isp, TEI1_ISP_V, ___ISR_Handler); - - -/***************************** - * Parity control unit of - * the bus state controller - *****************************/ -isp( _prt_isp, PRT_ISP_V, ___ISR_Handler); - - -/****************************** - * Analog digital converter - * ADC - ******************************/ -isp( _adu_isp, ADU_ISP_V, ___ISR_Handler); - - -/****************************** - * Watchdog timer - ******************************/ -isp( _wdt_isp, WDT_ISP_V, ___ISR_Handler); - - -/****************************** - * DRAM refresh control unit - * of bus state controller - ******************************/ -isp( _dref_isp, DREF_ISP_V, ___ISR_Handler); diff --git a/bsps/sh/gensh1/start/linkcmds b/bsps/sh/gensh1/start/linkcmds deleted file mode 100644 index b74c79fbaf..0000000000 --- a/bsps/sh/gensh1/start/linkcmds +++ /dev/null @@ -1,241 +0,0 @@ -/* - * This is an adapted linker script from egcs-1.0.1 - * - * Memory layout for an SH 7032 with main memory in area 2 - * This memory layout it very similar to that used for Hitachi's - * EVB with CMON in rom - * - * NOTE: The ram start address may vary, all other start addresses are fixed - * Not suiteable for gdb's simulator - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -OUTPUT_ARCH(sh) -ENTRY(_start) -STARTUP(start.o) - -_RamBase = DEFINED(_RamBase) ? _RamBase : 0x0a040000; -_RamSize = DEFINED(_RamSize) ? _RamSize : 512K; -_RamEnd = _RamBase + _RamSize; -_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0; - -MEMORY -{ - rom : o = 0x00000000, l = 128k - onchip_peri : o = 0x05000000, l = 512 - ram : o = 0x0A040000, l = 512k /* enough to link all tests */ - - onchip_ram : o = 0x0f000000, l = 8k -} - -SECTIONS -{ - /* boot vector table */ - .monvects 0x00000000 (NOLOAD): { - _monvects = . ; - } > rom - - /* monitor play area */ - .monram 0x0A040000 (NOLOAD) : - { - _ramstart = .; - } > ram - - /* monitor vector table */ - .vects 0x0A042000 (NOLOAD) : { - _vectab = . ; - *(.vects); - } - - /* Read-only sections, merged into text segment: */ - - . = 0x0a044000 ; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .gnu.version : { *(.gnu.version) } - .gnu.version_d : { *(.gnu.version_d) } - .gnu.version_r : { *(.gnu.version_r) } - .rela.dyn : - { - *(.rela.init) - *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) - *(.rela.fini) - *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) - *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) - *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) - *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) - *(.rela.ctors) - *(.rela.dtors) - *(.rela.got) - *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) - *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) - *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) - *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) - *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) - } >ram - .rel.text : - { *(.rel.text) *(.rel.gnu.linkonce.t*) } - .rel.data : - { *(.rel.data) *(.rel.gnu.linkonce.d*) } - .rel.rodata : - { *(.rel.rodata*) *(.rel.gnu.linkonce.r*) } - .rel.got : { *(.rel.got) } - .rel.ctors : { *(.rel.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rel.init : { *(.rel.init) } - .rel.fini : { *(.rel.fini) } - .rel.bss : { *(.rel.bss) } - .rel.plt : { *(.rel.plt) } - .plt : { *(.plt) } - .text . : - { - _start = .; - *(.text*) - *(.stub) - - /* - * Special FreeBSD sysctl sections. - */ - . = ALIGN (16); - __start_set_sysctl_set = .; - ___start_set_sysctl_set = .; - *(set_sysc*); /* set_sysctl_* but name is truncated by SH-coff */ - __stop_set_sysctl_set = ABSOLUTE(.); - ___stop_set_sysctl_set = ABSOLUTE(.); - *(set_doma*); /* set_domain_* but name is truncated by SH-coff */ - *(set_pseu*); /* set_pseudo_* but name is truncated by SH-coff */ - - /* .gnu.warning sections are handled specially by elf32.em. */ - *(.gnu.warning) - *(.gnu.linkonce.t*) - } > ram - _etext = .; - PROVIDE (etext = .); - .init . : { KEEP(*(.init)) } > ram =0 - .fini . : { KEEP(*(.fini)) } > ram =0 - .ctors . : { KEEP(*(.ctors)) } > ram =0 - .dtors . : { KEEP(*(.dtors)) } > ram =0 - .rodata . : { *(.rodata*) KEEP (*(SORT(.rtemsroset.*))) *(.gnu.linkonce.r*) } > ram - .rodata1 . : { *(.rodata1) } > ram - .tdata : { - __TLS_Data_begin = .; - *(.tdata .tdata.* .gnu.linkonce.td.*) - __TLS_Data_end = .; - } > ram - .tbss : { - __TLS_BSS_begin = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) - __TLS_BSS_end = .; - } > ram - __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin; - __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin; - __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin; - __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin; - __TLS_Size = __TLS_BSS_end - __TLS_Data_begin; - __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); - /* Adjust the address for the data segment. We want to adjust up to - the same address within the page on the next page up. */ - . = ALIGN(128) + (. & (128 - 1)); - .data . : - { - *(.data*) - KEEP (*(SORT(.rtemsrwset.*))) - *(.gcc_exc*) - ___EH_FRAME_BEGIN__ = .; - *(.eh_fram*) - ___EH_FRAME_END__ = .; - LONG(0); - *(.gcc_except_table*) - *(.gnu.linkonce.d*) - CONSTRUCTORS - } > ram - .data1 . : { *(.data1) } - .got . : { *(.got.plt) *(.got) } - .dynamic . : { *(.dynamic) } - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - .sdata . : { *(.sdata) } - _edata = .; - PROVIDE (edata = .); - __bss_start = .; - .sbss . : { *(.sbss*) *(.scommon) } - .bss . : - { - *(.dynbss) - *(.bss .bss* .gnu.linkonce.b*) - *(COMMON) - } > ram - _end = . ; - PROVIDE (end = .); - - .noinit (NOLOAD) : { - *(SORT_BY_NAME (SORT_BY_ALIGNMENT (.noinit*))) - } > ram - - .rtemsstackinterrupt (NOLOAD) : { - *(.rtemsstack.interrupt) - } > onchip_ram - - .rtemsstack (NOLOAD) : { - *(SORT(.rtemsstack.*)) - } > ram - - _WorkAreaBase = . ; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* These must appear regardless of . */ - - /* Addition to let linker know about custom section for GDB pretty-printing support. */ - .debug_gdb_scripts 0 : { *(.debug_gdb_scripts) } -} diff --git a/bsps/sh/gensh1/start/start.S b/bsps/sh/gensh1/start/start.S deleted file mode 100644 index 88b2512a6e..0000000000 --- a/bsps/sh/gensh1/start/start.S +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include - - BEGIN_CODE - PUBLIC(start) -SYM (start): - ! install the stack pointer - mov.l stack_k,r15 - - ! zero out bss - mov.l edata_k,r0 - mov.l end_k,r1 - mov #0,r2 -0: - mov.l r2,@r0 - add #4,r0 - cmp/ge r0,r1 - bt 0b - - ! copy the vector table from rom to ram - mov.l vects_k,r0 ! vectab - mov #0,r1 ! address of boot vector table - mov #0,r2 ! number of bytes copied - mov.w vects_size,r3 ! size of entries in vectab -1: - mov.l @r1+,r4 - mov.l r4,@r0 - add #4,r0 - add #1,r2 - cmp/hi r3,r2 - bf 1b - - mov.l vects_k,r0 ! update vbr to point to vectab - ldc r0,vbr - - ! call the mainline - mov #0,r4 ! command line - mov.l main_k,r0 - jsr @r0 - - ! call exit - mov r0,r4 - mov.l exit_k,r0 - jsr @r0 - or r0,r0 - - END_CODE - - .align 2 -stack_k: - .long SYM(_ISR_Stack_area_end) -edata_k: - .long SYM(edata) -end_k: - .long SYM(end) -main_k: - .long SYM(boot_card) -exit_k: - .long SYM(exit) - -vects_k: - .long SYM(vectab) -vects_size: - .word 255 diff --git a/bsps/sh/gensh2/README.md b/bsps/sh/gensh2/README.md deleted file mode 100644 index e24249c39c..0000000000 --- a/bsps/sh/gensh2/README.md +++ /dev/null @@ -1,224 +0,0 @@ -gensh2 -====== - - Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) - Adapted by: John Mills (jmills@tga.com) - Corrections: Radzislaw Galler (rgaller@et.put.poznan.pl) - - -``` -BSP NAME: generic SH2 (gensh2) -BOARD: EVB7045F (note 2) -BUS: n/a -CPU FAMILY: Hitachi SH -CPU: SH 7045F -COPROCESSORS: none -MODE: n/a - -DEBUG MONITOR: gdb -``` - -PERIPHERALS ------------ -``` -TIMERS: on-chip - RESOLUTION: cf. Hitachi SH 704X Hardware Manual (Phi/16) -SERIAL PORTS: on-chip (with 2 ports) -REAL-TIME CLOCK: none -DMA: not used -VIDEO: none -SCSI: none -NETWORKING: none -``` - -DRIVER INFORMATION ------------------- -``` -CLOCK DRIVER: on-chip timer -IOSUPP DRIVER: default -SHMSUPP: default -TIMER DRIVER: on-chip timer -TTY DRIVER: /dev/console -``` - -STDIO ------ -``` -PORT: /dev/sci0 -ELECTRICAL: SCI0 -BAUD: 9600 -BITS PER CHARACTER: 8 -PARITY: NONE -STOP BITS: 1 -``` - -NOTES ------ -(1) The present 'hw_init.c' file provides 'early_hw_init'(void) which - is normally called from 'start.S' to provide such minimal HW setup - as is conveniently written in 'C' and can make use of global - symbols for 7045F processor elements. It also provides - 'void bsp_hw_init (void)' normally called from 'bspstart.c', shortly - before RTEMS itself is started. - - These are both minimal functions intended to support the RTEMS test - suites. - -(2) See README.EVB7045F - - - -Getting started with EVB7045F and gensh2 ----------------------------------------- -Author: Radzislaw Galler (rgaller@et.put.poznan.pl) - -This is a capture of success path to put a RTEMS sample -'hello.exe' on the evaluation board EVB7045F. - - -What you need -------------- - * Computer with two operating systems: Linux and Wndows 2000 (tm) - - that was in my case (see section 'Variations') - - * Flash Development Toolkit (FDT) - available on HMSE homepage - (http://www.hmse.com/products/fdt/support.htm) - - * 'gdbstubs' - available on SourceForge - (http://sourceforge.net/projects/gdbstubs/) - - * working GNU C compiler for Hitach SH processors; do-it-yourself - (on Linux) or download ready stuff for Windows'9x/NT/2k from - (http://www.hitachi-eu.com/hel/ecg/) or from Hitach Databook 2001 - CD-ROM (if no luck try to search on the net for gnu99r1p1.zip) - - * GDB compiled for target sh-rtems - do-it-yourself or download - from ftp://ftp.oarcorp.com:21/pub/rtems/snapshots/c_tools/ - - * RTEMS (ofcourse) you probably already have if you are reading this - document - -Instalation of 'gdbstubs' -------------------------- - Once you downladed and unzipped gdbstubs you have to compile - it. First modify the Makefile to use the compiler installed on your - machine. Then issue the command: - - $ make - - This should produce the default target sh2-7045edk.out. This is the - S-record file which should be added to FDT project (renaming it to - *.mot extension helps a bit). - If you are lucky you will be able to put the file into the FLASH - following the instuctions in FDT and EVB manuals. - - Well I wasn't lucky so I had to bypass the Universal Programming - Board (see EVB7045F User Manual) and manually put the processor into - BOOT mode. This can be done by shortening the capacitor C8 (or C108 - on schematics) which puts the UPB into permanent reset state, and by - removing jumper JP4 (or JP104 on schematics) and connecting its - middle pin to the ground. After pressing CRES button the processor - is in BOOT mode. In FDT select "direct connection": - - Menu Project->Properties->Device->Select Interface - - After that there should be no problem in putting the program into the - FLASH. - -Loading 'hello.exe' on board ----------------------------- - I assume you are able to compile RTEMS with 'gensh2' BSP and - necessary tools. If not please refer to 'started.pdf' document which - describes the procedure (http://www.oarcorp.com/). - - At the time of writing this document 'gdbstubs' default - communication port was SCI1. So it was the default port for - /dev/console in RTEMS. To avoid problems I had check these settings - both in 'gdbstubs' and $RTEMS_ROOT/c/src/lib/libbsp/sh/gensh2/include/bsp.h - - After changing the line - -```c - #define BSP_CONSOLE_DEVNAME "/dev/sci1" -``` - - to - -```c - #define BSP_CONSOLE_DEVNAME "/dev/sci0" -``` - in 'bsp.h' and rebuilding RTEMS there should no problem in running - 'hello.exe' and other samples. - - For downloading connect a serial cable to computer and EVB. You will - also need a second cable and second serial port to see the effects - of your work. - - Assuming you are working in Linux and Xwindows fire up two terminal - windows. In the first one run sh-rtems-gdb, in the second run a - serial port terminal (for example 'minicom'). Set up the serial - terminal to a port connected to SCI0 and leave the window in a - visible place on the desktop. The debugger should be invoked best - from the directory where 'hello.exe' is placed. Assuming that here - is a GDB session: - - --------start------ - -```shell - $ sh-rtems-gdb hello.exe - GNU gdb 5.0 - Copyright 2000 Free Software Foundation, Inc. - GDB is free software, covered by the GNU General Public License, and you are - welcome to change it and/or distribute copies of it under certain conditions. - Type "show copying" to see the conditions. - There is absolutely no warranty for GDB. Type "show warranty" for details. - This GDB was configured as "--host=i686-pc-linux-gnu --target=sh-rtems"... - (gdb) set remotebaud 115200 - (gdb) target remote /dev/ttyS0 - Remote debugging using /dev/ttyS0 - 0x0 in ?? () - (gdb) load - Loading section .text, size 0x12d70 lma 0x444000 - Loading section .data, size 0xb80 lma 0x456df0 - Loading section .stack, size 0x10 lma 0xfffffec0 - Start address 0x444000 , load size 80128 - Transfer rate: 58274 bits/sec, 153 bytes/write. - (gdb) continue - Continuing. - - Program received signal 0, Signal 0. - 0x44ec36 in exit (code=0) at exit.c:70 - 70 exit.c: No such file or directory. - (gdb) - --------end------- -``` - And here is a capture from the serial terminal window: - -```shell -*** HELLO WORLD TEST *** -Hello World -*** END OF HELLO WORLD TEST *** - - Beautiful, isn't it? That's all! -``` - - -Variations ----------- - I'm sure that not every one can afford having two operating systems - on one computer. I believe there will be a day that nobody will need - an MS stuff anymore... ;) - - It is possible to repeat the success on MS Windows only. To do the - same on Linux only you need a tool to downlad 'gdbstubs' on the - board. This should be no problem to find it on the net but right now - I don't know about it. - - For your convenience there are several graphical interfaces for GDB - available on the net. I just name two of them: - - DDD - stands for Data Display Debugger - (http://www.gnu.org/software/ddd/) - - Insight - a Tcl/Tk interface available both for MS Windows and - Xwindows (http://sources.redhat.com/insight/) diff --git a/bsps/sh/gensh2/btimer/btimer.c b/bsps/sh/gensh2/btimer/btimer.c deleted file mode 100644 index 152c99b1aa..0000000000 --- a/bsps/sh/gensh2/btimer/btimer.c +++ /dev/null @@ -1,191 +0,0 @@ -/** - * @file - * @brief Timer for the Hitachi SH 704X - */ - -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include -#include - -#include -#include - -extern uint32_t bsp_clicks_per_second; - -/* - * We use a Phi/4 timer - */ -#define SCALE (Timer_MHZ/4) - -#define MTU1_STARTMASK 0xfd -#define MTU1_SYNCMASK 0xfd -#define MTU1_MODEMASK 0xc0 -#define MTU1_TCRMASK 0x01 -#define MTU1_TIORMASK 0x88 -#define MTU1_STAT_MASK 0xf8 -#define MTU1_TIERMASK 0xfc -#define IPRC_MTU1_MASK 0xfff0 - -#ifndef MTU1_PRIO -#define MTU1_PRIO 15 -#endif - -#define MTU1_VECTOR 86 - -extern rtems_isr timerisr(void); - -static uint32_t Timer_interrupts; - -bool benchmark_timer_find_average_overhead; - -static uint32_t Timer_MHZ ; - -void benchmark_timer_initialize( void ) -{ - uint8_t temp8; - uint16_t temp16; - rtems_interrupt_level level; - rtems_isr *ignored; - - Timer_MHZ = bsp_clicks_per_second / 1000000 ; - - /* - * Timer has never overflowed. This may not be necessary on some - * implemenations of timer but .... - */ - - Timer_interrupts /* .i */ = 0; - rtems_interrupt_disable( level ); - - /* - * Somehow start the timer - */ - /* stop Timer 1 */ - temp8 = read8(MTU_TSTR) & MTU1_STARTMASK; - write8( temp8, MTU_TSTR ); - - /* initialize counter 1 */ - write16( 0, MTU_TCNT1); - - /* Timer 1 is independent of other timers */ - temp8 = read8(MTU_TSYR) & MTU1_SYNCMASK; - write8( temp8, MTU_TSYR ); - - /* Timer 1, normal mode */ - temp8 = read8(MTU_TMDR1) & MTU1_MODEMASK; - write8( temp8, MTU_TMDR1 ); - - /* x0000000 - * |||||+++--- Internal Clock - * |||++------ Count on rising edge - * |++-------- disable TCNT clear - * +---------- don`t care - */ - write8( MTU1_TCRMASK, MTU_TCR1 ); - - /* gra and grb are not used */ - write8( MTU1_TIORMASK, MTU_TIOR1 ); - - /* reset all status flags */ - temp8 = read8(MTU_TSR1) & MTU1_STAT_MASK; - write8( temp8, MTU_TSR1 ); - - /* enable overflow interrupt */ - write8( MTU1_TIERMASK, MTU_TIER1 ); - - /* set interrupt priority */ - temp16 = read16(INTC_IPRC) & IPRC_MTU1_MASK; - temp16 |= MTU1_PRIO; - write16( temp16, INTC_IPRC); - - /* initialize ISR */ - _CPU_ISR_install_raw_handler( MTU1_VECTOR, timerisr, &ignored ); - rtems_interrupt_enable( level ); - - /* start timer 1 */ - temp8 = read8(MTU_TSTR) | ~MTU1_STARTMASK; - write8( temp8, MTU_TSTR ); -} - -/* - * The following controls the behavior of benchmark_timer_read(). - * - * AVG_OVERHEAD is the overhead for starting and stopping the timer. It - * is usually deducted from the number returned. - * - * LEAST_VALID is the lowest number this routine should trust. Numbers - * below this are "noise" and zero is returned. - */ - -#define AVG_OVERHEAD 1 /* It typically takes X.X microseconds */ - /* (Y countdowns) to start/stop the timer. */ - /* This value is in microseconds. */ -#define LEAST_VALID 0 /* 20 */ /* Don't trust a clicks value lower than this */ - -benchmark_timer_t benchmark_timer_read( void ) -{ - uint32_t clicks; - uint32_t total ; - /* - * Read the timer and see how many clicks it has been since we started. - */ - - - clicks = read16( MTU_TCNT1 ); /* XXX: read some HW here */ - - /* - * Total is calculated by taking into account the number of timer overflow - * interrupts since the timer was initialized and clicks since the last - * interrupts. - */ - - total = clicks + Timer_interrupts * 65536; - - if ( benchmark_timer_find_average_overhead ) - return total / SCALE; /* in XXX microsecond units */ - else - { - if ( total < LEAST_VALID ) - return 0; /* below timer resolution */ - /* - * Somehow convert total into microseconds - */ - return (total / SCALE - AVG_OVERHEAD) ; - } -} - -void benchmark_timer_disable_subtracting_average_overhead(bool find_flag) -{ - benchmark_timer_find_average_overhead = find_flag; -} - -/* Timer 1 is used */ - -#pragma interrupt -void timerisr( void ) -{ - uint8_t temp8; - - /* reset the flags of the status register */ - temp8 = read8(MTU_TSR1) & MTU1_STAT_MASK; - write8( temp8, MTU_TSR1 ); - - Timer_interrupts += 1; -} diff --git a/bsps/sh/gensh2/clock/ckinit.c b/bsps/sh/gensh2/clock/ckinit.c deleted file mode 100644 index 7b5c789e91..0000000000 --- a/bsps/sh/gensh2/clock/ckinit.c +++ /dev/null @@ -1,234 +0,0 @@ -/* - * This file contains the clock driver the Hitachi SH 704X - */ - -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * Modified to reflect registers of sh7045 processor: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * August, 1999 - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include - -#include - -#include -#include -#include -#include -#include - -static void Clock_exit( void ); - -extern uint32_t bsp_clicks_per_second; - -#define _MTU_COUNTER0_MICROSECOND (Clock_MHZ/16) - -#ifndef CLOCKPRIO -#define CLOCKPRIO 10 -#endif - -#define MTU0_STARTMASK 0xfe -#define MTU0_SYNCMASK 0xfe -#define MTU0_MODEMASK 0xc0 -#define MTU0_TCRMASK 0x22 /* bit 7 also used, vs 703x */ -#define MTU0_STAT_MASK 0xc0 -#define MTU0_IRQMASK 0xfe -#define MTU0_TIERMASK 0x01 -#define IPRC_MTU0_MASK 0xff0f -#define MTU0_TIORVAL 0x08 - -/* - * The interrupt vector number associated with the clock tick device - * driver. - */ - -#define CLOCK_VECTOR MTUA0_ISP_V - -/* - * Clock_driver_ticks is a monotonically increasing counter of the - * number of clock ticks since the driver was initialized. - */ -volatile uint32_t Clock_driver_ticks; - -static rtems_isr Clock_isr( rtems_vector_number vector ); -static uint32_t Clock_MHZ ; - -/* - * Clock_isrs is the number of clock ISRs until the next invocation of - * the RTEMS clock tick routine. The clock tick device driver - * gets an interrupt once a millisecond and counts down until the - * length of time between the user configured microseconds per tick - * has passed. - */ -uint32_t Clock_isrs; /* ISRs until next tick */ -static uint32_t Clock_isrs_const; /* only calculated once */ - -/* - * The previous ISR on this clock tick interrupt vector. - */ -rtems_isr_entry Old_ticker; - -/* - * Isr Handler - */ -static rtems_isr Clock_isr( - rtems_vector_number vector -) -{ - /* - * bump the number of clock driver ticks since initialization - * - - * determine if it is time to announce the passing of tick as configured - * to RTEMS through the rtems_clock_tick directive - * - * perform any timer dependent tasks - */ - uint8_t temp; - - /* reset the flags of the status register */ - temp = read8( MTU_TSR0) & MTU0_STAT_MASK; - write8( temp, MTU_TSR0); - - Clock_driver_ticks++ ; - - if( Clock_isrs == 1) - { - rtems_clock_tick(); - Clock_isrs = Clock_isrs_const; - } - else - { - Clock_isrs-- ; - } -} - -/* - * Install_clock - * - * Install a clock tick handler and reprograms the chip. This - * is used to initially establish the clock tick. - */ -static void Install_clock( - rtems_isr_entry clock_isr -) -{ - uint8_t temp8 = 0; - uint32_t factor = 1000000; - - /* - * Initialize the clock tick device driver variables - */ - - Clock_driver_ticks = 0; - Clock_isrs_const = rtems_configuration_get_microseconds_per_tick() / 10000; - Clock_isrs = Clock_isrs_const; - - factor /= rtems_configuration_get_microseconds_per_tick(); /* minimalization of integer division error */ - Clock_MHZ = bsp_clicks_per_second / factor ; - - rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker ); - - /* - * Hardware specific initialize goes here - */ - - /* stop Timer 0 */ - temp8 = read8( MTU_TSTR) & MTU0_STARTMASK; - write8( temp8, MTU_TSTR); - - /* set initial counter value to 0 */ - write16( 0, MTU_TCNT0); - - /* Timer 0 runs independent */ - temp8 = read8( MTU_TSYR) & MTU0_SYNCMASK; - write8( temp8, MTU_TSYR); - - /* Timer 0 normal mode */ - temp8 = read8( MTU_TMDR0) & MTU0_MODEMASK; - write8( temp8, MTU_TMDR0); - - /* TCNT is cleared by GRA ; internal clock /16 */ - write8( MTU0_TCRMASK , MTU_TCR0); - - /* use GRA without I/O - pins */ - write8( MTU0_TIORVAL, MTU_TIORL0); - - /* reset flags of the status register */ - temp8 = read8( MTU_TSR0) & MTU0_STAT_MASK; - write8( temp8, MTU_TSR0); - - /* Irq if is equal GRA */ - temp8 = read8( MTU_TIER0) | MTU0_TIERMASK; - write8( temp8, MTU_TIER0); - - /* set interrupt priority */ - if( sh_set_irq_priority( CLOCK_VECTOR, CLOCKPRIO ) != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); - - /* set counter limits */ - write16( _MTU_COUNTER0_MICROSECOND, MTU_GR0A); - - /* start counter */ - temp8 = read8( MTU_TSTR) |~MTU0_STARTMASK; - write8( temp8, MTU_TSTR); - - /* - * Schedule the clock cleanup routine to execute if the application exits. - */ - atexit( Clock_exit ); -} - -/* - * Clean up before the application exits - */ -void Clock_exit( void ) -{ - uint8_t temp8 = 0; - - /* turn off the timer interrupts */ - /* set interrupt priority to 0 */ - if( sh_set_irq_priority( CLOCK_VECTOR, 0 ) != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred( RTEMS_UNSATISFIED); - -/* - * temp16 = read16( MTU_TIER0) & IPRC_MTU0_IRQMASK; - * write16( temp16, MTU_TIER0); - */ - - /* stop counter */ - temp8 = read8( MTU_TSTR) & MTU0_STARTMASK; - write8( temp8, MTU_TSTR); - - /* old vector shall not be installed */ -} - -void _Clock_Initialize( void ) -{ - Install_clock( Clock_isr ); -} diff --git a/bsps/sh/gensh2/config/gensh2-testsuite.tcfg b/bsps/sh/gensh2/config/gensh2-testsuite.tcfg deleted file mode 100644 index ddc6dc6d22..0000000000 --- a/bsps/sh/gensh2/config/gensh2-testsuite.tcfg +++ /dev/null @@ -1,13 +0,0 @@ -# -# gensh2 RTEMS Test Database. -# -# Format is one line per test that is _NOT_ built. -# - -include: testdata/disable-iconv-tests.tcfg -exclude: fileio -exclude: fsdosfsname01 -exclude: iostream -exclude: linpack -exclude: record02 -exclude: utf8proc01 diff --git a/bsps/sh/gensh2/config/gensh2.cfg b/bsps/sh/gensh2/config/gensh2.cfg deleted file mode 100644 index 49cf0850d2..0000000000 --- a/bsps/sh/gensh2/config/gensh2.cfg +++ /dev/null @@ -1,21 +0,0 @@ -# -# gensh2.cfg -# -# default configuration for Hitachi sh1 processors -# -# Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) -# - -include $(RTEMS_ROOT)/make/custom/default.cfg - -RTEMS_CPU=sh - -# This contains the compiler options necessary to select the CPU model -# and (hopefully) optimize for it. -CPU_CFLAGS = -m2 - -# optimize flag: typically -O2 -CFLAGS_OPTIMIZE_V = -O2 -g -CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections - -LDFLAGS = -Wl,--gc-sections diff --git a/bsps/sh/gensh2/console/config.c b/bsps/sh/gensh2/console/config.c deleted file mode 100644 index 33ed1bd76e..0000000000 --- a/bsps/sh/gensh2/console/config.c +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * This file contains the TTY driver table. The implementation is - * based on libchip/serial drivers, but it uses internal SHx SCI so - * the implementation of the driver is placed in - * lib/libcpu/sh/sh7045/sci instead of libchip/serial. - * - * COPYRIGHT (c) 1989-2001. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Function set for interrupt enabled termios console - */ -const console_fns sh_sci_fns = -{ - libchip_serial_default_probe, /* deviceProbe */ - sh_sci_first_open, /* deviceFirstOpen */ - NULL, /* deviceLastClose */ - NULL, /* deviceRead */ - sh_sci_write_support_int, /* deviceWrite */ - sh_sci_initialize_interrupts, /* deviceInitialize */ - sh_sci_write_polled, /* deviceWritePolled */ - sh_sci_set_attributes, /* deviceSetAttributes */ - true /* deviceOutputUsesInterrupts */ -}; - -/* - * Function set for polled termios console - */ -const console_fns sh_sci_fns_polled = -{ - libchip_serial_default_probe, /* deviceProbe */ - sh_sci_first_open, /* deviceFirstOpen */ - sh_sci_last_close, /* deviceLastClose */ - sh_sci_inbyte_nonblocking_polled, /* deviceRead */ - sh_sci_write_support_polled, /* deviceWrite */ - sh_sci_init, /* deviceInitialize */ - sh_sci_write_polled, /* deviceWritePolled */ - sh_sci_set_attributes, /* deviceSetAttributes */ - false /* deviceOutputUsesInterrupts */ -}; - -#if 1 /* (CONSOLE_USE_INTERRUPTS) */ -#define SCI_FUNCTIONS &sh_sci_fns -#else -#define SCI_FUNCTIONS &sh_sci_fns_polled -#endif - -static const struct termios term1 = { - 0, - 0, - 0, - 0, - {0}, - B9600 | CS8, - B9600 | CS8 -}; - -static const struct termios term2 = { - 0, - 0, - 0, - 0, - {0}, - B115200 | CS8, - B115200 | CS8 -}; - -console_tbl Console_Configuration_Ports[] = { - { - "/dev/sci0", /* sDeviceName */ - SERIAL_CUSTOM, /* deviceType */ - SCI_FUNCTIONS, /* pDeviceFns */ - NULL, /* deviceProbe */ - NULL, /* pDeviceFlow */ - 16, /* ulMargin */ - 8, /* ulHysteresis */ - (void *)&term1, /* baud rate */ /* pDeviceParams */ - SCI_SMR0, /* ulCtrlPort1 */ - 3, /* ulCtrlPort2 as IRQ priority level*/ - TXI0_ISP_V, /* ulDataPort as TX end vector number*/ - NULL, /* unused */ /* getRegister */ - NULL, /* unused */ /* setRegister */ - NULL, /* unused */ /* getData */ - NULL, /* unused */ /* setData */ - 0, /* ulClock */ - RXI0_ISP_V, /* ulIntVector as RX end vector number*/ - }, - { - "/dev/sci1", /* sDeviceName */ - SERIAL_CUSTOM, /* deviceType */ - SCI_FUNCTIONS, /* pDeviceFns */ - NULL, /* deviceProbe */ - NULL, /* pDeviceFlow */ - 16, /* ulMargin */ - 8, /* ulHysteresis */ - (void *)&term2, /* baud rate */ /* pDeviceParams */ - SCI_SMR1, /* ulCtrlPort1 */ - 3, /* ulCtrlPort2 as IRQ priority level*/ - TXI1_ISP_V, /* ulDataPort as TX end vector number*/ - NULL, /* unused */ /* getRegister */ - NULL, /* unused */ /* setRegister */ - NULL, /* unused */ /* getData */ - NULL, /* unused */ /* setData */ - 0, /* ulClock */ - RXI1_ISP_V, /* ulIntVector as RX end vector number*/ - } -}; - -/* - * Declare some information used by the console driver - */ - -#define NUM_CONSOLE_PORTS (sizeof(Console_Configuration_Ports)/sizeof(console_tbl)) - -unsigned long Console_Configuration_Count = NUM_CONSOLE_PORTS; diff --git a/bsps/sh/gensh2/console/sci.c b/bsps/sh/gensh2/console/sci.c deleted file mode 100644 index ba7f8bc832..0000000000 --- a/bsps/sh/gensh2/console/sci.c +++ /dev/null @@ -1,553 +0,0 @@ -/* - * /dev/sci[0|1] for Hitachi SH 704X - * - * The SH doesn't have a designated console device. Therefore we "alias" - * another device as /dev/console and revector all calls to /dev/console - * to this device. - * - * This approach is similar to installing a sym-link from one device to - * another device. If rtems once will support sym-links for devices files, - * this implementation could be dropped. - */ - -/* - * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modified to reflect sh7045 processor: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - */ - -#include - - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include - -#ifndef STANDALONE_EVB -#define STANDALONE_EVB 0 -#endif - -/* - * NOTE: Some SH variants have 3 sci devices - */ - -#define SCI_MINOR_DEVICES 2 - -/* - * FIXME: sh7045 register names match Hitachi data book, - * but conflict with RTEMS sh7032 usage. - */ - -#define SH_SCI_BASE_0 SCI_SMR0 -#define SH_SCI_BASE_1 SCI_SMR1 - -#define SH_SCI_DEF_COMM_0 CS8, B9600 -#define SH_SCI_DEF_COMM_1 CS8, B9600 - -struct scidev_t { - char * name; - uint32_t addr; - rtems_device_minor_number minor; - unsigned short opened; - tcflag_t cflags; - speed_t spd; -} sci_device[SCI_MINOR_DEVICES] = -{ - { "/dev/sci0", SH_SCI_BASE_0, 0, 0, SH_SCI_DEF_COMM_0 }, - { "/dev/sci1", SH_SCI_BASE_1, 1, 0, SH_SCI_DEF_COMM_1 } -}; - -/* local data structures maintain hardware configuration */ -#if UNUSED -static sci_setup_t sio_param[2]; -#endif - -/* Translate termios' tcflag_t into sci settings */ -static int _sci_set_cflags( - struct scidev_t *sci_dev, - tcflag_t c_cflag, - speed_t spd -) -{ - uint8_t smr; - uint8_t brr; - - if ( spd ) - { - if ( _sci_get_brparms( spd, &smr, &brr ) != 0 ) - return -1; - } - - if ( c_cflag & CSIZE ) - { - if ( c_cflag & CS8 ) - smr &= ~SCI_SEVEN_BIT_DATA; - else if ( c_cflag & CS7 ) - smr |= SCI_SEVEN_BIT_DATA; - else - return -1; - } - - if ( c_cflag & CSTOPB ) - smr |= SCI_STOP_BITS_2; - else - smr &= ~SCI_STOP_BITS_2; - - if ( c_cflag & PARENB ) - smr |= SCI_PARITY_ON; - else - smr &= ~SCI_PARITY_ON; - - if ( c_cflag & PARODD ) - smr |= SCI_ODD_PARITY; - else - smr &= ~SCI_ODD_PARITY; - - write8( smr, sci_dev->addr + SCI_SMR ); - write8( brr, sci_dev->addr + SCI_BRR ); - - return 0; -} - -/* - * local functions operate SCI ports 0 and 1 - * called from polling routines or ISRs - */ -static bool wrtSCI0(unsigned char ch) -{ - uint8_t temp; - bool result = false; - - if ((read8(SCI_SSR0) & SCI_TDRE) != 0x00) { - /* Write the character to the TDR */ - write8(ch, SCI_TDR0); - /* Clear the TDRE bit */ - temp = read8(SCI_SSR0) & ~SCI_TDRE; - write8(temp, SCI_SSR0); - result = true; - } - return result; -} /* wrtSCI0 */ - -static bool wrtSCI1(unsigned char ch) -{ - uint8_t temp; - bool result = false; - - if ((read8(SCI_SSR1) & SCI_TDRE) != 0x00) { - /* Write the character to the TDR */ - write8(ch, SCI_TDR1); - /* Clear the TDRE bit */ - temp = read8(SCI_SSR1) & ~SCI_TDRE; - write8(temp, SCI_SSR1); - result = true; - } - return result; -} /* wrtSCI1 */ - -/* polled output steers byte to selected port */ -static void sh_sci_outbyte_polled( - rtems_device_minor_number minor, - char ch ) -{ - if (minor == 0) /* blocks until port ready */ - while (wrtSCI0(ch) != true); /* SCI0*/ - else - while (wrtSCI1(ch) != true); /* SCI1*/ -} /* sh_sci_outbyte_polled */ - -/* - * Initial version calls polled output driver and blocks - */ -static void outbyte( - rtems_device_minor_number minor, - char ch) -{ - sh_sci_outbyte_polled(minor, (unsigned char)ch); -} /* outbyte */ - -static bool rdSCI0(unsigned char *ch) -{ - uint8_t temp; - bool result = false; - - if ((read8(SCI_SSR0) & SCI_RDRF) != 0x00) { - /* read input */ - *ch = read8(SCI_RDR0); - /* Clear RDRF flag */ - temp = read8(SCI_SSR0) & ~SCI_RDRF; - write8(temp, SCI_SSR0); - /* Check for transmission errors */ - if (temp & (SCI_ORER | SCI_FER | SCI_PER)) { - /* TODO: report to RTEMS transmission error */ - - /* clear error flags*/ - temp &= ~(SCI_ORER | SCI_FER | SCI_PER); - write8(temp, SCI_SSR0); - } - result = true; - } - return result; -} /* rdSCI0 */ - -static bool rdSCI1(unsigned char *ch) -{ - uint8_t temp; - bool result = false; - - if ((read8(SCI_SSR1) & SCI_RDRF) != 0x00) { - /* read input */ - *ch = read8(SCI_RDR1); - /* Clear RDRF flag */ - temp= read8(SCI_SSR1) & ~SCI_RDRF; - write8(temp, SCI_SSR1); - /* Check for transmission errors */ - if (temp & (SCI_ORER | SCI_FER | SCI_PER)) { - /* TODO: report to RTEMS transmission error */ - - /* clear error flags*/ - temp &= ~(SCI_ORER | SCI_FER | SCI_PER); - write8(temp, SCI_SSR1); - } - result = true; - } - return result; -} /* rdSCI1 */ - -/* initial version pulls byte from selected port */ -static char sh_sci_inbyte_polled( rtems_device_minor_number minor ) -{ - uint8_t ch = 0; - - if (minor == 0) /* blocks until char.ready */ - while (rdSCI0(&ch) != true); /* SCI0 */ - else - while (rdSCI1(&ch) != true); /* SCI1 */ - return ch; -} /* sh_sci_inbyte_polled */ - -/* Initial version calls polled input driver */ -static char inbyte( rtems_device_minor_number minor ) -{ - char ch; - - ch = sh_sci_inbyte_polled(minor); - return ch; -} /* inbyte */ - -/* sh_sci_initialize - * - * This routine initializes (registers) the sh_sci IO drivers. - * - * Input parameters: ignored - * - * Output parameters: NONE - * - * Return values: RTEMS_SUCCESSFUL - * if all sci[...] register, else calls - * rtems_fatal_error_occurred(status) - */ -rtems_device_driver sh_sci_initialize( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg ) -{ - rtems_device_driver status; - rtems_device_minor_number i; - - /* - * register all possible devices. - * the initialization of the hardware is done by sci_open - * - * One of devices could be previously registered by console - * initialization therefore we check it everytime - */ - for ( i = 0 ; i < SCI_MINOR_DEVICES ; i++ ) { - /* OK. We assume it is not registered yet. */ - status = rtems_io_register_name( - sci_device[i].name, - major, - sci_device[i].minor - ); - if (status != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred(status); - } - - /* non-default hardware setup occurs in sh_sci_open() */ - return RTEMS_SUCCESSFUL; -} - -/* - * Open entry point - * Sets up port and pins for selected sci. - */ -rtems_device_driver sh_sci_open( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg ) -{ - uint8_t temp8; - uint16_t temp16; - - unsigned a; - - /* check for valid minor number */ - if (( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 )) { - return RTEMS_INVALID_NUMBER; - } - - /* device already opened */ - if ( sci_device[minor].opened > 0 ) { - sci_device[minor].opened++; - return RTEMS_SUCCESSFUL; - } - - /* set PFC registers to enable I/O pins */ - - if ((minor == 0)) { - temp16 = read16(PFC_PACRL2); /* disable SCK0, DMA, IRQ */ - temp16 &= ~(PA2MD1 | PA2MD0); - temp16 |= (PA_TXD0 | PA_RXD0); /* enable pins for Tx0, Rx0 */ - write16(temp16, PFC_PACRL2); - - } else if (minor == 1) { - temp16 = read16(PFC_PACRL2); /* disable SCK1, DMA, IRQ */ - temp16 &= ~(PA5MD1 | PA5MD0); - temp16 |= (PA_TXD1 | PA_RXD1); /* enable pins for Tx1, Rx1 */ - write16(temp16, PFC_PACRL2); - - } /* add other devices and pins as req'd. */ - - /* set up SCI registers */ - write8(0x00, sci_device[minor].addr + SCI_SCR); /* Clear SCR */ - /* set SMR and BRR */ - _sci_set_cflags( &sci_device[minor], sci_device[minor].cflags, sci_device[minor].spd ); - - for (a=0; a < 10000L; a++) { /* Delay */ - __asm__ volatile ("nop"); - } - - write8((SCI_RE | SCI_TE), /* enable async. Tx and Rx */ - sci_device[minor].addr + SCI_SCR); - - /* clear error flags */ - temp8 = read8(sci_device[minor].addr + SCI_SSR); - while (temp8 & (SCI_RDRF | SCI_ORER | SCI_FER | SCI_PER)) { - temp8 = read8(sci_device[minor].addr + SCI_RDR); /* flush input */ - temp8 = read8(sci_device[minor].addr + SCI_SSR); /* clear some flags */ - write8(temp8 & ~(SCI_RDRF | SCI_ORER | SCI_FER | SCI_PER), - sci_device[minor].addr + SCI_SSR); - temp8 = read8(sci_device[minor].addr + SCI_SSR); /* check if everything is OK */ - } - /* Clear RDRF flag */ - write8(0x00, sci_device[minor].addr + SCI_TDR); /* force output */ - /* Clear the TDRE bit */ - temp8 = read8(sci_device[minor].addr + SCI_SSR) & ~SCI_TDRE; - write8(temp8, sci_device[minor].addr + SCI_SSR); - - /* add interrupt setup if required */ - - - sci_device[minor].opened++; - - return RTEMS_SUCCESSFUL; -} - -/* - * Close entry point - */ -rtems_device_driver sh_sci_close( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - /* FIXME: Incomplete */ - if ( sci_device[minor].opened > 0 ) - sci_device[minor].opened--; - else - return RTEMS_INVALID_NUMBER; - - return RTEMS_SUCCESSFUL; -} - -/* - * read bytes from the serial port. We only have stdin. - */ -rtems_device_driver sh_sci_read( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - rtems_libio_rw_args_t *rw_args; - char *buffer; - int maximum; - int count = 0; - - rw_args = (rtems_libio_rw_args_t *) arg; - - buffer = rw_args->buffer; - maximum = rw_args->count; - - for (count = 0; count < maximum; count++) { - buffer[ count ] = inbyte(minor); - if (buffer[ count ] == '\n' || buffer[ count ] == '\r') { - buffer[ count++ ] = '\n'; - break; - } - } - - rw_args->bytes_moved = count; - return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED; -} - -/* - * write bytes to the serial port. Stdout and stderr are the same. - */ -rtems_device_driver sh_sci_write( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - int count; - int maximum; - rtems_libio_rw_args_t *rw_args; - char *buffer; - - rw_args = (rtems_libio_rw_args_t *) arg; - - buffer = rw_args->buffer; - maximum = rw_args->count; - - for (count = 0; count < maximum; count++) { - if ( buffer[ count ] == '\n') { - outbyte(minor, '\r'); - } - outbyte( minor, buffer[ count ] ); - } - - rw_args->bytes_moved = maximum; - return 0; -} - -/* - * IO Control entry point - */ -rtems_device_driver sh_sci_control( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - /* Not yet supported */ - return RTEMS_SUCCESSFUL; -} - -/* - * Termios polled first open - */ -static int _sh_sci_poll_first_open(int major, int minor, void *arg) -{ - return sh_sci_open(major, minor, arg); -} - -/* - * Termios general last close - */ -static int _sh_sci_last_close(int major, int minor, void *arg) -{ - return sh_sci_close(major, minor, arg); -} - -/* - * Termios polled read - */ -static int _sh_sci_poll_read(int minor) -{ - int value = -1; - uint8_t ch = 0; - - if ( minor == 0 ) { - if ( rdSCI0( &ch ) ) - value = (int) ch; - } else if ( minor == 1 ) { - if ( rdSCI1( &ch ) ) - value = (int) ch; - } - return value; -} - -/* - * Termios polled write - */ -static ssize_t _sh_sci_poll_write(int minor, const char *buf, size_t len) -{ - size_t count; - - for (count = 0; count < len; count++) - outbyte( minor, buf[count] ); - return count; -} - -/* - * Termios set attributes - */ -static int _sh_sci_set_attributes( int minor, const struct termios *t) -{ - return _sci_set_cflags( &sci_device[ minor ], t->c_cflag, t->c_ospeed); -} - - -const rtems_termios_callbacks sci_poll_callbacks = { - _sh_sci_poll_first_open, /* FirstOpen*/ - _sh_sci_last_close, /* LastClose*/ - _sh_sci_poll_read, /* PollRead */ - _sh_sci_poll_write, /* Write */ - _sh_sci_set_attributes, /* setAttributes */ - NULL, /* stopRemoteTX */ - NULL, /* StartRemoteTX */ - TERMIOS_POLLED /* outputUsesInterrupts */ -}; - -/* FIXME: not yet supported */ -const rtems_termios_callbacks sci_interrupt_callbacks; - -const rtems_termios_callbacks* sh_sci_get_termios_handlers( bool poll ) -{ - return poll ? - &sci_poll_callbacks : - &sci_interrupt_callbacks; -} diff --git a/bsps/sh/gensh2/console/sci_termios.c b/bsps/sh/gensh2/console/sci_termios.c deleted file mode 100644 index b9f507eb23..0000000000 --- a/bsps/sh/gensh2/console/sci_termios.c +++ /dev/null @@ -1,468 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * Termios console serial driver. - */ - -/* - * Based on SCI driver by Ralf Corsepius and John M. Mills - * - * Author: Radzislaw Galler - * - * COPYRIGHT (c) 1989-2001. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include -#include - -#include -#include - -#include -#include - -#include -#include -#include - -#include -#include -#include - - -/* - * Some handy macros - */ -#define SH_SCI_REG_DATA(_data, _minor, _register) \ - (write8(_data, Console_Port_Tbl[_minor]->ulCtrlPort1 + (_register))) - -#define SH_SCI_REG_FLAG(_flag, _minor, _register) \ - (write8(read8(Console_Port_Tbl[_minor]->ulCtrlPort1 + (_register)) | (_flag), \ - Console_Port_Tbl[_minor]->ulCtrlPort1 + (_register))) - -#define SH_SCI_REG_MASK(_flag, _minor, _register) \ - (write8(read8(Console_Port_Tbl[_minor]->ulCtrlPort1 + (_register)) & ~(_flag),\ - Console_Port_Tbl[_minor]->ulCtrlPort1 + (_register))) - -/* - * NOTE: Some SH variants have 3 sci devices - */ - -#define SCI_MINOR_DEVICES 2 - - -/* - * Automatically generated function imported from scitab.rel - */ -extern int _sci_get_brparms( - speed_t spd, - unsigned char *smr, - unsigned char *brr -); - -/* - * Translate termios flags into SCI settings - */ -int sh_sci_set_attributes( - int minor, - const struct termios *t -) -{ - uint8_t smr; - uint8_t brr; - int a; - - tcflag_t c_cflag = t->c_cflag; - speed_t spd = t->c_ospeed; - - if ( spd ) { - if ( _sci_get_brparms( spd, &smr, &brr ) != 0 ) - return -1 ; - } - - if ( c_cflag & CSIZE ) { - if ( c_cflag & CS8 ) - smr &= ~SCI_SEVEN_BIT_DATA; - else if ( c_cflag & CS7 ) - smr |= SCI_SEVEN_BIT_DATA; - else - return -1 ; - } - - if ( c_cflag & CSTOPB ) - smr |= SCI_STOP_BITS_2; - else - smr &= ~SCI_STOP_BITS_2; - - if ( c_cflag & PARENB ) - smr |= SCI_PARITY_ON ; - else - smr &= ~SCI_PARITY_ON ; - - if ( c_cflag & PARODD ) - smr |= SCI_ODD_PARITY ; - else - smr &= ~SCI_ODD_PARITY; - - SH_SCI_REG_MASK((SCI_RE | SCI_TE), minor, SCI_SCR); - - SH_SCI_REG_DATA(smr, minor, SCI_SMR); - SH_SCI_REG_DATA(brr, minor, SCI_BRR); - - for (a=0; a < 10000L; a++) { /* Delay one bit */ - __asm__ volatile ("nop"); - } - - SH_SCI_REG_FLAG((SCI_RE | SCI_TE), minor, SCI_SCR); - - return 0; -} - -/* - * Receive-data-full ISR - * - * The same routine for all interrupt sources of the same type. - */ -static rtems_isr sh_sci_rx_isr(rtems_vector_number vector) -{ - int minor; - - for (minor = 0; minor < Console_Port_Count; minor++) { - if (Console_Port_Tbl[minor]->ulIntVector == vector) { - char temp8; - - /* - * FIXME: error handling should be added - */ - temp8 = read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_RDR); - - rtems_termios_enqueue_raw_characters( - Console_Port_Data[minor].termios_data, &temp8, 1); - - SH_SCI_REG_MASK(SCI_RDRF, minor, SCI_SSR); - break; - } - } -} - -/* - * Transmit-data-empty ISR - * - * The same routine for all interrupt sources of the same type. - */ -static rtems_isr sh_sci_tx_isr(rtems_vector_number vector) -{ - int minor; - - for (minor = 0; minor < Console_Port_Count; minor++) { - if (Console_Port_Tbl[minor]->ulDataPort == vector) { - /* - * FIXME: Error handling should be added - */ - - /* - * Mask end-of-transmission interrupt - */ - SH_SCI_REG_MASK(SCI_TIE, minor, SCI_SCR); - - if (rtems_termios_dequeue_characters( - Console_Port_Data[minor].termios_data, 1)) { - /* - * More characters to be received - interrupt must be enabled - */ - SH_SCI_REG_FLAG(SCI_TIE, minor, SCI_SCR); - } - break; - } - } -} - - -/* - * Initialization of serial port - */ -void sh_sci_init(int minor) -{ - uint16_t temp16; - - /* - * set PFC registers to enable I/O pins - */ - if ((minor == 0)) { - temp16 = read16(PFC_PACRL2); /* disable SCK0, DMA, IRQ */ - temp16 &= ~(PA2MD1 | PA2MD0); - temp16 |= (PA_TXD0 | PA_RXD0); /* enable pins for Tx0, Rx0 */ - write16(temp16, PFC_PACRL2); - - } else if (minor == 1) { - temp16 = read16(PFC_PACRL2); /* disable SCK1, DMA, IRQ */ - temp16 &= ~(PA5MD1 | PA5MD0); - temp16 |= (PA_TXD1 | PA_RXD1); /* enable pins for Tx1, Rx1 */ - write16(temp16, PFC_PACRL2); - } - - /* - * Non-default hardware setup occurs in sh_sci_first_open - */ -} - -/* - * Initialization of interrupts - * - * Interrupts can be started only after opening a device, so interrupt - * flags are set up in sh_sci_first_open function - */ -void sh_sci_initialize_interrupts(int minor) -{ - rtems_isr_entry old_isr; - rtems_status_code status; - - sh_sci_init(minor); - /* - * Disable IRQ of SCIx - */ - status = sh_set_irq_priority( Console_Port_Tbl[minor]->ulIntVector, 0); - - if (status != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred(status); - - SH_SCI_REG_MASK(SCI_RIE, minor, SCI_SCR); - - /* - * Catch apropriate vectors - */ - status = rtems_interrupt_catch( - sh_sci_rx_isr, - Console_Port_Tbl[minor]->ulIntVector, - &old_isr); - - if (status != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred(status); - - status = rtems_interrupt_catch( - sh_sci_tx_isr, - Console_Port_Tbl[minor]->ulDataPort, - &old_isr); - - if (status != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred(status); - - /* - * Enable IRQ of SCIx - */ - SH_SCI_REG_FLAG(SCI_RIE, minor, SCI_SCR); - - status = sh_set_irq_priority( - Console_Port_Tbl[minor]->ulIntVector, - Console_Port_Tbl[minor]->ulCtrlPort2); - - if (status != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred(status); -} - - -/* - * Open entry point - * Sets up port and pins for selected sci. - */ - -int sh_sci_first_open( - int major, - int minor, - void *arg -) -{ - char temp8; - unsigned int a ; - - /* - * check for valid minor number - */ - if (( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 )) { - return RTEMS_INVALID_NUMBER; - } - - /* - * set up SCI registers - */ - /* Clear SCR - disable Tx and Rx */ - SH_SCI_REG_DATA(0x00, minor, SCI_SCR); - - /* set SMR and BRR - baudrate and format */ - sh_sci_set_attributes(minor, Console_Port_Tbl[minor]->pDeviceParams); - - for (a=0; a < 10000L; a++) { /* Delay */ - __asm__ volatile ("nop"); - } - - write8((SCI_RE | SCI_TE), /* enable async. Tx and Rx */ - Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SCR); - - /* - * clear error flags - */ - temp8 = read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SSR); - while(temp8 & (SCI_RDRF | SCI_ORER | SCI_FER | SCI_PER)) { - /* flush input */ - temp8 = read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_RDR); - - /* clear some flags */ - SH_SCI_REG_FLAG((SCI_RDRF|SCI_ORER|SCI_FER|SCI_PER), minor, SCI_SSR); - - /* check if everything is OK */ - temp8 = read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SSR); - } - - /* Clear RDRF flag */ - SH_SCI_REG_DATA(0x00, minor, SCI_TDR); /* force output */ - - /* Clear the TDRE bit */ - SH_SCI_REG_FLAG(SCI_TDRE, minor, SCI_SSR); - - /* - * Interrupt setup - */ - if (Console_Port_Tbl[minor]->pDeviceFns->deviceOutputUsesInterrupts) { - SH_SCI_REG_FLAG(SCI_RIE, minor, SCI_SCR); - } - - return RTEMS_SUCCESSFUL ; -} - -/* - * Close entry point - */ - -int sh_sci_last_close( - int major, - int minor, - void *arg -) -{ - /* FIXME: Incomplete */ - - /* Shutdown interrupts if necessary */ - if (Console_Port_Tbl[minor]->pDeviceFns->deviceOutputUsesInterrupts) - { - SH_SCI_REG_MASK((SCI_TIE | SCI_RIE), minor, SCI_SCR); - } - return RTEMS_SUCCESSFUL ; -} - -/* - * Interrupt aware write routine - */ -ssize_t sh_sci_write_support_int( - int minor, - const char *buf, - size_t len -) -{ - if (!len) - return 0; - /* - * Put data into TDR and clear transmission-end-flag - */ - SH_SCI_REG_DATA(*buf, minor, SCI_TDR); - SH_SCI_REG_MASK(SCI_TDRE, minor, SCI_SSR); - /* - * Enable interrupt - */ - SH_SCI_REG_FLAG(SCI_TIE, minor, SCI_SCR); - - return 1; -} - -/* - * Polled write method - */ -ssize_t sh_sci_write_support_polled( - int minor, - const char *buf, - size_t len -) -{ - int count = 0; - - while(count < len) { - sh_sci_write_polled(minor, buf[count]); - count++; - } - /* - * Return number of bytes written - */ - return count; -} - -/* - * Polled write of one character at a time - */ -void sh_sci_write_polled( - int minor, - char c -) -{ - /* - * Wait for end of previous character - */ - while(!(read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SSR) & SCI_TDRE)); - /* - * Send the character - */ - SH_SCI_REG_DATA(c, minor, SCI_TDR); - - /* - * Clear TDRE flag - */ - SH_SCI_REG_MASK(SCI_TDRE, minor, SCI_SSR); -} - -/* - * Non-blocking read - */ -int sh_sci_inbyte_nonblocking_polled(int minor) -{ - char inbyte; - - /* - * Check if input buffer is full - */ - if (read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SSR) & SCI_RDRF) { - inbyte = read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_RDR); - SH_SCI_REG_MASK(SCI_RDRF, minor, SCI_SSR); - - /* - * Check for errors - */ - if (read8(Console_Port_Tbl[minor]->ulCtrlPort1 + SCI_SSR) & - (SCI_ORER | SCI_FER | SCI_PER)) { - SH_SCI_REG_MASK((SCI_ORER | SCI_FER | SCI_PER), minor, SCI_SSR); - return -1; - } - return (int)inbyte; - } - return -1; -} diff --git a/bsps/sh/gensh2/console/scitab.c b/bsps/sh/gensh2/console/scitab.c deleted file mode 100644 index 7c8e699246..0000000000 --- a/bsps/sh/gensh2/console/scitab.c +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * Copyright (c) 2018 embedded brains GmbH & Co. KG - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * The content of this file was previously generated by the GPL licensed shgen - * tool during the BSP build for a configured clock frequency - * (CPU_CLOCK_RATE_HZ). All tools were removed from the RTEMS source repository - * at some point in time. Tools with a BSD-style license were moved to the - * RTEMS tools repository. - */ - -#include - -int _sci_get_brparms( - unsigned int spd, - unsigned char *smr, - unsigned char *brr -) -{ - if (spd != 9600) { - return -1; - } - - *smr = 0x00; - *brr = 0x5f; - return 0; -} diff --git a/bsps/sh/gensh2/include/bsp.h b/bsps/sh/gensh2/include/bsp.h deleted file mode 100644 index 082ea8169a..0000000000 --- a/bsps/sh/gensh2/include/bsp.h +++ /dev/null @@ -1,100 +0,0 @@ -/** - * @file - * - * @ingroup RTEMSBSPsSH2 - * - * @brief Global BSP definitions. - */ - -/* - * generic sh2 - * - * This include file contains all board IO definitions. - */ - -/* - * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Minor adaptations for sh2 by: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - */ - -#ifndef LIBBSP_SH_GENSH2_BSP_H -#define LIBBSP_SH_GENSH2_BSP_H - -/** - * @defgroup RTEMSBSPsSH2 SH-2 - * - * @ingroup RTEMSBSPsSH - * - * @brief SH-2 Board Support Package. - * - * @{ - */ - -#include - -#include -#include - -#include /* for tcflag_t */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if 1 -/* FIXME: - * These definitions will be no longer necessary if the old - * implementation of SCI driver will be droped - */ -#define BSP_CONSOLE_DEVNAME "/dev/sci0" -#define BSP_CONSOLE_MINOR_NUMBER ((rtems_device_minor_number) 0) -#define BSP_CONSOLE_DRIVER_TABLE_ENTRY DEVSCI_DRIVER_TABLE_ENTRY -#define BSP_CONSOLE_DEVICE_TERMIOS_HANDLERS (sh_sci_get_termios_handlers(TRUE)) -#endif - -/* Constants */ - -/* - * BSP methods that cross file boundaries. - */ -void bsp_hw_init(void); - -int _sci_get_brparms( - unsigned int spd, - unsigned char *smr, - unsigned char *brr -); - -#ifdef __cplusplus -} -#endif - -/** @} */ - -#endif diff --git a/bsps/sh/gensh2/include/bsp/irq.h b/bsps/sh/gensh2/include/bsp/irq.h deleted file mode 100644 index 8a97d7a1b0..0000000000 --- a/bsps/sh/gensh2/include/bsp/irq.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/bsps/sh/gensh2/include/rtems/score/iosh7045.h b/bsps/sh/gensh2/include/rtems/score/iosh7045.h deleted file mode 100644 index db3252b72d..0000000000 --- a/bsps/sh/gensh2/include/rtems/score/iosh7045.h +++ /dev/null @@ -1,322 +0,0 @@ -/* - * This include file contains information pertaining to the Hitachi SH - * processor. - * - * NOTE: NOT ALL VALUES HAVE BEEN CHECKED !! - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which - * contained no copyright notice. - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modified to reflect on-chip registers for sh7045 processor, based on - * "Register.h" distributed with Hitachi's EVB7045F tutorials, and which - * contained no copyright notice: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * August, 1999 - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - */ - -#ifndef __IOSH7045_H -#define __IOSH7045_H - -/* - * After each line is explained whether the access is char short or long. - * The functions read/writeb, w, l, 8, 16, 32 can be found - * in exec/score/cpu/sh/sh_io.h - * - * 8 bit == char ( readb, writeb, read8, write8) - * 16 bit == short ( readw, writew, read16, write16 ) - * 32 bit == long ( readl, writel, read32, write32 ) - * JMM: Addresses noted "[char, ]short,word" are per Hitachi _SuperH_RISC_ - * ENGINE_..Hardware_Manual; alignment access-restrictions may apply - */ - -#define REG_BASE 0xFFFF8000 - -/* SCI0 Registers */ -#define SCI_SMR0 (REG_BASE + 0x01a0) /*char: Serial mode ch 0 */ -#define SCI_BRR0 (REG_BASE + 0x01a1) /*char: Bit rate ch 0 */ -#define SCI_SCR0 (REG_BASE + 0x01a2) /*char: Serial control ch 0 */ -#define SCI_TDR0 (REG_BASE + 0x01a3) /*char: Transmit data ch 0 */ -#define SCI_SSR0 (REG_BASE + 0x01a4) /*char: Serial status ch 0 */ -#define SCI_RDR0 (REG_BASE + 0x01a5) /*char: Receive data ch 0 */ - -#define SCI0_SMR SCI_SMR0 - -/* SCI1 Registers */ -#define SCI_SMR1 (REG_BASE + 0x01b0) /* char: Serial mode ch 1 */ -#define SCI_BRR1 (REG_BASE + 0x01b1) /* char: Bit rate ch 1 */ -#define SCI_SCR1 (REG_BASE + 0x01b2) /* char: Serial control ch 1 */ -#define SCI_TDR1 (REG_BASE + 0x01b3) /* char: Transmit data ch 1 */ -#define SCI_SSR1 (REG_BASE + 0x01b4) /* char: Serial status ch 1 */ -#define SCI_RDR1 (REG_BASE + 0x01b5) /* char: Receive data ch 1 */ - -#define SCI1_SMR SCI_SMR1 - -/* ADI */ -/* High Speed A/D (Excluding A-Mask Part)*/ -#define ADDRA (REG_BASE + 0x03F0) /* short */ -#define ADDRB (REG_BASE + 0x03F2) /* short */ -#define ADDRC (REG_BASE + 0x03F4) /* short */ -#define ADDRD (REG_BASE + 0x03F6) /* short */ -#define ADDRE (REG_BASE + 0x03F8) /* short */ -#define ADDRF (REG_BASE + 0x03FA) /* short */ -#define ADDRG (REG_BASE + 0x03FC) /* short */ -#define ADDRH (REG_BASE + 0x03FE) /* short */ -#define ADCSR (REG_BASE + 0x03E0) /* char */ -#define ADCR (REG_BASE + 0x03E1) /* char */ - -/* Mid-Speed A/D (A-Mask part)*/ -#define ADDRA0 (REG_BASE + 0x0400) /* char, short */ -#define ADDRA0H (REG_BASE + 0x0400) /* char, short */ -#define ADDRA0L (REG_BASE + 0x0401) /* char */ -#define ADDRB0 (REG_BASE + 0x0402) /* char, short */ -#define ADDRB0H (REG_BASE + 0x0402) /* char, short */ -#define ADDRB0L (REG_BASE + 0x0403) /* char */ -#define ADDRC0 (REG_BASE + 0x0404) /* char, short */ -#define ADDRC0H (REG_BASE + 0x0404) /* char, short */ -#define ADDRC0L (REG_BASE + 0x0405) /* char */ -#define ADDRD0 (REG_BASE + 0x0406) /* char, short */ -#define ADDRD0H (REG_BASE + 0x0406) /* char, short */ -#define ADDRD0L (REG_BASE + 0x0407) /* char */ -#define ADCSR0 (REG_BASE + 0x0410) /* char */ -#define ADCR0 (REG_BASE + 0x0412) /* char */ -#define ADDRA1 (REG_BASE + 0x0408) /* char, short */ -#define ADDRA1H (REG_BASE + 0x0408) /* char, short */ -#define ADDRA1L (REG_BASE + 0x0409) /* char */ -#define ADDRB1 (REG_BASE + 0x040A) /* char, short */ -#define ADDRB1H (REG_BASE + 0x040A) /* char, short */ -#define ADDRB1L (REG_BASE + 0x040B) /* char */ -#define ADDRC1 (REG_BASE + 0x040C) /* char, short */ -#define ADDRC1H (REG_BASE + 0x040C) /* char, short */ -#define ADDRC1L (REG_BASE + 0x040D) /* char */ -#define ADDRD1 (REG_BASE + 0x040E) /* char, short */ -#define ADDRD1H (REG_BASE + 0x040E) /* char, short */ -#define ADDRD1L (REG_BASE + 0x040F) /* char */ -#define ADCSR1 (REG_BASE + 0x0411) /* char */ -#define ADCR1 (REG_BASE + 0x0413) /* char */ - -/*MTU SHARED*/ -#define MTU_TSTR (REG_BASE + 0x0240) /* char, short, word */ -#define MTU_TSYR (REG_BASE + 0x0241) /* char, short, word */ -#define MTU_ICSR (REG_BASE + 0x03C0) /* input lev. CSR */ -#define MTU_OCSR (REG_BASE + 0x03C0) /* output lev. CSR */ - -/*MTU CHANNEL 0*/ -#define MTU_TCR0 (REG_BASE + 0x0260) /* char, short, word */ -#define MTU_TMDR0 (REG_BASE + 0x0261) /* char, short, word */ -#define MTU_TIORH0 (REG_BASE + 0x0262) /* char, short, word */ -#define MTU_TIORL0 (REG_BASE + 0x0263) /* char, short, word */ -#define MTU_TIER0 (REG_BASE + 0x0264) /* char, short, word */ -#define MTU_TSR0 (REG_BASE + 0x0265) /* char, short, word */ -#define MTU_TCNT0 (REG_BASE + 0x0266) /* short, word */ -#define MTU_GR0A (REG_BASE + 0x0268) /* short, word */ -#define MTU_GR0B (REG_BASE + 0x026A) /* short, word */ -#define MTU_GR0C (REG_BASE + 0x026C) /* short, word */ -#define MTU_GR0D (REG_BASE + 0x026E) /* short, word */ - -/*MTU CHANNEL 1*/ -#define MTU_TCR1 (REG_BASE + 0x0280) /* char, short, word */ -#define MTU_TMDR1 (REG_BASE + 0x0281) /* char, short, word */ -#define MTU_TIOR1 (REG_BASE + 0x0282) /* char, short, word */ -#define MTU_TIER1 (REG_BASE + 0x0284) /* char, short, word */ -#define MTU_TSR1 (REG_BASE + 0x0285) /* char, short, word */ -#define MTU_TCNT1 (REG_BASE + 0x0286) /* short, word */ -#define MTU_GR1A (REG_BASE + 0x0288) /* short, word */ -#define MTU_GR1B (REG_BASE + 0x028A) /* short, word */ - -/*MTU CHANNEL 2*/ -#define MTU_TCR2 (REG_BASE + 0x02A0) /* char, short, word */ -#define MTU_TMDR2 (REG_BASE + 0x02A1) /* char, short, word */ -#define MTU_TIOR2 (REG_BASE + 0x02A2) /* char, short, word */ -#define MTU_TIER2 (REG_BASE + 0x02A4) /* char, short, word */ -#define MTU_TSR2 (REG_BASE + 0x02A5) /* char, short, word */ -#define MTU_TCNT2 (REG_BASE + 0x02A6) /* short, word */ -#define MTU_GR2A (REG_BASE + 0x02A8) /* short, word */ -#define MTU_GR2B (REG_BASE + 0x02AA) /* short, word */ - -/*MTU CHANNELS 3-4 SHARED*/ -#define MTU_TOER (REG_BASE + 0x020A) /* char, short, word */ -#define MTU_TOCR (REG_BASE + 0x020B) /* char, short, word */ -#define MTU_TGCR (REG_BASE + 0x020D) /* char, short, word */ -#define MTU_TCDR (REG_BASE + 0x0214) /* short, word */ -#define MTU_TDDR (REG_BASE + 0x0216) /* short, word */ -#define MTU_TCNTS (REG_BASE + 0x0220) /* short, word */ -#define MTU_TCBR (REG_BASE + 0x0222) /* short, word */ - -/*MTU CHANNEL 3*/ -#define MTU_TCR3 (REG_BASE + 0x0200) /* char, short, word */ -#define MTU_TMDR3 (REG_BASE + 0x0202) /* char, short, word */ -#define MTU_TIORH3 (REG_BASE + 0x0204) /* char, short, word */ -#define MTU_TIORL3 (REG_BASE + 0x0205) /* char, short, word */ -#define MTU_TIER3 (REG_BASE + 0x0208) /* char, short, word */ -#define MTU_TSR3 (REG_BASE + 0x022C) /* char, short, word */ -#define MTU_TCNT3 (REG_BASE + 0x0210) /* short, word */ -#define MTU_GR3A (REG_BASE + 0x0218) /* short, word */ -#define MTU_GR3B (REG_BASE + 0x021A) /* short, word */ -#define MTU_GR3C (REG_BASE + 0x0224) /* short, word */ -#define MTU_GR3D (REG_BASE + 0x0226) /* short, word */ - -/*MTU CHANNEL 4*/ -#define MTU_TCR4 (REG_BASE + 0x0201) /* char, short, word */ -#define MTU_TMDR4 (REG_BASE + 0x0203) /* char, short, word */ -#define MTU_TIOR4 (REG_BASE + 0x0206) /* char, short, word */ -#define MTU_TIORH4 (REG_BASE + 0x0206) /* char, short, word */ -#define MTU_TIORL4 (REG_BASE + 0x0207) /* char, short, word */ -#define MTU_TIER4 (REG_BASE + 0x0209) /* char, short, word */ -#define MTU_TSR4 (REG_BASE + 0x022D) /* char, short, word */ -#define MTU_TCNT4 (REG_BASE + 0x0212) /* short, word */ -#define MTU_GR4A (REG_BASE + 0x021C) /* short, word */ -#define MTU_GR4B (REG_BASE + 0x021E) /* short, word */ -#define MTU_GR4C (REG_BASE + 0x0228) /* short, word */ -#define MTU_GR4D (REG_BASE + 0x022A) /* short, word */ - -/*DMAC CHANNELS 0-3 SHARED*/ -#define DMAOR (REG_BASE + 0x06B0) /* short */ - -/*DMAC CHANNEL 0*/ -#define DMA_SAR0 (REG_BASE + 0x06C0) /* short, word */ -#define DMA_DAR0 (REG_BASE + 0x06C4) /* short, word */ -#define DMA_DMATCR0 (REG_BASE + 0x06C8) /* short, word */ -#define DMA_CHCR0 (REG_BASE + 0x06CC) /* short, word */ - -/*DMAC CHANNEL 1*/ -#define DMA_SAR1 (REG_BASE + 0x06D0) /* short, word */ -#define DMA_DAR1 (REG_BASE + 0x06D4) /* short, word */ -#define DMA_DMATCR1 (REG_BASE + 0x06D8) /* short, wordt */ -#define DMA_CHCR1 (REG_BASE + 0x06DC) /* short, word */ - -/*DMAC CHANNEL 3*/ -#define DMA_SAR3 (REG_BASE + 0x06E0) /* short, word */ -#define DMA_DAR3 (REG_BASE + 0x06E4) /* short, word */ -#define DMA_DMATCR3 (REG_BASE + 0x06E8) /* short, word */ -#define DMA_CHCR3 (REG_BASE + 0x06EC) /* short, word */ - -/*DMAC CHANNEL 4*/ -#define DMA_SAR4 (REG_BASE + 0x06F0) /* short, word */ -#define DMA_DAR4 (REG_BASE + 0x06F4) /* short, word */ -#define DMA_DMATCR4 (REG_BASE + 0x06F8) /* short, word */ -#define DMA_CHCR4 (REG_BASE + 0x06FC) /* short, word */ - -/*Data Transfer Controller*/ -#define DTC_DTEA (REG_BASE + 0x0700) /* char, short, word */ -#define DTC_DTEB (REG_BASE + 0x0701) /* char, short(?), word(?) */ -#define DTC_DTEC (REG_BASE + 0x0702) /* char, short(?), word(?) */ -#define DTC_DTED (REG_BASE + 0x0703) /* char, short(?), word(?) */ -#define DTC_DTEE (REG_BASE + 0x0704) /* char, short(?), word(?) */ -#define DTC_DTCSR (REG_BASE + 0x0706) /* char, short, word */ -#define DTC_DTBR (REG_BASE + 0x0708) /* short, word */ - -/*Cache Memory*/ -#define CAC_CCR (REG_BASE + 0x0740) /* char, short, word */ - -/*INTC*/ -#define INTC_IPRA (REG_BASE + 0x0348) /* char, short, word */ -#define INTC_IPRB (REG_BASE + 0x034A) /* char, short, word */ -#define INTC_IPRC (REG_BASE + 0x034C) /* char, short, word */ -#define INTC_IPRD (REG_BASE + 0x034E) /* char, short, word */ -#define INTC_IPRE (REG_BASE + 0x0350) /* char, short, word */ -#define INTC_IPRF (REG_BASE + 0x0352) /* char, short, word */ -#define INTC_IPRG (REG_BASE + 0x0354) /* char, short, word */ -#define INTC_IPRH (REG_BASE + 0x0356) /* char, short, word */ -#define INTC_ICR (REG_BASE + 0x0358) /* char, short, word */ -#define INTC_ISR (REG_BASE + 0x035A) /* char, short, word */ - -/*Flash (F-ZTAT)*/ -#define FL_FLMCR1 (REG_BASE + 0x0580) /* Fl.Mem.Contr.Reg 1: char */ -#define FL_FLMCR2 (REG_BASE + 0x0581) /* Fl.Mem.Contr.Reg 2: char */ -#define FL_EBR1 (REG_BASE + 0x0582) /* Fl.Mem.Erase Blk.1: char */ -#define FL_EBR2 (REG_BASE + 0x0584) /* Fl.Mem.Erase Blk.2: char */ -#define FL_RAMER (REG_BASE + 0x0628) /* Ram Emul.Reg.- char,short,word */ - -/*UBC*/ -#define UBC_BARH (REG_BASE + 0x0600) /* char, short, word */ -#define UBC_BARL (REG_BASE + 0x0602) /* char, short, word */ -#define UBC_BAMRH (REG_BASE + 0x0604) /* char, short, word */ -#define UBC_BAMRL (REG_BASE + 0x0606) /* char, short, word */ -#define UBC_BBR (REG_BASE + 0x0608) /* char, short, word */ -/*BSC*/ -#define BSC_BCR1 (REG_BASE + 0x0620) /* short */ -#define BSC_BCR2 (REG_BASE + 0x0622) /* short */ -#define BSC_WCR1 (REG_BASE + 0x0624) /* short */ -#define BSC_WCR2 (REG_BASE + 0x0626) /* short */ -#define BSC_DCR (REG_BASE + 0x062A) /* short */ -#define BSC_RTCSR (REG_BASE + 0x062C) /* short */ -#define BSC_RTCNT (REG_BASE + 0x062E) /* short */ -#define BSC_RTCOR (REG_BASE + 0x0630) /* short */ - -/*WDT*/ -#define WDT_R_TCSR (REG_BASE + 0x0610) /* rd: char */ -#define WDT_R_TCNT (REG_BASE + 0x0611) /* rd: char */ -#define WDT_R_RSTCSR (REG_BASE + 0x0613) /* rd: char */ -#define WDT_W_TCSR (REG_BASE + 0x0610) /* wrt: short */ -#define WDT_W_TCNT (REG_BASE + 0x0610) /* wrt: short */ -#define WDT_W_RSTCSR (REG_BASE + 0x0612) /* wrt: short */ - -/*POWER DOWN STATE*/ -#define PDT_SBYCR (REG_BASE + 0x0614) /* char */ - -/* Port I/O Control Registers */ -#define IO_PADRH (REG_BASE + 0x0380) /* Port A Data Register */ -#define IO_PADRL (REG_BASE + 0x0382) /* Port A Data Register */ -#define IO_PBDR (REG_BASE + 0x0390) /* Port B Data Register */ -#define IO_PCDR (REG_BASE + 0x0392) /* Port C Data Register */ -#define IO_PDDRH (REG_BASE + 0x03A0) /* Port D Data Register */ -#define IO_PDDRL (REG_BASE + 0x03A2) /* Port D Data Register */ -#define IO_PEDR (REG_BASE + 0x03B0) /* Port E Data Register */ -#define IO_PFDR (REG_BASE + 0x03B2) /* Port F Data Register */ - -/*Pin Function Control Register*/ -#define PFC_PAIORH (REG_BASE + 0x0384) /* Port A I/O Reg. H */ -#define PFC_PAIORL (REG_BASE + 0x0386) /* Port A I/O Reg. L */ -#define PFC_PACRH (REG_BASE + 0x0388) /* Port A Ctr. Reg. H */ -#define PFC_PACRL1 (REG_BASE + 0x038C) /* Port A Ctr. Reg. L1 */ -#define PFC_PACRL2 (REG_BASE + 0x038E) /* Port A Ctr. Reg. L2 */ -#define PFC_PBIOR (REG_BASE + 0x0394) /* Port B I/O Register */ -#define PFC_PBCR1 (REG_BASE + 0x0398) /* Port B Ctr. Reg. R1 */ -#define PFC_PBCR2 (REG_BASE + 0x039A) /* Port B Ctr. Reg. R2 */ -#define PFC_PCIOR (REG_BASE + 0x0396) /* Port C I/O Register */ -#define PFC_PCCR (REG_BASE + 0x039C) /* Port C Ctr. Reg. */ -#define PFC_PDIORH (REG_BASE + 0x03A4) /* Port D I/O Reg. H */ -#define PFC_PDIORL (REG_BASE + 0x03A6) /* Port D I/O Reg. L */ -#define PFC_PDCRH1 (REG_BASE + 0x03A8) /* Port D Ctr. Reg. H1 */ -#define PFC_PDCRH2 (REG_BASE + 0x03AA) /* Port D Ctr. Reg. H2 */ -#define PFC_PDCRL (REG_BASE + 0x03AC) /* Port D Ctr. Reg. L */ -#define PFC_PEIOR (REG_BASE + 0x03B4) /* Port E I/O Register */ -#define PFC_PECR1 (REG_BASE + 0x03B8) /* Port E Ctr. Reg. 1 */ -#define PFC_PECR2 (REG_BASE + 0x03BA) /* Port E Ctr. Reg. 2 */ -#define PFC_IFCR (REG_BASE + 0x03C8) /* short */ - -/*Compare/Match Timer*/ -#define CMT_CMSTR (REG_BASE + 0x3D0) /* Start Reg. char, short, word */ -#define CMT_CMCSR0 (REG_BASE + 0x3D2) /* C0 SCR short, word */ -#define CMT_CMCNT0 (REG_BASE + 0x3D4) /* C0 Counter char, short, word */ -#define CMT_CMCOR0 (REG_BASE + 0x3D6) /* C0 Const.Reg. char, short, word */ -#define CMT_CMCSR1 (REG_BASE + 0x3D8) /* C1 SCR short, word */ -#define CMT_CMCNT1 (REG_BASE + 0x3DA) /* C1 Counter char, short, word */ -#define CMT_CMCOR1 (REG_BASE + 0x3DC) /* C1 Const.Reg. char, short, word */ - -#endif diff --git a/bsps/sh/gensh2/include/rtems/score/ispsh7045.h b/bsps/sh/gensh2/include/rtems/score/ispsh7045.h deleted file mode 100644 index e4f74de5fd..0000000000 --- a/bsps/sh/gensh2/include/rtems/score/ispsh7045.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * This include file contains information pertaining to the Hitachi SH - * processor. - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modified to reflect isp entries for sh7045 processor: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - */ - -#ifndef __CPU_ISPS_H -#define __CPU_ISPS_H - -#ifdef __cplusplus -extern "C" { -#endif - -extern void __ISR_Handler( uint32_t vector ); - - -/* - * interrupt vector table offsets - */ -#define NMI_ISP_V 11 -#define USB_ISP_V 12 -#define IRQ0_ISP_V 64 -#define IRQ1_ISP_V 65 -#define IRQ2_ISP_V 66 -#define IRQ3_ISP_V 67 -#define IRQ4_ISP_V 68 -#define IRQ5_ISP_V 69 -#define IRQ6_ISP_V 70 -#define IRQ7_ISP_V 71 -#define DMA0_ISP_V 72 -#define DMA1_ISP_V 76 -#define DMA2_ISP_V 80 -#define DMA3_ISP_V 84 - -#define MTUA0_ISP_V 88 -#define MTUB0_ISP_V 89 -#define MTUC0_ISP_V 90 -#define MTUD0_ISP_V 91 -#define MTUV0_ISP_V 92 - -#define MTUA1_ISP_V 96 -#define MTUB1_ISP_V 97 -#define MTUV1_ISP_V 100 -#define MTUU1_ISP_V 101 - -#define MTUA2_ISP_V 104 -#define MTUB2_ISP_V 105 -#define MTUV2_ISP_V 108 -#define MTUU2_ISP_V 109 - -#define MTUA3_ISP_V 112 -#define MTUB3_ISP_V 113 -#define MTUC3_ISP_V 114 -#define MTUD3_ISP_V 115 -#define MTUV3_ISP_V 116 - -#define MTUA4_ISP_V 120 -#define MTUB4_ISP_V 121 -#define MTUC4_ISP_V 122 -#define MTUD4_ISP_V 123 -#define MTUV4_ISP_V 124 - -#define ERI0_ISP_V 128 -#define RXI0_ISP_V 129 -#define TXI0_ISP_V 130 -#define TEI0_ISP_V 131 - -#define ERI1_ISP_V 132 -#define RXI1_ISP_V 133 -#define TXI1_ISP_V 134 -#define TEI1_ISP_V 135 - -#define ADI0_ISP_V 136 -#define ADI1_ISP_V 137 -#define DTC_ISP_V 140 /* Data Transfer Controller */ -#define CMT0_ISP_V 144 /* Compare Match Timer */ -#define CMT1_ISP_V 148 -#define WDT_ISP_V 152 /* Wtachdog Timer */ -#define CMI_ISP_V 153 /* BSC RAS interrupt */ -#define OEI_ISP_V 156 /* I/O Port */ -#define DREF_ISP_V CMI_ISP_V /* DRAM Refresh from BSC */ -#if 0 -#define PRT_ISP_V /* parity error - no equivalent */ -#endif - -/* dummy ISP */ -extern void _dummy_isp( void ); - -/* Non Maskable Interrupt */ -extern void _nmi_isp( void ); - -/* User Break Controller */ -extern void _usb_isp( void ); - -/* External interrupts 0-7 */ -extern void _irq0_isp( void ); -extern void _irq1_isp( void ); -extern void _irq2_isp( void ); -extern void _irq3_isp( void ); -extern void _irq4_isp( void ); -extern void _irq5_isp( void ); -extern void _irq6_isp( void ); -extern void _irq7_isp( void ); - -/* DMA - Controller */ -extern void _dma0_isp( void ); -extern void _dma1_isp( void ); -extern void _dma2_isp( void ); -extern void _dma3_isp( void ); - -/* Interrupt Timer Unit */ -/* Timer 0 */ -extern void _mtua0_isp( void ); -extern void _mtub0_isp( void ); -extern void _mtuc0_isp( void ); -extern void _mtud0_isp( void ); -extern void _mtuv0_isp( void ); -/* Timer 1 */ -extern void _mtua1_isp( void ); -extern void _mtub1_isp( void ); -extern void _mtuv1_isp( void ); -extern void _mtuu1_isp( void ); -/* Timer 2 */ -extern void _mtua2_isp( void ); -extern void _mtub2_isp( void ); -extern void _mtuv2_isp( void ); -extern void _mtuu2_isp( void ); -/* Timer 3 */ -extern void _mtua3_isp( void ); -extern void _mtub3_isp( void ); -extern void _mtuc3_isp( void ); -extern void _mtud3_isp( void ); -extern void _mtuv3_isp( void ); -/* Timer 4 */ -extern void _mtua4_isp( void ); -extern void _mtub4_isp( void ); -extern void _mtuc4_isp( void ); -extern void _mtud4_isp( void ); -extern void _mtuv4_isp( void ); - -/* serial interfaces */ -extern void _eri0_isp( void ); -extern void _rxi0_isp( void ); -extern void _txi0_isp( void ); -extern void _tei0_isp( void ); -extern void _eri1_isp( void ); -extern void _rxi1_isp( void ); -extern void _txi1_isp( void ); -extern void _tei1_isp( void ); - -/* ADC */ -extern void _adi0_isp( void ); -extern void _adi1_isp( void ); - -/* Data Transfer Controller */ -extern void _dtci_isp( void ); - -/* Compare Match Timer */ -extern void _cmt0_isp( void ); -extern void _cmt1_isp( void ); - -/* Watchdog Timer */ -extern void _wdt_isp( void ); - -/* DRAM refresh control unit of bus state controller */ -extern void _bsc_isp( void ); - -/* I/O Port */ -extern void _oei_isp( void ); - -/* Parity Control Unit of the Bus State Controllers */ -/* extern void _prt_isp( void ); */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsps/sh/gensh2/include/sh/io_types.h b/bsps/sh/gensh2/include/sh/io_types.h deleted file mode 100644 index 1dab885672..0000000000 --- a/bsps/sh/gensh2/include/sh/io_types.h +++ /dev/null @@ -1,84 +0,0 @@ -/************************************************************************ - * - * Data types and constants for Hitachi SH704X on-chip peripherals - * - * Author: John M.Mills (jmills@tga.com) - * - * COPYRIGHT (c) 1999, TGA Technologies, Norcross, GA, USA - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * This file may be distributed as part of the RTEMS software item. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - * - * - ************************************************************************/ - -#ifndef _sh_io_types_h -#define _sh_io_types_h - -#include -#include - -typedef enum {SCI0, SCI1} portNo; -typedef enum {eight, seven} dataBits; -typedef enum {one, two} stopBits; -typedef enum {even, odd} parity; - -typedef struct { - portNo line; - int speed_ix; - dataBits dBits; - int parEn; - parity par; - int mulPro; - stopBits sBits; -} sci_setup_t; - -typedef union{ - unsigned char Reg; /* By Register */ - struct { /* By Field */ - unsigned char Sync :1; /* Async/Sync */ - unsigned char DBts :1; /* Char.Length */ - unsigned char ParEn :1; /* Parity En.*/ - unsigned char Odd :1; /* Even/Odd */ - unsigned char SBts :1; /* No.Stop Bits */ - unsigned char MulP :1; /* Multi-Proc. */ - unsigned char Dvsr :2; /* Clock Sel. */ - } Fld; -} sci_smr_t; - -typedef union { - unsigned char Reg; /* By Register */ - struct { /* By Field */ - unsigned char TIE :1; /* Tx.Int.En. */ - unsigned char RIE :1; /* Rx.Int.En. */ - unsigned char TE :1; /* Tx.En. */ - unsigned char RE :1; /* Rx.En. */ - unsigned char MPIE:1; /* Mult.Pro.Int.En. */ - unsigned char TEIE:1; /* Tx.End Int.En. */ - unsigned char CkSrc :2; /* Clock Src. */ - } Fld; -} sci_scr_t; - -typedef struct { - unsigned char n ; - unsigned char N ; -} sci_bitrate_t; - -#endif /* _sh_io_types_h */ diff --git a/bsps/sh/gensh2/include/sh/sci.h b/bsps/sh/gensh2/include/sh/sci.h deleted file mode 100644 index dc34371d48..0000000000 --- a/bsps/sh/gensh2/include/sh/sci.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Driver for the sh2 704x on-chip serial devices (sci) - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _sh_sci_h -#define _sh_sci_h - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Devices are set to 9600 bps, 8 databits, 1 stopbit, no - * parity and asynchronous mode by default. - * - * NOTE: - * The onboard serial devices of the SH do not support hardware - * handshake. - */ - -#define DEVSCI_DRIVER_TABLE_ENTRY \ - { sh_sci_initialize, sh_sci_open, sh_sci_close, sh_sci_read, \ - sh_sci_write, sh_sci_control } - -extern rtems_device_driver sh_sci_initialize( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -extern rtems_device_driver sh_sci_open( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -extern rtems_device_driver sh_sci_close( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -extern rtems_device_driver sh_sci_read( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -extern rtems_device_driver sh_sci_write( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -extern rtems_device_driver sh_sci_control( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -extern const rtems_termios_callbacks * sh_sci_get_termios_handlers( - bool poll -); - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsps/sh/gensh2/include/sh/sci_termios.h b/bsps/sh/gensh2/include/sh/sci_termios.h deleted file mode 100644 index 8b5f3974f3..0000000000 --- a/bsps/sh/gensh2/include/sh/sci_termios.h +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * COPYRIGHT (c) 1989-2001. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _SH_SCI_TERMIOS_H_ -#define _SH_SCI_TERMIOS_H_ - -#ifdef __cplusplus -extern "C"{ -#endif - - -int sh_sci_set_attributes( - int minor, - const struct termios *t -); - -void sh_sci_initialize_interrupts(int minor); - -void sh_sci_init(int minor); - -ssize_t sh_sci_write_support_int( - int minor, - const char *buf, - size_t len -); - -ssize_t sh_sci_write_support_polled( - int minor, - const char *buf, - size_t len -); - -void sh_sci_write_polled( - int minor, - char c -); - -int sh_sci_inbyte_nonblocking_polled(int minor); - - -int sh_sci_first_open( - int major, - int minor, - void *arg -); - -int sh_sci_last_close( - int major, - int minor, - void *arg -); - -#ifdef __cplusplus -} -#endif - - -#endif /* _SH_SCI_TERMIOS_H_ */ diff --git a/bsps/sh/gensh2/include/sh/sh7_pfc.h b/bsps/sh/gensh2/include/sh/sh7_pfc.h deleted file mode 100644 index b56433a9e2..0000000000 --- a/bsps/sh/gensh2/include/sh/sh7_pfc.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Bit values for the pin function controller of the Hitachi SH704x - * - * From Hitachi tutorials - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _sh7_pfc_h -#define _sh7_pfc_h - -#include - -/* - * Port A IO Registers (PAIORH, PAIORL) - * 1 => OUTPUT - * 0 => INPUT - */ -#define PAIORH PFC_PAIORH -#define PAIORL PFC_PAIORL - -/* PAIORH */ -#define PA23IOR 0x0080 -#define PA22IOR 0x0040 -#define PA21IOR 0x0020 -#define PA20IOR 0x0010 -#define PA19IOR 0x0008 -#define PA18IOR 0x0004 -#define PA17IOR 0x0002 -#define PA16IOR 0x0001 - -/* PAIORL */ -#define PA15IOR 0x8000 -#define PA14IOR 0x4000 -#define PA13IOR 0x2000 -#define PA12IOR 0x1000 -#define PA11IOR 0x0800 -#define PA10IOR 0x0400 -#define PA9IOR 0x0200 -#define PA8IOR 0x0100 -#define PA7IOR 0x0080 -#define PA6IOR 0x0040 -#define PA5IOR 0x0020 -#define PA4IOR 0x0010 -#define PA3IOR 0x0008 -#define PA2IOR 0x0004 -#define PA1IOR 0x0002 -#define PA0IOR 0x0001 - -/* - * Port A Control Registers (PACRH, PACRL1, PACRL2) - * and mode bits - */ -#define PACRH PFC_PACRH -#define PACRL1 PFC_PACRL1 -#define PACRL2 PFC_PACRL2 - -/* PACRH */ -#define PA23MD0 0x4000 -#define PA22MD0 0x1000 -#define PA21MD0 0x0400 -#define PA20MD0 0x0100 -#define PA19MD1 0x0080 -#define PA19MD0 0x0040 -#define PA18MD1 0x0020 -#define PA18MD0 0x0010 -#define PA17MD0 0x0004 -#define PA16MD0 0x0001 - -/* PACRL1 */ -#define PA15MD0 0x4000 -#define PA14MD0 0x1000 -#define PA13MD0 0x0400 -#define PA12MD0 0x0100 -#define PA11MD0 0x0040 -#define PA10MD0 0x0010 -#define PA9MD1 0x0008 -#define PA9MD0 0x0004 -#define PA8MD1 0x0002 -#define PA8MD0 0x0001 - -/* PACRL2 */ -#define PA7MD1 0x8000 -#define PA7MD0 0x4000 -#define PA6MD1 0x2000 -#define PA6MD0 0x1000 -#define PA5MD1 0x0800 -#define PA5MD0 0x0400 -#define PA4MD0 0x0100 -#define PA3MD0 0x0040 -#define PA2MD1 0x0020 -#define PA2MD0 0x0010 -#define PA1MD0 0x0004 -#define PA0MD0 0x0001 - -#define PA_TXD1 PA4MD0 -#define PA_RXD1 PA3MD0 -#define PA_TXD0 PA1MD0 -#define PA_RXD0 PA0MD0 - -/* - * Port B IO Register (PBIOR) - */ -#define PBIOR PFC_PBIOR -#define PB15IOR 0x8000 -#define PB14IOR 0x4000 -#define PB13IOR 0x2000 -#define PB12IOR 0x1000 -#define PB11IOR 0x0800 -#define PB10IOR 0x0400 -#define PB9IOR 0x0200 -#define PB8IOR 0x0100 -#define PB7IOR 0x0080 -#define PB6IOR 0x0040 -#define PB5IOR 0x0020 -#define PB4IOR 0x0010 -#define PB3IOR 0x0008 -#define PB2IOR 0x0004 -#define PB1IOR 0x0002 -#define PB0IOR 0x0001 - -/* - * Port B Control Register (PBCR1) - */ -#define PBCR1 PFC_PBCR1 -#define PB15MD1 0x8000 -#define PB15MD0 0x4000 -#define PB14MD1 0x2000 -#define PB14MD0 0x1000 -#define PB13MD1 0x0800 -#define PB13MD0 0x0400 -#define PB12MD1 0x0200 -#define PB12MD0 0x0100 -#define PB11MD1 0x0080 -#define PB11MD0 0x0040 -#define PB10MD1 0x0020 -#define PB10MD0 0x0010 -#define PB9MD1 0x0008 -#define PB9MD0 0x0004 -#define PB8MD1 0x0002 -#define PB8MD0 0x0001 - -#define PB15MD PB15MD1|PB14MD0 -#define PB14MD PB14MD1|PB14MD0 -#define PB13MD PB13MD1|PB13MD0 -#define PB12MD PB12MD1|PB12MD0 -#define PB11MD PB11MD1|PB11MD0 -#define PB10MD PB10MD1|PB10MD0 -#define PB9MD PB9MD1|PB9MD0 -#define PB8MD PB8MD1|PB8MD0 - -#define PB_TXD1 PB11MD1 -#define PB_RXD1 PB10MD1 -#define PB_TXD0 PB9MD1 -#define PB_RXD0 PB8MD1 - -/* - * Port B Control Register (PBCR2) - */ -#define PBCR2 PFC_PBCR2 -#define PB7MD1 0x8000 -#define PB7MD0 0x4000 -#define PB6MD1 0x2000 -#define PB6MD0 0x1000 -#define PB5MD1 0x0800 -#define PB5MD0 0x0400 -#define PB4MD1 0x0200 -#define PB4MD0 0x0100 -#define PB3MD1 0x0080 -#define PB3MD0 0x0040 -#define PB2MD1 0x0020 -#define PB2MD0 0x0010 -#define PB1MD1 0x0008 -#define PB1MD0 0x0004 -#define PB0MD1 0x0002 -#define PB0MD0 0x0001 - -#define PB7MD PB7MD1|PB7MD0 -#define PB6MD PB6MD1|PB6MD0 -#define PB5MD PB5MD1|PB5MD0 -#define PB4MD PB4MD1|PB4MD0 -#define PB3MD PB3MD1|PB3MD0 -#define PB2MD PB2MD1|PB2MD0 -#define PB1MD PB1MD1|PB1MD0 -#define PB0MD PB0MD1|PB0MD0 - -#endif /* _sh7_pfc_h */ diff --git a/bsps/sh/gensh2/include/sh/sh7_sci.h b/bsps/sh/gensh2/include/sh/sh7_sci.h deleted file mode 100644 index 7218313704..0000000000 --- a/bsps/sh/gensh2/include/sh/sh7_sci.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Bit values for the serial control registers of the Hitachi SH704X - * - * From Hitachi tutorials - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _sh7_sci_h -#define _sh7_sci_h - -#include - -/* - * Serial mode register bits - */ - -#define SCI_SYNC_MODE 0x80 -#define SCI_SEVEN_BIT_DATA 0x40 -#define SCI_PARITY_ON 0x20 -#define SCI_ODD_PARITY 0x10 -#define SCI_STOP_BITS_2 0x08 -#define SCI_ENABLE_MULTIP 0x04 -#define SCI_PHI_64 0x03 -#define SCI_PHI_16 0x02 -#define SCI_PHI_4 0x01 -#define SCI_PHI_0 0x00 - -/* - * Serial register offsets, relative to SCI0_SMR or SCI1_SMR - */ - -#define SCI_SMR 0x00 -#define SCI_BRR 0x01 -#define SCI_SCR 0x02 -#define SCI_TDR 0x03 -#define SCI_SSR 0x04 -#define SCI_RDR 0x05 - -/* - * Serial control register bits - */ -#define SCI_TIE 0x80 /* Transmit interrupt enable */ -#define SCI_RIE 0x40 /* Receive interrupt enable */ -#define SCI_TE 0x20 /* Transmit enable */ -#define SCI_RE 0x10 /* Receive enable */ -#define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */ -#define SCI_TEIE 0x04 /* Transmit end interrupt enable */ -#define SCI_CKE1 0x02 /* Clock enable 1 */ -#define SCI_CKE0 0x01 /* Clock enable 0 */ - -/* - * Serial status register bits - */ -#define SCI_TDRE 0x80 /* Transmit data register empty */ -#define SCI_RDRF 0x40 /* Receive data register full */ -#define SCI_ORER 0x20 /* Overrun error */ -#define SCI_FER 0x10 /* Framing error */ -#define SCI_PER 0x08 /* Parity error */ -#define SCI_TEND 0x04 /* Transmit end */ -#define SCI_MPB 0x02 /* Multiprocessor bit */ -#define SCI_MPBT 0x01 /* Multiprocessor bit transfer */ - -/* - * INTC Priority Settings - */ - -#define SCI0_IPMSK 0x00F0 -#define SCI0_LOWIP 0x0010 -#define SCI1_IPMSK 0x000F -#define SCI1_LOWIP 0x0001 - -#endif /* _sh7_sci_h */ diff --git a/bsps/sh/gensh2/include/tm27.h b/bsps/sh/gensh2/include/tm27.h deleted file mode 100644 index 0dfa7bf628..0000000000 --- a/bsps/sh/gensh2/include/tm27.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/bsps/sh/gensh2/start/cpu_asm.c b/bsps/sh/gensh2/start/cpu_asm.c deleted file mode 100644 index d483e2f065..0000000000 --- a/bsps/sh/gensh2/start/cpu_asm.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - * This file contains the basic algorithms for all assembly code used - * in an specific CPU port of RTEMS. These algorithms must be implemented - * in assembly language - * - * NOTE: This port uses a C file with inline assembler instructions - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/* - * This is supposed to be an assembly file. This means that system.h - * and cpu.h should not be included in a "real" cpu_asm file. An - * implementation in assembly should include "cpu_asm.h" - */ - -#include -#include -#include -#include - -#include -#include -#include - -unsigned long *_old_stack_ptr; - -register unsigned long *stack_ptr __asm__ ("r15"); - -/* - * sh_set_irq_priority - * - * this function sets the interrupt level of the specified interrupt - * - * parameters: - * - irq : interrupt number - * - prio: priority to set for this interrupt number - * - * returns: 0 if ok - * -1 on error - */ - -unsigned int sh_set_irq_priority( - unsigned int irq, - unsigned int prio ) -{ - uint32_t shiftcount; - uint32_t prioreg; - uint16_t temp16; - ISR_Level level; - - /* - * first check for valid interrupt - */ - if (( irq > 156) || (irq < 64) || (_Hardware_isr_Table[irq] == _dummy_isp)) - return -1; - /* - * check for valid irq priority - */ - if ( prio > 15 ) - return -1; - - /* - * look up appropriate interrupt priority register - */ - if ( irq > 71) - { - irq = irq - 72; - shiftcount = 12 - ((irq & ~0x03) % 16); - - switch( irq / 16) - { - case 0: { prioreg = INTC_IPRC; break;} - case 1: { prioreg = INTC_IPRD; break;} - case 2: { prioreg = INTC_IPRE; break;} - case 3: { prioreg = INTC_IPRF; break;} - case 4: { prioreg = INTC_IPRG; break;} - case 5: { prioreg = INTC_IPRH; break;} - default: return -1; - } - } - else - { - shiftcount = 12 - 4 * ( irq % 4); - if ( irq > 67) - prioreg = INTC_IPRB; - else - prioreg = INTC_IPRA; - } - - /* - * Set the interrupt priority register - */ - _ISR_Local_disable( level ); - - temp16 = read16( prioreg); - temp16 &= ~( 15 << shiftcount); - temp16 |= prio << shiftcount; - write16( temp16, prioreg); - - _ISR_Local_enable( level ); - - return 0; -} - -/* - * This routine provides the RTEMS interrupt management. - */ - -void __ISR_Handler( uint32_t vector) -{ - ISR_Level level; - - _ISR_Local_disable( level ); - - _Thread_Dispatch_disable(); - - if ( _ISR_Nest_level == 0 ) - { - /* Install irq stack */ - _old_stack_ptr = stack_ptr; - stack_ptr = _CPU_Interrupt_stack_high; - } - - _ISR_Nest_level++; - - _ISR_Local_enable( level ); - - /* call isp */ - if ( _ISR_Vector_table[ vector]) - (*_ISR_Vector_table[ vector ])( vector ); - - _ISR_Local_disable( level ); - - _Thread_Dispatch_unnest( _Per_CPU_Get() ); - - _ISR_Nest_level--; - - if ( _ISR_Nest_level == 0 ) - /* restore old stack pointer */ - stack_ptr = _old_stack_ptr; - - _ISR_Local_enable( level ); - - if ( _ISR_Nest_level ) - return; - - if ( !_Thread_Dispatch_is_enabled() ) { - return; - } - - if ( _Thread_Dispatch_necessary ) { - _Thread_Dispatch(); - } -} diff --git a/bsps/sh/gensh2/start/hw_init.c b/bsps/sh/gensh2/start/hw_init.c deleted file mode 100644 index f3cbb54ecf..0000000000 --- a/bsps/sh/gensh2/start/hw_init.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * hw_init.c: set up sh7045F internal subunits - * Pin and memory assignments assume - * target is Hitachi SH7045F EVB ("lcevb") - * - * Provides two initialization routines: - * A. 'void early_hw_init(void)' for 'start.S' - * sets up hw needed for early RTEMS boot, and - * B. 'void bsp_hw_init(void)' for 'bspstart.c' - * sets up hardware used by this BSP. - * - * Author: John M. Mills (jmills@tga.com) - * COPYRIGHT(c) 2000, TGA Technologies, Inc - * Norcross, GA 30071 U.S.A - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Adapted from Hitachi EVB7045F tutorial files by: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * - * - * This file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - */ - -#include - -#include - -#include -#include -#include - -/* exported entries */ -extern void bsp_hw_init (void); -extern void early_hw_init (void); - -/* called from 'start.S' on "#ifdef START_HW_INIT" */ -void early_hw_init (void) -{ -#ifdef STANDALONE_EVB - /* STANDALONE_EVB minimally sets up bus and DRAM here */ - /* no STANDALONE_EVB accepts defaults from debug monitor */ - - /* FIXME: replace 'magic numbers' with logical names */ - - write16(0x2020, BSC_BCR1); /* Bus width access - 32-bit on CS1 */ - write16(0xF3DD, BSC_BCR2); /* Idle cycles CS3-CS0 - 0 idle cycles*/ - write16(0xFF3F, BSC_WCR1); /* Waits for CS3-CS0 - 3 waits on CS1 */ - write16(0x000F, BSC_WCR2); /* Waits for DRAM/DMA access - default */ - write16(0x0000, BSC_DCR); /* DRAM control - default */ - write16(0x0000, BSC_RTCSR); /* DRAM refresh - default */ - write16(0x0000, BSC_RTCNT); /* DRAM refresh counter - default*/ - write16(0x0000, BSC_RTCOR); /* DRAM refresh compare match - default */ -#endif - - /* add early-init functions here */ - -}; - -/* to be called from 'bspstart.c' */ -void bsp_hw_init (void) -{ - uint16_t temp16; - -#ifdef STANDALONE_EVB - /* STANDALONE_EVB: sets up PFC */ - /* no STANDALONE_EVB: accepts defaults, adds RESET */ - - /* FIXME: replace 'magic numbers' */ - - write16(0x5000, PFC_PACRH); /* Pin function controller - WRHH, WRHL */ - write16(0x1550, PFC_PACRL1); /* Pin fun. controller - WRH,WRL,RD,CS1 */ - write16(0x0000, PFC_PBCR1); /* Pin function controller - default */ - write16(0x2005, PFC_PBCR2); /* Pin fcn. controller - A18,A17,A16 */ - write16(0xFFFF, PFC_PCCR); /* Pin function controller - A15-A0 */ - write16(0x5555, PFC_PDCRH1); /* Pin function controller - D31-D24 */ - write16(0x5555, PFC_PDCRH2); /* Pin function controller - D23-D16 */ - write16(0xFFFF, PFC_PDCRL); /* Pin function controller - D15-D0 */ - write16(0x0000, PFC_IFCR); /* Pin function controller - default */ - write16(0x0000, PFC_PACRL2); /* default disconnects all I/O pins;*/ - /* [re-connected by DEVICE_open()] */ -#endif - - /* default hardware setup for SH7045F EVB */ - - /* PFC: General I/O except pin 13 (reset): */ - temp16 = read16(PFC_PECR1); - temp16 |= 0x0800; - write16(temp16, PFC_PECR1); - - /* All I/O lines bits 7-0: */ - write16(0x00, PFC_PECR2); - - /* P5 (LED) out, all other pins in: */ - temp16 = read16(PFC_PEIOR); - temp16 |= 0x0020; - write16(temp16, PFC_PEIOR); - -} diff --git a/bsps/sh/gensh2/start/ispsh7045.c b/bsps/sh/gensh2/start/ispsh7045.c deleted file mode 100644 index 874d930ba1..0000000000 --- a/bsps/sh/gensh2/start/ispsh7045.c +++ /dev/null @@ -1,310 +0,0 @@ -/* - * This file contains the isp frames for the user interrupts. - * From these procedures __ISR_Handler is called with the vector number - * as argument. - * - * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in - * some releases of gcc doesn't properly handle #pragma interrupt, if a - * file contains both isrs and normal functions. - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modified to reflect isp entries for sh7045 processor: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * August, 1999 - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - */ - -#include - -/* - * This is a exception vector table - * - * It has the same structure as the actual vector table (vectab) - */ - - -/* SH-2 ISR Table */ -#include - -CPU_ISR_raw_handler _Hardware_isr_Table[256]={ -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* PWRon Reset, Maual Reset,...*/ -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, -_nmi_isp, _usb_isp, /* irq 11, 12*/ -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, -/* trapa 0 -31 */ -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp, /* external H/W: irq 64-71 */ -_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp, -_dma0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DMAC: irq 72-87*/ -_dma1_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dma2_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dma3_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_mtua0_isp, _mtub0_isp, _mtuc0_isp, _mtud0_isp, /* MTUs: irq 88-127 */ -_mtuv0_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_mtua1_isp, _mtub1_isp, _dummy_isp, _dummy_isp, -_mtuv1_isp, _mtuu1_isp, _dummy_isp, _dummy_isp, -_mtua2_isp, _mtub2_isp, _dummy_isp, _dummy_isp, -_mtuv2_isp, _mtuu2_isp, _dummy_isp, _dummy_isp, -_mtua3_isp, _mtub3_isp, _mtuc3_isp, _mtud3_isp, -_mtuv3_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_mtua4_isp, _mtub4_isp, _mtuc4_isp, _mtud4_isp, -_mtuv4_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp, /* SCI0-1: irq 128-135*/ -_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp, -_adi0_isp, _adi1_isp, _dummy_isp, _dummy_isp, /* ADC0-1: irq 136-139*/ -_dtci_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DTU: irq 140-143 */ -_cmt0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* CMT0-1: irq 144-151 */ -_cmt1_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_wdt_isp, /* WDT: irq 152*/ -_bsc_isp, _dummy_isp, _dummy_isp, /* BSC: irq 153-155*/ -_oei_isp, /* I/O Port: irq 156*/ -}; - -#define Str(a)#a - -/* - * Some versions of gcc and all version of egcs at least until egcs-1.1b - * are not able to handle #pragma interrupt correctly if more than 1 isr is - * contained in a file and when optimizing. - * We try to work around this problem by using the macro below. - */ -#define isp( name, number, func)\ -__asm__ (".global _"Str(name)"\n\t"\ - "_"Str(name)": \n\t"\ - " mov.l r0,@-r15 \n\t"\ - " mov.l r1,@-r15 \n\t"\ - " mov.l r2,@-r15 \n\t"\ - " mov.l r3,@-r15 \n\t"\ - " mov.l r4,@-r15 \n\t"\ - " mov.l r5,@-r15 \n\t"\ - " mov.l r6,@-r15 \n\t"\ - " mov.l r7,@-r15 \n\t"\ - " mov.l r14,@-r15 \n\t"\ - " sts.l pr,@-r15 \n\t"\ - " sts.l mach,@-r15 \n\t"\ - " sts.l macl,@-r15 \n\t"\ - " mov r15,r14 \n\t"\ - " mov.l "Str(name)"_v, r2 \n\t"\ - " mov.l "Str(name)"_k, r1\n\t"\ - " jsr @r1 \n\t"\ - " mov r2,r4 \n\t"\ - " mov r14,r15 \n\t"\ - " lds.l @r15+,macl \n\t"\ - " lds.l @r15+,mach \n\t"\ - " lds.l @r15+,pr \n\t"\ - " mov.l @r15+,r14 \n\t"\ - " mov.l @r15+,r7 \n\t"\ - " mov.l @r15+,r6 \n\t"\ - " mov.l @r15+,r5 \n\t"\ - " mov.l @r15+,r4 \n\t"\ - " mov.l @r15+,r3 \n\t"\ - " mov.l @r15+,r2 \n\t"\ - " mov.l @r15+,r1 \n\t"\ - " mov.l @r15+,r0 \n\t"\ - " rte \n\t"\ - " nop \n\t"\ - " .align 2 \n\t"\ - #name"_k: \n\t"\ - ".long "Str(func)"\n\t"\ - #name"_v: \n\t"\ - ".long "Str(number)); - -/************************************************ - * Dummy interrupt service procedure for - * interrupts being not allowed --> Trap 34 - ************************************************/ -__asm__ (" .section .text\n\ -.global __dummy_isp\n\ -__dummy_isp:\n\ - mov.l r14,@-r15\n\ - mov r15, r14\n\ - trapa #34\n\ - mov.l @r15+,r14\n\ - rte\n\ - nop"); - -/******************************************************************* - * ISP Vector Table for sh7045 family of processors * - *******************************************************************/ - - -/***************************** - * Non maskable interrupt - *****************************/ -isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler); - -/***************************** - * User break controller - *****************************/ -isp( _usb_isp, USB_ISP_V, ___ISR_Handler); - -/***************************** - * External interrupts 0-7 - *****************************/ -isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler); -isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler); -isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler); -isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler); -isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler); -isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler); -isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler); -isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler); - -/***************************** - * DMA - controller - *****************************/ -isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler); -isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler); -isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler); -isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler); - - -/***************************** - * Match timer unit - *****************************/ - -/***************************** - * Timer 0 - *****************************/ -isp( _mtua0_isp, MTUA0_ISP_V, ___ISR_Handler); -isp( _mtub0_isp, MTUB0_ISP_V, ___ISR_Handler); -isp( _mtuc0_isp, MTUC0_ISP_V, ___ISR_Handler); -isp( _mtud0_isp, MTUD0_ISP_V, ___ISR_Handler); -isp( _mtuv0_isp, MTUV0_ISP_V, ___ISR_Handler); - -/***************************** - * Timer 1 - *****************************/ -isp( _mtua1_isp, MTUA1_ISP_V, ___ISR_Handler); -isp( _mtub1_isp, MTUB1_ISP_V, ___ISR_Handler); -isp( _mtuv1_isp, MTUV1_ISP_V, ___ISR_Handler); -isp( _mtuu1_isp, MTUU1_ISP_V, ___ISR_Handler); - -/***************************** - * Timer 2 - *****************************/ -isp( _mtua2_isp, MTUA2_ISP_V, ___ISR_Handler); -isp( _mtub2_isp, MTUB2_ISP_V, ___ISR_Handler); -isp( _mtuv2_isp, MTUV2_ISP_V, ___ISR_Handler); -isp( _mtuu2_isp, MTUU2_ISP_V, ___ISR_Handler); - -/***************************** - * Timer 3 - *****************************/ -isp( _mtua3_isp, MTUA3_ISP_V, ___ISR_Handler); -isp( _mtub3_isp, MTUB3_ISP_V, ___ISR_Handler); -isp( _mtuc3_isp, MTUC3_ISP_V, ___ISR_Handler); -isp( _mtud3_isp, MTUD3_ISP_V, ___ISR_Handler); -isp( _mtuv3_isp, MTUV3_ISP_V, ___ISR_Handler); - -/***************************** - * Timer 4 - *****************************/ -isp( _mtua4_isp, MTUA4_ISP_V, ___ISR_Handler); -isp( _mtub4_isp, MTUB4_ISP_V, ___ISR_Handler); -isp( _mtuc4_isp, MTUC4_ISP_V, ___ISR_Handler); -isp( _mtud4_isp, MTUD4_ISP_V, ___ISR_Handler); -isp( _mtuv4_isp, MTUV4_ISP_V, ___ISR_Handler); - - -/***************************** - * Serial interfaces - *****************************/ - -/***************************** - * Serial interface 0 - *****************************/ -isp( _eri0_isp, ERI0_ISP_V, ___ISR_Handler); -isp( _rxi0_isp, RXI0_ISP_V, ___ISR_Handler); -isp( _txi0_isp, TXI0_ISP_V, ___ISR_Handler); -isp( _tei0_isp, TEI0_ISP_V, ___ISR_Handler); - -/***************************** - * Serial interface 1 - *****************************/ -isp( _eri1_isp, ERI1_ISP_V, ___ISR_Handler); -isp( _rxi1_isp, RXI1_ISP_V, ___ISR_Handler); -isp( _txi1_isp, TXI1_ISP_V, ___ISR_Handler); -isp( _tei1_isp, TEI1_ISP_V, ___ISR_Handler); - - -/****************************** - * A/D converters - * ADC0-1 - ******************************/ -isp( _adi0_isp, ADI0_ISP_V, ___ISR_Handler); -isp( _adi1_isp, ADI1_ISP_V, ___ISR_Handler); - - -/****************************** - * Data transfer controller - ******************************/ -isp( _dtci_isp, DTC_ISP_V, ___ISR_Handler); - - -/****************************** - * Counter match timer - ******************************/ -isp( _cmt0_isp, CMT0_ISP_V, ___ISR_Handler); -isp( _cmt1_isp, CMT1_ISP_V, ___ISR_Handler); - - -/****************************** - * Watchdog timer - ******************************/ -isp( _wdt_isp, WDT_ISP_V, ___ISR_Handler); - - -/****************************** - * DRAM refresh control unit - * of bus state controller - ******************************/ -isp( _bsc_isp, CMI_ISP_V, ___ISR_Handler); - -/****************************** - * I/O port - ******************************/ -isp( _oei_isp, OEI_ISP_V, ___ISR_Handler); - - -/***************************** - * Parity control unit of - * the bus state controller - * NOT PROVIDED IN SH-2 - *****************************/ -/* isp( _prt_isp, PRT_ISP_V, ___ISR_Handler); */ diff --git a/bsps/sh/gensh2/start/linkcmds b/bsps/sh/gensh2/start/linkcmds deleted file mode 100644 index ac59afa406..0000000000 --- a/bsps/sh/gensh2/start/linkcmds +++ /dev/null @@ -1,252 +0,0 @@ -/* - * This is an adapted linker script from egcs-1.0.1 - * - * Memory layout for an SH7045F with main memory in area 2 - * This memory layout it very similar to that used for Hitachi's - * EVB with CMON in FLASH - * - * NOTE: The ram start address may vary, all other start addresses are fixed - * Not suiteable for gdb's simulator - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modified to reflect SH7045F processor and EVB: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - */ - -OUTPUT_ARCH(sh) -ENTRY(_start) -STARTUP(start.o) - -/* These assignments load code into SH7045F EVB SRAM for monitor debugging */ - -_RamBase = DEFINED(_RamBase) ? _RamBase : 0x00440000; -_RamSize = DEFINED(_RamSize) ? _RamSize : 512K; -_RamEnd = _RamBase + _RamSize; -_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0; - -MEMORY -{ - rom : o = 0x00400000, l = 0x00040000 - ram : o = 0x00440000, l = 0x00080000 - onchip_peri : o = 0xFFFF8000, l = 0x00000800 - onchip_ram : o = 0xFFFFF000, l = 0x00001000 -} - -/* Sections are defined for RAM loading and monitor debugging */ -SECTIONS -{ - /* boot vector table */ - .monvects 0x00400000 (NOLOAD): { - _monvects = . ; - } > rom - - /* monitor play area */ - .monram 0x00440000 (NOLOAD) : - { - _ramstart = .; - } > ram - - /* monitor vector table */ - .vects 0x00442000 (NOLOAD) : { - _vectab = . ; - *(.vects); - } - - /* Read-only sections, merged into text segment: */ - - . = 0x00444000 ; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .gnu.version : { *(.gnu.version) } - .gnu.version_d : { *(.gnu.version_d) } - .gnu.version_r : { *(.gnu.version_r) } - .rela.dyn : - { - *(.rela.init) - *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) - *(.rela.fini) - *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) - *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) - *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) - *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) - *(.rela.ctors) - *(.rela.dtors) - *(.rela.got) - *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) - *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) - *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) - *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) - *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) - } >ram - .rel.text : - { *(.rel.text) *(.rel.gnu.linkonce.t*) } - .rel.data : - { *(.rel.data) *(.rel.gnu.linkonce.d*) } - .rel.rodata : - { *(.rel.rodata*) *(.rel.gnu.linkonce.r*) } - .rel.got : { *(.rel.got) } - .rel.ctors : { *(.rel.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rel.init : { *(.rel.init) } - .rel.fini : { *(.rel.fini) } - .rel.bss : { *(.rel.bss) } - .rel.plt : { *(.rel.plt) } - .plt : { *(.plt) } - .text . : - { - _start = .; - *(.text*) - *(.stub) - - /* - * Special FreeBSD sysctl sections. - */ - . = ALIGN (16); - ___start_set_sysctl_set = .; - *(set_sysc*); /* set_sysctl_* but name is truncated by SH-coff */ - ___stop_set_sysctl_set = ABSOLUTE(.); - *(set_doma*); /* set_domain_* but name is truncated by SH-coff */ - *(set_pseu*); /* set_pseudo_* but name is truncated by SH-coff */ - - /* .gnu.warning sections are handled specially by elf32.em. */ - *(.gnu.warning) - *(.gnu.linkonce.t*) - } > ram - _etext = .; - PROVIDE (etext = .); - .init . : { KEEP(*(.init)) } > ram =0 - .fini . : { KEEP(*(.fini)) } > ram =0 - .ctors . : { KEEP(*(.ctors)) } > ram =0 - .dtors . : { KEEP(*(.dtors)) } > ram =0 - .rodata . : { *(.rodata*) KEEP (*(SORT(.rtemsroset.*))) *(.gnu.linkonce.r*) } > ram - .rodata1 . : { *(.rodata1) } > ram - .tdata : { - __TLS_Data_begin = .; - *(.tdata .tdata.* .gnu.linkonce.td.*) - __TLS_Data_end = .; - } > ram - .tbss : { - __TLS_BSS_begin = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) - __TLS_BSS_end = .; - } > ram - __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin; - __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin; - __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin; - __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin; - __TLS_Size = __TLS_BSS_end - __TLS_Data_begin; - __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); - /* Adjust the address for the data segment. We want to adjust up to - the same address within the page on the next page up. */ - . = ALIGN(128) + (. & (128 - 1)); - .data . : - { - *(.data*) - KEEP (*(SORT(.rtemsrwset.*))) - *(.gcc_exc*) - ___EH_FRAME_BEGIN__ = .; - *(.eh_fram*) - ___EH_FRAME_END__ = .; - LONG(0); - *(.gcc_except_table*) - *(.gnu.linkonce.d*) - CONSTRUCTORS - } > ram - .data1 . : { *(.data1) } - .got . : { *(.got.plt) *(.got) } - .dynamic . : { *(.dynamic) } - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - .sdata . : { *(.sdata) } - _edata = .; - PROVIDE (edata = .); - __bss_start = .; - .sbss . : { *(.sbss*) *(.scommon) } - .bss . : - { - *(.dynbss) - *(.bss .bss* .gnu.linkonce.b*) - *(COMMON) - } > ram - _end = . ; - PROVIDE (end = .); - - .noinit (NOLOAD) : { - *(SORT_BY_NAME (SORT_BY_ALIGNMENT (.noinit*))) - } > ram - - .rtemsstackinterrupt (NOLOAD) : { - *(.rtemsstack.interrupt) - } > onchip_ram - - .rtemsstack (NOLOAD) : { - *(SORT(.rtemsstack.*)) - } > ram - - _WorkAreaBase = . ; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* These must appear regardless of . */ - - /* Addition to let linker know about custom section for GDB pretty-printing support. */ - .debug_gdb_scripts 0 : { *(.debug_gdb_scripts) } -} diff --git a/bsps/sh/gensh2/start/linkcmds.ram b/bsps/sh/gensh2/start/linkcmds.ram deleted file mode 100644 index c6f173d129..0000000000 --- a/bsps/sh/gensh2/start/linkcmds.ram +++ /dev/null @@ -1,251 +0,0 @@ -/* - * This is an adapted linker script from egcs-1.0.1 - * - * Memory layout for an SH7045F with main memory in area 2 - * This memory layout it very similar to that used for Hitachi's - * EVB with CMON in FLASH - * - * NOTE: The ram start address may vary, all other start addresses are fixed - * Not suiteable for gdb's simulator - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modified to reflect SH7045F processor and EVB: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - */ - -OUTPUT_ARCH(sh) -ENTRY(_start) -STARTUP(start.o) - -/* These assignments load code into SH7045F EVB SRAM for monitor debugging */ -_RamBase = DEFINED(_RamBase) ? _RamBase : 0x00440000; -_RamSize = DEFINED(_RamSize) ? _RamSize : 512K; -_RamEnd = _RamBase + _RamSize; -_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0; - -MEMORY -{ - rom : o = 0x00400000, l = 0x00040000 - ram : o = 0x00440000, l = 0x00080000 - onchip_peri : o = 0xFFFF8000, l = 0x00000800 - onchip_ram : o = 0xFFFFF000, l = 0x00001000 -} - -/* Sections are defined for RAM loading and monitor debugging */ -SECTIONS -{ - /* boot vector table */ - .monvects 0x00400000 (NOLOAD): { - _monvects = . ; - } > rom - - /* monitor play area */ - .monram 0x00440000 (NOLOAD) : - { - _ramstart = .; - } > ram - - /* monitor vector table */ - .vects 0x00442000 (NOLOAD) : { - _vectab = . ; - *(.vects); - } - - /* Read-only sections, merged into text segment: */ - - . = 0x00444000 ; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .gnu.version : { *(.gnu.version) } - .gnu.version_d : { *(.gnu.version_d) } - .gnu.version_r : { *(.gnu.version_r) } - .rela.dyn : - { - *(.rela.init) - *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) - *(.rela.fini) - *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) - *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) - *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) - *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) - *(.rela.ctors) - *(.rela.dtors) - *(.rela.got) - *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) - *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) - *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) - *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) - *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) - } >ram - .rel.text : - { *(.rel.text) *(.rel.gnu.linkonce.t*) } - .rel.data : - { *(.rel.data) *(.rel.gnu.linkonce.d*) } - .rel.rodata : - { *(.rel.rodata) *(.rel.gnu.linkonce.r*) } - .rel.got : { *(.rel.got) } - .rel.ctors : { *(.rel.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rel.init : { *(.rel.init) } - .rel.fini : { *(.rel.fini) } - .rel.bss : { *(.rel.bss) } - .rel.plt : { *(.rel.plt) } - .init : { *(.init) } =0 - .plt : { *(.plt) } - .text . : - { - *(.text*) - *(.stub) - - /* - * Special FreeBSD sysctl sections. - */ - . = ALIGN (16); - ___start_set_sysctl_set = .; - *(set_sysc*); /* set_sysctl_* but name is truncated by SH-coff */ - ___stop_set_sysctl_set = ABSOLUTE(.); - *(set_doma*); /* set_domain_* but name is truncated by SH-coff */ - *(set_pseudo_*); - - /* .gnu.warning sections are handled specially by elf32.em. */ - *(.gnu.warning) - *(.gnu.linkonce.t*) - } > ram - _etext = .; - PROVIDE (etext = .); - .fini . : { *(.fini) } > ram =0 - .rodata . : { *(.rodata) KEEP (*(SORT(.rtemsroset.*))) *(.gnu.linkonce.r*) } > ram - .rodata1 . : { *(.rodata1) } > ram - .tdata : { - __TLS_Data_begin = .; - *(.tdata .tdata.* .gnu.linkonce.td.*) - __TLS_Data_end = .; - } > ram - .tbss : { - __TLS_BSS_begin = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) - __TLS_BSS_end = .; - } > ram - __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin; - __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin; - __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin; - __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin; - __TLS_Size = __TLS_BSS_end - __TLS_Data_begin; - __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); - /* Adjust the address for the data segment. We want to adjust up to - the same address within the page on the next page up. */ - . = ALIGN(128) + (. & (128 - 1)); - .data . : - { - *(.data) - KEEP (*(SORT(.rtemsrwset.*))) - *(.gnu.linkonce.d*) - CONSTRUCTORS - } > ram - .data1 . : { *(.data1) } - .ctors . : - { - ___ctors = .; - *(.ctors) - ___ctors_end = .; - } - .dtors . : - { - ___dtors = .; - *(.dtors) - ___dtors_end = .; - } - .got . : { *(.got.plt) *(.got) } - .dynamic . : { *(.dynamic) } - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - .sdata . : { *(.sdata) } - _edata = .; - PROVIDE (edata = .); - __bss_start = .; - .sbss . : { *(.sbss*) *(.scommon) } - .bss . : - { - *(.dynbss) - *(.bss .bss* .gnu.linkonce.b*) - *(COMMON) - } > ram - _end = . ; - PROVIDE (end = .); - - .noinit (NOLOAD) : { - *(SORT_BY_NAME (SORT_BY_ALIGNMENT (.noinit*))) - } > ram - - .rtemsstackidle (NOLOAD) : { - *(SORT(.rtemsstack.idle*)) - } > ram - - _WorkAreaBase = . ; - - .rtemsstack (NOLOAD) : { - *(SORT(.rtemsstack.*)) - } > onchip_ram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* These must appear regardless of . */ -} diff --git a/bsps/sh/gensh2/start/linkcmds.rom b/bsps/sh/gensh2/start/linkcmds.rom deleted file mode 100644 index 2d3071e260..0000000000 --- a/bsps/sh/gensh2/start/linkcmds.rom +++ /dev/null @@ -1,256 +0,0 @@ -/* - * This is an adapted linker script from egcs-1.0.1 - * - * Memory layout for an SH7045F with main memory in area 2 - * This memory layout it very similar to that used for Hitachi's - * EVB with CMON in FLASH - * - * NOTE: The ram start address may vary, all other start addresses are fixed - * Not suiteable for gdb's simulator - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modified to reflect SH7045F processor and EVB: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - */ - -OUTPUT_ARCH(sh) -ENTRY(_start) -STARTUP(start.o) - -/* These asignments represent actual SH7045F EVB architecture */ -_RamBase = DEFINED(_RamBase) ? _RamBase : 0x00400000; -_RamSize = DEFINED(_RamSize) ? _RamSize : 0x0008000; -_RamEnd = _RamBase + _RamSize; -_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0; - -MEMORY -{ - rom : o = 0x00000000, l = 0x00040000 - ram : o = 0x00400000, l = 0x00080000 - onchip_peri : o = 0xFFFF8000, l = 0x00000800 - onchip_ram : o = 0xFFFFF000, l = 0x00001000 -} - - -/* Sections are defined for RAM loading and monitor debugging */ -SECTIONS -{ - /* boot vector table */ - .monvects 0x00000000 (NOLOAD): { - _monvects = . ; - } > rom - - /* monitor play area */ - .monram 0x00400000 (NOLOAD) : - { - _ramstart = .; - } > ram - - /* monitor vector table */ - .vects 0x00402000 (NOLOAD) : { - _vectab = . ; - *(.vects); - } - - /* Read-only sections, merged into text segment: */ - - . = 0x00404000 ; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .gnu.version : { *(.gnu.version) } - .gnu.version_d : { *(.gnu.version_d) } - .gnu.version_r : { *(.gnu.version_r) } - .rela.dyn : - { - *(.rela.init) - *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) - *(.rela.fini) - *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) - *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) - *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) - *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) - *(.rela.ctors) - *(.rela.dtors) - *(.rela.got) - *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) - *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) - *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) - *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) - *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) - } >ram - .rel.text : - { *(.rel.text) *(.rel.gnu.linkonce.t*) } - .rel.data : - { *(.rel.data) *(.rel.gnu.linkonce.d*) } - .rel.rodata : - { *(.rel.rodata) *(.rel.gnu.linkonce.r*) } - .rel.got : { *(.rel.got) } - .rel.ctors : { *(.rel.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rel.init : { *(.rel.init) } - .rel.fini : { *(.rel.fini) } - .rel.bss : { *(.rel.bss) } - .rel.plt : { *(.rel.plt) } - .init : { *(.init) } =0 - .plt : { *(.plt) } - .text . : - { - *(.text*) - *(.stub) - - /* - * Special FreeBSD sysctl sections. - */ - . = ALIGN (16); - ___start_set_sysctl_set = .; - *(set_sysc*); /* set_sysctl_* but name is truncated by SH-coff */ - ___stop_set_sysctl_set = ABSOLUTE(.); - *(set_doma*); /* set_domain_* but name is truncated by SH-coff */ - *(set_pseudo_*); - - /* .gnu.warning sections are handled specially by elf32.em. */ - *(.gnu.warning) - *(.gnu.linkonce.t*) - } > ram - _etext = .; - PROVIDE (etext = .); - .fini . : { *(.fini) } > ram =0 - .rodata . : { *(.rodata) KEEP (*(SORT(.rtemsroset.*))) *(.gnu.linkonce.r*) } > ram - .rodata1 . : { *(.rodata1) } > ram - .tdata : { - __TLS_Data_begin = .; - *(.tdata .tdata.* .gnu.linkonce.td.*) - __TLS_Data_end = .; - } > ram - .tbss : { - __TLS_BSS_begin = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) - __TLS_BSS_end = .; - } > ram - __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin; - __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin; - __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin; - __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin; - __TLS_Size = __TLS_BSS_end - __TLS_Data_begin; - __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); - /* Adjust the address for the data segment. We want to adjust up to - the same address within the page on the next page up. */ - . = ALIGN(128) + (. & (128 - 1)); - .data . : - { - *(.data) - KEEP (*(SORT(.rtemsrwset.*))) - *(.gnu.linkonce.d*) - CONSTRUCTORS - } > ram - .data1 . : { *(.data1) } - .ctors . : - { - ___ctors = .; - *(.ctors) - ___ctors_end = .; - } - .dtors . : - { - ___dtors = .; - *(.dtors) - ___dtors_end = .; - } - .got . : { *(.got.plt) *(.got) } - .dynamic . : { *(.dynamic) } - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - .sdata . : { *(.sdata) } - _edata = .; - PROVIDE (edata = .); - __bss_start = .; - .sbss . : { *(.sbss*) *(.scommon) } - .bss . : - { - *(.dynbss) - *(.bss .bss* .gnu.linkonce.b*) - *(COMMON) - } > ram - _end = . ; - PROVIDE (end = .); - - .noinit (NOLOAD) : { - *(SORT_BY_NAME (SORT_BY_ALIGNMENT (.noinit*))) - } > ram - - .rtemsstackidle (NOLOAD) : { - *(SORT(.rtemsstack.idle*)) - } > ram - - _HeapStart = . ; - . = . + 1024 * 20 ; - PROVIDE( _HeapEnd = . ); - - _WorkAreaBase = . ; - - .rtemsstack (NOLOAD) : { - *(SORT(.rtemsstack.*)) - } > onchip_ram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* These must appear regardless of . */ -} diff --git a/bsps/sh/gensh2/start/start.S b/bsps/sh/gensh2/start/start.S deleted file mode 100644 index 47c725f206..0000000000 --- a/bsps/sh/gensh2/start/start.S +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * Modified to reflect Hitachi EDK SH7045F: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - * - * COPYRIGHT (c) 1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include - - BEGIN_CODE - PUBLIC(start) - -SYM (start): - ! install the stack pointer - mov.l stack_k,r15 - -#ifdef START_HW_INIT /* from $RTEMS_BSP.cfg */ - ! Initialize minimal hardware - mov.l hw_init_k, r0 - jsr @r0 - nop !dead slot -#endif /* START_HW_INIT */ - - ! zero out bss - mov.l edata_k,r0 - mov.l end_k,r1 - mov #0,r2 -0: - mov.l r2,@r0 - add #4,r0 - cmp/ge r0,r1 - bt 0b - - ! copy the vector table from rom to ram - mov.l vects_k,r0 ! vectab - mov #0,r1 ! address of boot vector table - mov #0,r2 ! number of bytes copied - mov.w vects_size,r3 ! size of entries in vectab -1: - mov.l @r1+,r4 - mov.l r4,@r0 - add #4,r0 - add #1,r2 - cmp/hi r3,r2 - bf 1b - -#ifndef STANDALONE_EVB - ! overlay monitor vectors onto RTEMS table template - ! code adapted from Hitachi EDK7045F User Manual: "Copyvect.s" - mova vects_k,r0 - mov.l @r0, r1 ! Shadow vect tbl addr - stc vbr, r2 ! Original vect tbl addr - and #0, r0 - mov r0, r4 ! 0 in r4 and r0 - -!trapa #32 - or #0x80, r0 - mov.l @(r0,r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!cpu addr err - or #0x24, r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!ill slot - or #0x18, r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!ill inst - or #0x10, r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!nmi - or #0x2c, r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!User brk - or #0x30, r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!sci0 err - or #0x80, r0 - rotl r0 - rotl r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 -!sci rx - or #0x81, r0 - rotl r0 - rotl r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - - stc vbr,r3 ! capture copy of monitor vbr - mov.l vbrtemp_k,r0 - mov.l r3, @r0 - mov.l vects_k,r0 ! point vbr to vectab - ldc r0,vbr -#endif /* ! STANDALONE_EVB */ - - ! call the mainline - mov #0,r4 ! command line - mov.l main_k,r0 - jsr @r0 - nop - - ! call exit - mov r0,r4 - mov.l exit_k,r0 - jsr @r0 - or r0,r0 - - mov.l vbrtemp_k,r0 ! restore original vbr - mov.l @r0,r3 - ldc r3, vbr - trapa #13 ! UBR capture by monitor - nop !debug dead-slot target - - END_CODE - - .align 2 -stack_k: - .long SYM(_ISR_Stack_area_end) -edata_k: - .long SYM(edata) -end_k: - .long SYM(end) -main_k: - .long SYM(boot_card) -exit_k: - .long SYM(exit) -#ifdef START_HW_INIT /* from $RTEMS_BSP.cfg */ -hw_init_k: - .long SYM(early_hw_init) -#endif /* START_HW_INIT */ -vbrtemp_k: - .long SYM(vbrtemp) -vects_k: - .long SYM(vectab) -vects_size: - .word 255 - -#ifdef __ELF__ - .section .bss,"aw" -#else - .section .bss -#endif -SYM(vbrtemp): - .long 0x0 diff --git a/bsps/sh/gensh2/start/start.ram b/bsps/sh/gensh2/start/start.ram deleted file mode 100644 index f6bd16e4b2..0000000000 --- a/bsps/sh/gensh2/start/start.ram +++ /dev/null @@ -1,188 +0,0 @@ -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modified to reflect Hitachi EDK SH7045F: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - */ - -#include "asm.h" - - BEGIN_CODE - PUBLIC(start) - -SYM (start): - ! install the stack pointer - mov.l stack_k,r15 - -#ifdef START_HW_INIT /* from $RTEMS_BSP.cfg */ - ! Initialize minimal hardware - mov.l hw_init_k, r0 - jsr @r0 - nop !debug dead-slot target -#endif /* START_HW_INIT */ - - ! zero out bss - mov.l edata_k,r0 - mov.l end_k,r1 - mov #0,r2 -0: - mov.l r2,@r0 - add #4,r0 - cmp/ge r0,r1 - bt 0b - nop !debug dead-slot target - - ! copy the vector table from rom to ram - mov.l vects_k,r0 ! vectab - mov #0,r1 ! address of boot vector table - mov #0,r2 ! number of bytes copied - mov.w vects_size,r3 ! size of entries in vectab -1: - mov.l @r1+,r4 - mov.l r4,@r0 - add #4,r0 - add #1,r2 - cmp/hi r3,r2 - bf 1b - nop !debug dead-slot target - - ! overlay monitor vectors onto RTEMS table template - ! code adapted from Hitachi EDK7045F User Manual: "Copyvect.s" - mova vects_k,r0 - mov.l @r0, r1 ! Shadow vect tbl addr - stc vbr, r2 ! Original vect tbl addr - and #0, r0 - mov r0, r4 ! 0 in r4 and r0 - -!trapa #32 - or #0x80, r0 - mov.l @(r0,r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!cpu addr err - or #0x24, r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!ill slot - or #0x18, r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!ill inst - or #0x10, r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!nmi - or #0x2c, r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!User brk - or #0x30, r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 - -!sci0 err - or #0x80, r0 - rotl r0 - rotl r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - mov r4, r0 -!sci rx - or #0x81, r0 - rotl r0 - rotl r0 - mov.l @(r0, r2), r3 - mov.l r3, @(r0, r1) - - stc vbr,r3 ! capture copy of monitor vbr - mov.l vbrtemp_k,r0 - mov.l r3, @r0 - mov.l vects_k,r0 ! point vbr to vectab - ldc r0,vbr - - ! call the mainline - mov #0,r4 ! argc - mov #0,r5 ! argv - can place in dead slot - mov.l main_k,r0 - jsr @r0 - nop !debug dead-slot target - - ! call exit - mov r0,r4 - mov.l exit_k,r0 - or r0,r0 - jsr @r0 - nop !debug dead-slot target - - mov.l vbrtemp_k,r0 ! restore original vbr - mov.l @r0,r3 - ldc r3, vbr - trapa #13 ! UBR capture by monitor - nop !debug dead-slot target - - END_CODE - - .align 2 -stack_k: - .long SYM(_ISR_Stack_area_end) -edata_k: - .long SYM(edata) -end_k: - .long SYM(end) -main_k: - .long SYM(boot_card) -exit_k: - .long SYM(exit) -#ifdef START_HW_INIT /* from $RTEMS_BSP.cfg */ -hw_init_k: - .long SYM(hw_initialize) -#endif /* START_HW_INIT */ -vbrtemp_k: - .long SYM(vbrtemp) -vects_k: - .long SYM(vectab) -vects_size: - .word 255 - -#ifdef __ELF__ - .section .bss,"aw" -#else - .section .bss -#endif -SYM(vbrtemp): - .long 0x0 - diff --git a/bsps/sh/gensh2/start/start.rom b/bsps/sh/gensh2/start/start.rom deleted file mode 100644 index 533cf5ee66..0000000000 --- a/bsps/sh/gensh2/start/start.rom +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include "asm.h" - - BEGIN_CODE - PUBLIC(start) -SYM (start): - ! install the stack pointer - mov.l stack_k,r15 - - ! zero out bss - mov.l edata_k,r0 - mov.l end_k,r1 - mov #0,r2 -0: - mov.l r2,@r0 - add #4,r0 - cmp/ge r0,r1 - bt 0b - - ! copy the vector table from rom to ram - mov.l vects_k,r0 ! vectab - mov #0,r1 ! address of boot vector table - mov #0,r2 | number of bytes copied - mov.w vects_size,r3 ! size of entries in vectab -1: - mov.l @r1+,r4 - mov.l r4,@r0 - add #4,r0 - add #1,r2 - cmp/hi r3,r2 - bf 1b - - mov.l vects_k,r0 ! update vbr to point to vectab - ldc r0,vbr - - ! call the mainline - mov #0,r4 ! argc - mov.l main_k,r0 - jsr @r0 - mov #0,r5 ! argv - - ! call exit - mov r0,r4 - mov.l exit_k,r0 - jsr @r0 - or r0,r0 - - END_CODE - - .align 2 -stack_k: - .long SYM(_ISR_Stack_area_end) -edata_k: - .long SYM(edata) -end_k: - .long SYM(end) -main_k: - .long SYM(boot_card) -exit_k: - .long SYM(exit) - -vects_k: - .long SYM(vectab) -vects_size: - .word 255 diff --git a/bsps/sh/gensh4/README.md b/bsps/sh/gensh4/README.md deleted file mode 100644 index 9258e77543..0000000000 --- a/bsps/sh/gensh4/README.md +++ /dev/null @@ -1,100 +0,0 @@ -gensh4 -====== - - Author: Alexandra Kossovsky - Victor Vengerov - OKTET Ltd, http://www.oktet.ru - - -``` -BSP NAME: generic SH4 (gensh4) -BOARD: n/a -BUS: n/a -CPU FAMILY: Hitachi SH -CPU: SH 7750 -COPROCESSORS: none -MODE: n/a - -DEBUG MONITOR: gdb (sh-ipl-g+ loader/stub) -``` - -PERIPHERALS ------------ -``` -TIMERS: on-chip -SERIAL PORTS: on-chip (with 2 ports) -REAL-TIME CLOCK: none -DMA: not used -VIDEO: none -SCSI: none -NETWORKING: none -``` - -DRIVER INFORMATION ------------------- -``` -CLOCK DRIVER: on-chip timer -IOSUPP DRIVER: default -SHMSUPP: n/a -TIMER DRIVER: on-chip timer -TTY DRIVER: /dev/console -``` - -STDIO ------ -``` -PORT: /dev/console -ELECTRICAL: n/a -BAUD: n/a -BITS PER CHARACTER: n/a -PARITY: n/a -STOP BITS: n/a -``` - -NOTES ------ -(1) Driver for the on-chip serial devices is tested only with 1st serial - port. We cannot test it on serial port with FIFO. - - Console driver has 4 modes -- 2 with termios (interrupt-driven & - poll-driven modes), one raw mode working with serial port directly, - without termios, and one mode working with gdb stub (using 'trapa' - handled by sh-ipl-g+). - -(2) The present 'hw_init.c' file provides 'early_hw_init'(void) which - is normally called from 'start.S' to provide such minimal HW setup. - It is written in C, but it should be noted that any accesses to memory - (except hardware registers) are prohibited until hardware not - initialized. To avoid access to stack, hw_init.c should be compiled with - -fomit-frame-pointer. - - hw_init.c also provides 'bsp_cache_on'(void) normally called from - 'start.S' after copying all data from rom to ram. - -(3) In 'configure.ac' you should properly set 'CPU_CLOCK_RATE_HZ'. - It is frequency fed to the CPU core (external clock frequency can be - multiplied by on-chip PLLs). Please note that it is not a frequency of - external oscillator! See Hardware Manual, section 10, for details. - Global variable 'SH4_CPU_HZ_Frequency' is declared in 'bsp.h' and - initilized in 'bspstart.c' to ${HZ}. It is used by sci driver, - which exists in 'libcpu/sh/sh7750'. - -(4) There is SH4_WITH_IPL macro in console driver 'sh4_uart.h'. - When it is defined, the application works under - gdb-stub (it is able to turn cache on by 'trapa', use gdb mode in console - driver and get out from gdb to use other console modes). - -(5) There are 3 likcmds: - - linkcmds: code and data loaded to RAM. No code/data moving required. - - linkcmds.rom: code executed from the ROM; .data section moved to the - RAM on initialization. - - linkcmds.rom2ram: execution started from the ROM (after reset); code - and data moved to the RAM and execution continued from RAM. - - The same 'start.S' is used for all cases. - -(6) You can get gdb stub from http://www.oktet.ru/download/sh4/sh-ipl.tar.gz. - It is based on 'sh-ipl-g+' package used in sh-linux project. - -(7) This project was done in cooperation with Transas company - http://www.transas.com diff --git a/bsps/sh/gensh4/btimer/btimer.c b/bsps/sh/gensh4/btimer/btimer.c deleted file mode 100644 index ef462c780c..0000000000 --- a/bsps/sh/gensh4/btimer/btimer.c +++ /dev/null @@ -1,269 +0,0 @@ -/** - * @file - * @brief Timer driver for the Hitachi SH 7750 - */ - -/* - * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include -#include - -#include -#include - -extern uint32_t bsp_clicks_per_second; - -#ifndef TIMER_PRIO -#define TIMER_PRIO 15 -#endif - -/* Timer prescaler division ratio */ -#define TIMER_PRESCALER 4 -#define TCR1_TPSC SH7750_TCR_TPSC_DIV4 - -#define TIMER_VECTOR SH7750_EVT_TO_NUM(SH7750_EVT_TUNI1) - -extern rtems_isr timerisr(void); - -static uint32_t Timer_interrupts; - -/* Counter should be divided to this value to obtain time in microseconds */ -static uint32_t microseconds_divider; - -/* Interrupt period in microseconds */ -static uint32_t microseconds_per_int; - -bool benchmark_timer_find_average_overhead; - -/* benchmark_timer_initialize -- - * Initialize Timer 1 to operate as a RTEMS benchmark timer: - * - determine timer clock frequency - * - install timer interrupt handler - * - configure the Timer 1 hardware - * - start the timer - * - * PARAMETERS: - * none - * - * RETURNS: - * none - */ -void -benchmark_timer_initialize(void) -{ - uint8_t temp8; - uint16_t temp16; - rtems_interrupt_level level; - rtems_isr *ignored; - int cpudiv = 1; - int tidiv = 1; - - Timer_interrupts = 0; - rtems_interrupt_disable(level); - - /* Get CPU frequency divider from clock unit */ - switch (read16(SH7750_FRQCR) & SH7750_FRQCR_IFC) - { - case SH7750_FRQCR_IFCDIV1: - cpudiv = 1; - break; - - case SH7750_FRQCR_IFCDIV2: - cpudiv = 2; - break; - - case SH7750_FRQCR_IFCDIV3: - cpudiv = 3; - break; - - case SH7750_FRQCR_IFCDIV4: - cpudiv = 4; - break; - - case SH7750_FRQCR_IFCDIV6: - cpudiv = 6; - break; - - case SH7750_FRQCR_IFCDIV8: - cpudiv = 8; - break; - - default: - rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); - } - - /* Get peripheral module frequency divider from clock unit */ - switch (read16(SH7750_FRQCR) & SH7750_FRQCR_PFC) - { - case SH7750_FRQCR_PFCDIV2: - tidiv = 2 * TIMER_PRESCALER; - break; - - case SH7750_FRQCR_PFCDIV3: - tidiv = 3 * TIMER_PRESCALER; - break; - - case SH7750_FRQCR_PFCDIV4: - tidiv = 4 * TIMER_PRESCALER; - break; - - case SH7750_FRQCR_PFCDIV6: - tidiv = 6 * TIMER_PRESCALER; - break; - - case SH7750_FRQCR_PFCDIV8: - tidiv = 8 * TIMER_PRESCALER; - break; - - default: - rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); - } - - microseconds_divider = bsp_clicks_per_second * cpudiv / (tidiv * 1000000); - microseconds_per_int = 0xFFFFFFFF / microseconds_divider; - - /* - * Hardware specific initialization - */ - - /* Stop the Timer 0 */ - temp8 = read8(SH7750_TSTR); - temp8 &= ~SH7750_TSTR_STR1; - write8(temp8, SH7750_TSTR); - - /* Establish interrupt handler */ - _CPU_ISR_install_raw_handler( TIMER_VECTOR, timerisr, &ignored ); - - /* Reset timer constant and counter */ - write32(0xFFFFFFFF, SH7750_TCOR1); - write32(0xFFFFFFFF, SH7750_TCNT1); - - /* Select timer mode */ - write16( - SH7750_TCR_UNIE | /* Enable Underflow Interrupt */ - SH7750_TCR_CKEG_RAISE | /* Count on rising edge */ - TCR1_TPSC, /* Timer prescaler ratio */ - SH7750_TCR1); - - /* Set timer interrupt priority */ - temp16 = read16(SH7750_IPRA); - temp16 = (temp16 & ~SH7750_IPRA_TMU1) | (TIMER_PRIO << SH7750_IPRA_TMU1_S); - write16(temp16, SH7750_IPRA); - - - rtems_interrupt_enable(level); - - /* Start the Timer 1 */ - temp8 = read8(SH7750_TSTR); - temp8 |= SH7750_TSTR_STR1; - write8(temp8, SH7750_TSTR); - -} - -/* - * The following controls the behavior of benchmark_timer_read(). - * - * AVG_OVERHEAD is the overhead for starting and stopping the timer. It - * is usually deducted from the number returned. - * - * LEAST_VALID is the lowest number this routine should trust. Numbers - * below this are "noise" and zero is returned. - */ - -#define AVG_OVERHEAD 0 /* It typically takes X.X microseconds */ - /* (Y countdowns) to start/stop the timer. */ - /* This value is in microseconds. */ -#define LEAST_VALID 0 /* 20 */ /* Don't trust a clicks value lower than this */ - -/* benchmark_timer_read -- - * Read timer value in microsecond units since timer start. - * - * PARAMETERS: - * none - * - * RETURNS: - * number of microseconds since timer has been started - */ -benchmark_timer_t -benchmark_timer_read(void) -{ - uint32_t clicks; - uint32_t ints; - uint32_t total; - rtems_interrupt_level level; - uint32_t tcr; - - - rtems_interrupt_disable(level); - - clicks = 0xFFFFFFFF - read32(SH7750_TCNT1); - tcr = read32(SH7750_TCR1); - ints = Timer_interrupts; - - rtems_interrupt_enable(level); - - /* Handle the case when timer overflowed but interrupt was not processed */ - if ((clicks > 0xFF000000) && ((tcr & SH7750_TCR_UNF) != 0)) - { - ints++; - } - - total = microseconds_per_int * ints + (clicks / microseconds_divider); - - if ( benchmark_timer_find_average_overhead ) - return total; /* in microsecond units */ - else - { - if ( total < LEAST_VALID ) - return 0; /* below timer resolution */ - /* - * Somehow convert total into microseconds - */ - return (total - AVG_OVERHEAD) ; - } -} - -/* benchmark_timer_disable_subtracting_average_overhead -- - * This routine is invoked by the "Check Timer" (tmck) test in the - * RTEMS Timing Test Suite. It makes the benchmark_timer_read routine not - * subtract the overhead required to initialize and read the benchmark - * timer. - * - * PARAMETERS: - * find_flag - boolean flag, true if overhead must not be subtracted. - * - * RETURNS: - * none - */ -void -benchmark_timer_disable_subtracting_average_overhead(bool find_flag) -{ - benchmark_timer_find_average_overhead = find_flag; -} - -/* timerisr -- - * Timer interrupt handler routine. This function invoked on timer - * underflow event; once per 2^32 clocks. It should reset the timer - * event and increment timer interrupts counter. - */ -void -timerisr(void) -{ - uint8_t temp8; - - /* reset the flags of the status register */ - temp8 = read8(SH7750_TCR1) & ~SH7750_TCR_UNF; - write8(temp8, SH7750_TCR1); - - Timer_interrupts += 1; -} diff --git a/bsps/sh/gensh4/clock/ckinit.c b/bsps/sh/gensh4/clock/ckinit.c deleted file mode 100644 index 7e2b88acdb..0000000000 --- a/bsps/sh/gensh4/clock/ckinit.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - * This file contains the generic RTEMS clock driver the Hitachi SH 7750 - */ - -/* - * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov - * - * COPYRIGHT (c) 2001 - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include - -#include - -#include -#include -#include -#include -#include - -static void Clock_exit( void ); - -extern uint32_t bsp_clicks_per_second; - -#ifndef CLOCKPRIO -#define CLOCKPRIO 10 -#endif - -/* Clock timer prescaler division ratio */ -#define CLOCK_PRESCALER 4 -#define TCR0_TPSC SH7750_TCR_TPSC_DIV4 - -/* - * The interrupt vector number associated with the clock tick device - * driver. - */ -#define CLOCK_VECTOR SH7750_EVT_TO_NUM(SH7750_EVT_TUNI0) - -/* - * Clock_driver_ticks is a monotonically increasing counter of the - * number of clock ticks since the driver was initialized. - */ -volatile uint32_t Clock_driver_ticks; - -static rtems_isr Clock_isr( rtems_vector_number vector ); - -/* - * The previous ISR on this clock tick interrupt vector. - */ -rtems_isr_entry Old_ticker; - -/* - * Isr Handler - */ - -/* - * Clock_isr - * - * Clock interrupt handling routine. - */ -static rtems_isr Clock_isr(rtems_vector_number vector) -{ - uint16_t tcr; - - /* reset the timer underflow flag */ - tcr = read16(SH7750_TCR0); - write16(tcr & ~SH7750_TCR_UNF, SH7750_TCR0); - - /* Increment the clock interrupt counter */ - Clock_driver_ticks++ ; - - /* Invoke rtems clock service routine */ - rtems_clock_tick(); -} - -/* - * Install_clock - * - * Install a clock tick handler and reprograms the chip. This - * is used to initially establish the clock tick. - * - * SIDE EFFECTS: - * Establish clock interrupt handler, configure Timer 0 hardware - */ -static void Install_clock(rtems_isr_entry clock_isr) -{ - int cpudiv = 1; /* CPU frequency divider */ - int tidiv = 1; /* Timer input frequency divider */ - uint32_t timer_divider; /* Calculated Timer Divider value */ - uint8_t temp8; - uint16_t temp16; - - /* - * Initialize the clock tick device driver variables - */ - - Clock_driver_ticks = 0; - - /* Get CPU frequency divider from clock unit */ - switch (read16(SH7750_FRQCR) & SH7750_FRQCR_IFC) { - case SH7750_FRQCR_IFCDIV1: - cpudiv = 1; - break; - - case SH7750_FRQCR_IFCDIV2: - cpudiv = 2; - break; - - case SH7750_FRQCR_IFCDIV3: - cpudiv = 3; - break; - - case SH7750_FRQCR_IFCDIV4: - cpudiv = 4; - break; - - case SH7750_FRQCR_IFCDIV6: - cpudiv = 6; - break; - - case SH7750_FRQCR_IFCDIV8: - cpudiv = 8; - break; - - default: - rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); - } - - /* Get peripheral module frequency divider from clock unit */ - switch (read16(SH7750_FRQCR) & SH7750_FRQCR_PFC) { - case SH7750_FRQCR_PFCDIV2: - tidiv = 2 * CLOCK_PRESCALER; - break; - - case SH7750_FRQCR_PFCDIV3: - tidiv = 3 * CLOCK_PRESCALER; - break; - - case SH7750_FRQCR_PFCDIV4: - tidiv = 4 * CLOCK_PRESCALER; - break; - - case SH7750_FRQCR_PFCDIV6: - tidiv = 6 * CLOCK_PRESCALER; - break; - - case SH7750_FRQCR_PFCDIV8: - tidiv = 8 * CLOCK_PRESCALER; - break; - - default: - rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); - } - timer_divider = - (bsp_clicks_per_second * cpudiv / (tidiv*1000000)) * - rtems_configuration_get_microseconds_per_tick(); - - /* - * Hardware specific initialization - */ - - /* Stop the Timer 0 */ - temp8 = read8(SH7750_TSTR); - temp8 &= ~SH7750_TSTR_STR0; - write8(temp8, SH7750_TSTR); - - /* Establish interrupt handler */ - rtems_interrupt_catch( Clock_isr, CLOCK_VECTOR, &Old_ticker ); - - /* Reset counter */ - write32(timer_divider, SH7750_TCNT0); - - /* Load divider */ - write32(timer_divider, SH7750_TCOR0); - - write16( - SH7750_TCR_UNIE | /* Enable Underflow Interrupt */ - SH7750_TCR_CKEG_RAISE | /* Count on rising edge */ - TCR0_TPSC, /* Timer prescaler ratio */ - SH7750_TCR0); - - /* Set clock interrupt priority */ - temp16 = read16(SH7750_IPRA); - temp16 = (temp16 & ~SH7750_IPRA_TMU0) | (CLOCKPRIO << SH7750_IPRA_TMU0_S); - write16(temp16, SH7750_IPRA); - - /* Start the Timer 0 */ - temp8 = read8(SH7750_TSTR); - temp8 |= SH7750_TSTR_STR0; - write8(temp8, SH7750_TSTR); - - /* - * Schedule the clock cleanup routine to execute if the application exits. - */ - atexit( Clock_exit ); -} - -/* - * Clock_exit - * - * Clean up before the application exits - * - * SIDE EFFECTS: - * Stop Timer 0 counting, set timer 0 interrupt priority level to 0. - */ -void -Clock_exit(void) -{ - uint8_t temp8 = 0; - uint16_t temp16 = 0; - - /* turn off the timer interrupts */ - /* Stop the Timer 0 */ - temp8 = read8(SH7750_TSTR); - temp8 &= ~SH7750_TSTR_STR0; - write8(temp8, SH7750_TSTR); - - /* Lower timer interrupt priority to 0 */ - temp16 = read16(SH7750_IPRA); - temp16 = (temp16 & ~SH7750_IPRA_TMU0) | (0 << SH7750_IPRA_TMU0_S); - write16(temp16, SH7750_IPRA); - - /* old vector shall not be installed */ -} - -void _Clock_Initialize( void ) -{ - Install_clock( Clock_isr ); -} diff --git a/bsps/sh/gensh4/config/gensh4.cfg b/bsps/sh/gensh4/config/gensh4.cfg deleted file mode 100644 index 016262f11e..0000000000 --- a/bsps/sh/gensh4/config/gensh4.cfg +++ /dev/null @@ -1,28 +0,0 @@ -# -# gensh4.cfg -# -# default configuration for Hitachi SH7750 board -# -# Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia -# Author: Victor V. Vengerov - -include $(RTEMS_ROOT)/make/custom/default.cfg - -RTEMS_CPU=sh - -# This contains the compiler options necessary to select the CPU model -# and (hopefully) optimize for it. -# -# Seems to be good without initialisation FPSCR. -# Also works with SH4_FPSCR_DN bit set. -#CPU_CFLAGS = -m4-single-only -mfmovd -ml -#CPU_CFLAGS = -m4-single -ml -# -# It works with SH4_FPSCR_PR bit set -CPU_CFLAGS = -m4 -ml - -# optimize flag: typically -O2 -CFLAGS_OPTIMIZE_V = -O2 -g -CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections - -LDFLAGS = -Wl,--gc-sections diff --git a/bsps/sh/gensh4/console/console.c b/bsps/sh/gensh4/console/console.c deleted file mode 100644 index 02c43786d5..0000000000 --- a/bsps/sh/gensh4/console/console.c +++ /dev/null @@ -1,469 +0,0 @@ -/* - * Console driver for SH-4 UART modules - * - * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia - * Author: Alexandra Kossovsky - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include - -#include -#include -#include - -#include "sh/sh4uart.h" - -/* Descriptor structures for two on-chip UART channels */ -sh4uart sh4_uarts[2]; - -/* Console operations mode: - * 0 - raw (non-termios) polled input/output - * 1 - termios-based polled input/output - * 2 - termios-based interrupt-driven input/output - * 3 - non-termios over gdb stub - */ -int console_mode = 3; -#define CONSOLE_MODE_RAW (0) -#define CONSOLE_MODE_POLL (1) -#define CONSOLE_MODE_INT (2) -#define CONSOLE_MODE_IPL (3) - -/* Wrapper functions for SH-4 UART generic driver */ - -/* console_poll_read -- - * wrapper for poll read function - * - * PARAMETERS: - * minor - minor device number - * - * RETURNS: - * character code readed from UART, or -1 if there is no characters - * available - */ -static int -console_poll_read(int minor) -{ - return sh4uart_poll_read(&sh4_uarts[minor]); -} - -/* console_interrupt_write -- - * wrapper for interrupt write function - * - * PARAMETERS: - * minor - minor device number - * buf - output buffer - * len - output buffer length - * - * RETURNS: - * result code - */ -static ssize_t -console_interrupt_write(int minor, const char *buf, size_t len) -{ - return sh4uart_interrupt_write(&sh4_uarts[minor], buf, len); -} - -/* console_poll_write -- - * wrapper for polling mode write function - * - * PARAMETERS: - * minor - minor device number - * buf - output buffer - * len - output buffer length - * - * RETURNS: - * result code - */ -static ssize_t -console_poll_write(int minor, const char *buf, size_t len) -{ - return sh4uart_poll_write(&sh4_uarts[minor], buf, len); -} - -/* console_set_attributes -- - * wrapper for hardware-dependent termios attributes setting - * - * PARAMETERS: - * minor - minor device number - * t - pointer to the termios structure - * - * RETURNS: - * result code - */ -static int -console_set_attributes(int minor, const struct termios *t) -{ - return sh4uart_set_attributes(&sh4_uarts[minor], t); -} - -/* console_stop_remote_tx -- - * wrapper for stopping data flow from remote party. - * - * PARAMETERS: - * minor - minor device number - * - * RETURNS: - * result code - */ -static int -console_stop_remote_tx(int minor) -{ - if (minor < sizeof(sh4_uarts)/sizeof(sh4_uarts[0])) - return sh4uart_stop_remote_tx(&sh4_uarts[minor]); - else - return RTEMS_INVALID_NUMBER; -} - -/* console_start_remote_tx -- - * wrapper for resuming data flow from remote party. - * - * PARAMETERS: - * minor - minor device number - * - */ -static int -console_start_remote_tx(int minor) -{ - if (minor < sizeof(sh4_uarts)/sizeof(sh4_uarts[0])) - return sh4uart_start_remote_tx(&sh4_uarts[minor]); - else - return RTEMS_INVALID_NUMBER; -} - -/* console_first_open -- - * wrapper for UART controller initialization functions - * - * PARAMETERS: - * major - major device number - * minor - minor device number - * arg - libio device open argument - * - * RETURNS: - * error code - */ -static int -console_first_open(int major, int minor, void *arg) -{ - rtems_libio_open_close_args_t *args = arg; - rtems_status_code sc; - - sc = sh4uart_init(&sh4_uarts[minor], /* uart */ - args->iop->data1, /* tty */ - minor+1, /* channel */ - (console_mode == CONSOLE_MODE_INT)); - - if (sc == RTEMS_SUCCESSFUL) - sc = sh4uart_reset(&sh4_uarts[minor]); - - return sc; -} - -/* console_last_close -- - * wrapper for UART controller close function - * - * PARAMETERS: - * major - major device number - * minor - minor device number - * arg - libio device close argument - * - * RETURNS: - * error code - */ -static int -console_last_close(int major, int minor, void *arg) -{ - if (console_mode != CONSOLE_MODE_IPL) - /* working from gdb we should not disable port operations */ - return sh4uart_disable(&sh4_uarts[minor], - !(boot_mode == SH4_BOOT_MODE_IPL)); - else - return RTEMS_SUCCESSFUL; -} - -/* console_initialize -- - * This routine initializes the console IO drivers and register devices - * in RTEMS I/O system. - * - * PARAMETERS: - * major - major console device number - * minor - minor console device number (not used) - * arg - device initialize argument - * - * RETURNS: - * RTEMS error code (RTEMS_SUCCESSFUL if device initialized successfuly) - */ -rtems_device_driver -console_initialize(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) -{ - rtems_status_code status; - -#ifdef SH4_WITH_IPL - /* booting from flash we cannot have IPL console */ - if (boot_mode != SH4_BOOT_MODE_IPL && console_mode == CONSOLE_MODE_IPL) - console_mode = CONSOLE_MODE_INT; - - /* break out from gdb if neccessary */ - if (boot_mode == SH4_BOOT_MODE_IPL && console_mode != CONSOLE_MODE_IPL) - ipl_finish(); -#endif - - /* - * Set up TERMIOS - */ - if ((console_mode != CONSOLE_MODE_RAW) && - (console_mode != CONSOLE_MODE_IPL)) - rtems_termios_initialize (); - - /* - * Register the devices - */ - status = rtems_io_register_name ("/dev/console", major, 0); - if (status != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred (status); - - status = rtems_io_register_name ("/dev/aux", major, 1); - if (status != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred (status); - - if (console_mode == CONSOLE_MODE_RAW) - { - rtems_status_code sc; - sc = sh4uart_init(&sh4_uarts[0], /* uart */ - NULL, /* tty */ - 1, /* UART channel number */ - 0); /* Poll-mode */ - - if (sc == RTEMS_SUCCESSFUL) - sc = sh4uart_reset(&sh4_uarts[0]); - - sc = sh4uart_init(&sh4_uarts[1], /* uart */ - NULL, /* tty */ - 2, /* UART channel number */ - 0); /* Poll-mode */ - - if (sc == RTEMS_SUCCESSFUL) - sc = sh4uart_reset(&sh4_uarts[1]); - - return sc; - } - - return RTEMS_SUCCESSFUL; -} - -/* console_open -- - * Open console device driver. Pass appropriate termios callback - * functions to termios library. - * - * PARAMETERS: - * major - major device number for console devices - * minor - minor device number for console - * arg - device opening argument - * - * RETURNS: - * RTEMS error code - */ -rtems_device_driver -console_open(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) -{ - static const rtems_termios_callbacks intr_callbacks = { - console_first_open, /* firstOpen */ - console_last_close, /* lastClose */ - NULL, /* pollRead */ - console_interrupt_write, /* write */ - console_set_attributes, /* setAttributes */ - console_stop_remote_tx, /* stopRemoteTx */ - console_start_remote_tx, /* startRemoteTx */ - TERMIOS_IRQ_DRIVEN /* outputUsesInterrupts */ - }; - static const rtems_termios_callbacks poll_callbacks = { - console_first_open, /* firstOpen */ - console_last_close, /* lastClose */ - console_poll_read, /* pollRead */ - console_poll_write, /* write */ - console_set_attributes, /* setAttributes */ - console_stop_remote_tx, /* stopRemoteTx */ - console_start_remote_tx, /* startRemoteTx */ - TERMIOS_POLLED /* outputUsesInterrupts */ - }; - - switch (console_mode) - { - case CONSOLE_MODE_RAW: - case CONSOLE_MODE_IPL: - return RTEMS_SUCCESSFUL; - - case CONSOLE_MODE_INT: - return rtems_termios_open(major, minor, arg, &intr_callbacks); - - case CONSOLE_MODE_POLL: - return rtems_termios_open(major, minor, arg, &poll_callbacks); - - default: - rtems_fatal_error_occurred(0xC07A1310); - } - - return RTEMS_INTERNAL_ERROR; -} - -/* console_close -- - * Close console device. - * - * PARAMETERS: - * major - major device number for console devices - * minor - minor device number for console - * arg - device close argument - * - * RETURNS: - * RTEMS error code - */ -rtems_device_driver -console_close(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) -{ - if ((console_mode != CONSOLE_MODE_RAW) && - (console_mode != CONSOLE_MODE_IPL)) - return rtems_termios_close (arg); - else - return RTEMS_SUCCESSFUL; -} - -/* console_read -- - * Read from the console device - * - * PARAMETERS: - * major - major device number for console devices - * minor - minor device number for console - * arg - device read argument - * - * RETURNS: - * RTEMS error code - */ -rtems_device_driver -console_read(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) -{ - if ((console_mode != CONSOLE_MODE_RAW) && - (console_mode != CONSOLE_MODE_IPL)) - { - return rtems_termios_read (arg); - } - else - { - rtems_libio_rw_args_t *argp = arg; - char *buf = argp->buffer; - int count = argp->count; - int n = 0; - int c; - while (n < count) - { - do { - c = (console_mode == CONSOLE_MODE_RAW) ? - sh4uart_poll_read(&sh4_uarts[minor]) : - ipl_console_poll_read(minor); - } while (c == -1); - if (c == '\r') - c = '\n'; - *(buf++) = c; - n++; - if (c == '\n') - break; - } - argp->bytes_moved = n; - return RTEMS_SUCCESSFUL; - } -} - -/* console_write -- - * Write to the console device - * - * PARAMETERS: - * major - major device number for console devices - * minor - minor device number for console - * arg - device write argument - * - * RETURNS: - * RTEMS error code - */ -rtems_device_driver -console_write(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) -{ - switch (console_mode) - { - case CONSOLE_MODE_POLL: - case CONSOLE_MODE_INT: - return rtems_termios_write (arg); - case CONSOLE_MODE_RAW: - { - rtems_libio_rw_args_t *argp = arg; - char cr = '\r'; - char *buf = argp->buffer; - int count = argp->count; - int i; - - for (i = 0; i < count; i++) - { - if (*buf == '\n') - sh4uart_poll_write(&sh4_uarts[minor], &cr, 1); - sh4uart_poll_write(&sh4_uarts[minor], buf, 1); - buf++; - } - argp->bytes_moved = count; - return RTEMS_SUCCESSFUL; - } -#ifdef SH4_WITH_IPL - case CONSOLE_MODE_IPL: - { - rtems_libio_rw_args_t *argp = arg; - char *buf = argp->buffer; - int count = argp->count; - ipl_console_poll_write(minor, buf, count); - argp->bytes_moved = count; - return RTEMS_SUCCESSFUL; - } -#endif - default: /* Unreachable */ - return RTEMS_NOT_DEFINED; - } -} - -/* console_control -- - * Handle console device I/O control (IOCTL) - * - * PARAMETERS: - * major - major device number for console devices - * minor - minor device number for console - * arg - device ioctl argument - * - * RETURNS: - * RTEMS error code - */ -rtems_device_driver -console_control(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) -{ - if ((console_mode != CONSOLE_MODE_RAW) && - (console_mode != CONSOLE_MODE_IPL)) - { - return rtems_termios_ioctl (arg); - } - else - { - return RTEMS_SUCCESSFUL; - } -} diff --git a/bsps/sh/gensh4/console/sh4uart.c b/bsps/sh/gensh4/console/sh4uart.c deleted file mode 100644 index 7acc1de337..0000000000 --- a/bsps/sh/gensh4/console/sh4uart.c +++ /dev/null @@ -1,910 +0,0 @@ -/* - * Generic UART Serial driver for SH-4 processors - * - * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russian Fed. - * Author: Alexandra Kossovsky - * - * COPYRIGHT (c) 1989-2000. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#include -#include -#include -#include -#include "sh/sh4uart.h" - -#ifndef SH4_UART_INTERRUPT_LEVEL -#define SH4_UART_INTERRUPT_LEVEL 4 -#endif - -/* Forward function declarations */ -static rtems_isr -sh4uart1_interrupt_transmit(rtems_vector_number vec); -static rtems_isr -sh4uart1_interrupt_receive(rtems_vector_number vec); -static rtems_isr -sh4uart2_interrupt_transmit(rtems_vector_number vec); -static rtems_isr -sh4uart2_interrupt_receive(rtems_vector_number vec); - -/* - * sh4uart_init -- - * This function verifies the input parameters and perform initialization - * of the SH-4 on-chip UART descriptor structure. - * - * PARAMETERS: - * uart - pointer to the UART channel descriptor structure - * tty - pointer to termios structure - * chn - channel number (SH4_SCI/SH4_SCIF -- 1/2) - * int_driven - interrupt-driven (1) or polled (0) I/O mode - * - * RETURNS: - * RTEMS_SUCCESSFUL if all parameters are valid, or error code - */ -rtems_status_code -sh4uart_init(sh4uart *uart, void *tty, int chn, int int_driven) -{ - if (uart == NULL) - return RTEMS_INVALID_ADDRESS; - - if ((chn != SH4_SCI) && (chn != SH4_SCIF)) - return RTEMS_INVALID_NUMBER; - - uart->chn = chn; - uart->tty = tty; - uart->int_driven = int_driven; - -#if 0 - sh4uart_poll_write(uart, "init", 4); -#endif - return RTEMS_SUCCESSFUL; -} - -/* - * sh4uart_get_Pph -- - * Get current peripheral module clock. - * - * PARAMETERS: none; - * Cpu clock is get from CPU_CLOCK_RATE_HZ marco - * (defined in bspopts.h, included from bsp.h) - * - * RETURNS: - * peripheral module clock in Hz. - */ -static uint32_t -sh4uart_get_Pph(void) -{ - uint16_t frqcr = *(volatile uint16_t*)SH7750_FRQCR; - uint32_t Pph = CPU_CLOCK_RATE_HZ; - - switch (frqcr & SH7750_FRQCR_IFC) { - case SH7750_FRQCR_IFCDIV1: break; - case SH7750_FRQCR_IFCDIV2: Pph *= 2; break; - case SH7750_FRQCR_IFCDIV3: Pph *= 3; break; - case SH7750_FRQCR_IFCDIV4: Pph *= 4; break; - case SH7750_FRQCR_IFCDIV6: Pph *= 6; break; - case SH7750_FRQCR_IFCDIV8: Pph *= 8; break; - default: /* unreachable */ - break; - } - - switch (frqcr & SH7750_FRQCR_PFC) { - case SH7750_FRQCR_PFCDIV2: Pph /= 2; break; - case SH7750_FRQCR_PFCDIV3: Pph /= 3; break; - case SH7750_FRQCR_PFCDIV4: Pph /= 4; break; - case SH7750_FRQCR_PFCDIV6: Pph /= 6; break; - case SH7750_FRQCR_PFCDIV8: Pph /= 8; break; - default: /* unreachable */ - break; - } - - return Pph; -} - -/* - * sh4uart_set_baudrate -- - * Program the UART timer to specified baudrate - * - * PARAMETERS: - * uart - pointer to UART descriptor structure - * baud - termios baud rate (B50, B9600, etc...) - * - * ALGORITHM: - * see SH7750 Hardware Manual. - * - * RETURNS: - * none - */ -static void -sh4uart_set_baudrate(sh4uart *uart, speed_t baud) -{ - uint32_t rate; - int16_t div; - int n; - uint32_t Pph = sh4uart_get_Pph(); - - switch (baud) { - case B50: rate = 50; break; - case B75: rate = 75; break; - case B110: rate = 110; break; - case B134: rate = 134; break; - case B150: rate = 150; break; - case B200: rate = 200; break; - case B300: rate = 300; break; - case B600: rate = 600; break; - case B1200: rate = 1200; break; - case B2400: rate = 2400; break; - case B4800: rate = 4800; break; - case B9600: rate = 9600; break; - case B19200: rate = 19200; break; - case B38400: rate = 38400; break; - case B57600: rate = 57600; break; -#ifdef B115200 - case B115200: rate = 115200; break; -#endif -#ifdef B230400 - case B230400: rate = 230400; break; -#endif - default: rate = 9600; break; - } - - for (n = 0; n < 4; n++) { - div = Pph / (32 * (1 << (2 * n)) * rate) - 1; - if (div < 0x100) - break; - } - - /* Set default baudrate if specified baudrate is impossible */ - if (n >= 4) - sh4uart_set_baudrate(uart, B9600); - - if ( uart->chn == 1 ) { - volatile uint8_t *smr1 = (volatile uint8_t *)SH7750_SCSMR1; - *smr1 &= ~SH7750_SCSMR_CKS; - *smr1 |= n << SH7750_SCSMR_CKS_S; - } else { - volatile uint16_t *smr2 = (volatile uint16_t *)SH7750_SCSMR2; - *smr2 &= ~SH7750_SCSMR_CKS; - *smr2 |= n << SH7750_SCSMR_CKS_S; - } - - SCBRR(uart->chn) = div; - /* Wait at least 1 bit interwal */ - rtems_task_wake_after(RTEMS_MILLISECONDS_TO_TICKS(1000 / rate)); -} - -/* - * sh4uart_reset -- - * This function perform the hardware initialization of SH-4 - * on-chip UART controller using parameters - * filled by the sh4uart_init function. - * - * PARAMETERS: - * uart - pointer to UART channel descriptor structure - * - * RETURNS: - * RTEMS_SUCCESSFUL if channel is initialized successfully, error - * code in other case - */ -rtems_status_code -sh4uart_reset(sh4uart *uart) -{ - register int chn; - register int int_driven; - rtems_status_code rc; - uint16_t tmp; - - if (uart == NULL) - return RTEMS_INVALID_ADDRESS; - - chn = uart->chn; - int_driven = uart->int_driven; - - if ( chn == 1 ) { - volatile uint8_t *scr1 = (volatile uint8_t *)SH7750_SCSCR1; - volatile uint8_t *smr1 = (volatile uint8_t *)SH7750_SCSMR1; - *scr1 = 0x0; /* Is set properly at the end of this function */ - *smr1 = 0x0; /* 8-bit, non-parity, 1 stop bit, pf/1 clock */ - } else { - volatile uint16_t *scr2 = (volatile uint16_t *)SH7750_SCSCR2; - volatile uint16_t *smr2 = (volatile uint16_t *)SH7750_SCSMR2; - *scr2 = 0x0; /* Is set properly at the end of this function */ - *smr2 = 0x0; /* 8-bit, non-parity, 1 stop bit, pf/1 clock */ - } - - if (chn == SH4_SCIF) - SCFCR2 = SH7750_SCFCR2_TFRST | SH7750_SCFCR2_RFRST | - SH7750_SCFCR2_RTRG_1 | SH7750_SCFCR2_TTRG_4; - - if (chn == SH4_SCI) - SCSPTR1 = int_driven ? 0x0 : SH7750_SCSPTR1_EIO; - else - SCSPTR2 = SH7750_SCSPTR2_RTSDT; - - if (int_driven) { - uint16_t ipr; - - if (chn == SH4_SCI) { - ipr = IPRB; - ipr &= ~SH7750_IPRB_SCI1; - ipr |= SH4_UART_INTERRUPT_LEVEL << SH7750_IPRB_SCI1_S; - IPRB = ipr; - - rc = rtems_interrupt_catch(sh4uart1_interrupt_transmit, - SH7750_EVT_TO_NUM(SH7750_EVT_SCI_TXI), - &uart->old_handler_transmit); - if (rc != RTEMS_SUCCESSFUL) - return rc; - - rc = rtems_interrupt_catch(sh4uart1_interrupt_receive, - SH7750_EVT_TO_NUM(SH7750_EVT_SCI_RXI), - &uart->old_handler_receive); - if (rc != RTEMS_SUCCESSFUL) - return rc; - } else { - ipr = IPRC; - ipr &= ~SH7750_IPRC_SCIF; - ipr |= SH4_UART_INTERRUPT_LEVEL << SH7750_IPRC_SCIF_S; - IPRC = ipr; - - rc = rtems_interrupt_catch(sh4uart2_interrupt_transmit, - SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_TXI), - &uart->old_handler_transmit); - if (rc != RTEMS_SUCCESSFUL) - return rc; - rc = rtems_interrupt_catch(sh4uart2_interrupt_receive, - SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_RXI), - &uart->old_handler_receive); - if (rc != RTEMS_SUCCESSFUL) - return rc; - } - uart->tx_buf = NULL; - uart->tx_ptr = uart->tx_buf_len = 0; - } - - sh4uart_set_baudrate(uart, B38400); /* debug defaults (unfortunately, - it is differ to termios default */ - - tmp = SH7750_SCSCR_TE | SH7750_SCSCR_RE | - (chn == SH4_SCI ? 0x0 : SH7750_SCSCR2_REIE) | - (int_driven ? (SH7750_SCSCR_RIE | SH7750_SCSCR_TIE) : 0x0); - - if ( chn == 1 ) { - volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1; - *scr = tmp; - } else { - volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2; - *scr = tmp; - } - - return RTEMS_SUCCESSFUL; -} - -/* - * sh4uart_disable -- - * This function disable the operations on SH-4 UART controller - * - * PARAMETERS: - * uart - pointer to UART channel descriptor structure - * disable_port - disable receive and transmit on the port - * - * RETURNS: - * RTEMS_SUCCESSFUL if UART closed successfuly, or error code in - * other case - */ -rtems_status_code -sh4uart_disable(sh4uart *uart, int disable_port) -{ - rtems_status_code rc; - - if (disable_port) { - if ( uart->chn == 1 ) { - volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1; - *scr &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE); - } else { - volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2; - *scr &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE); - } - } - - if (uart->int_driven) { - rc = rtems_interrupt_catch(uart->old_handler_transmit, - uart->chn == SH4_SCI ? SH7750_EVT_SCI_TXI : SH7750_EVT_SCIF_TXI, - NULL); - if (rc != RTEMS_SUCCESSFUL) - return rc; - rc = rtems_interrupt_catch(uart->old_handler_receive, - uart->chn == SH4_SCI ? SH7750_EVT_SCI_RXI : SH7750_EVT_SCIF_RXI, - NULL); - if (rc != RTEMS_SUCCESSFUL) - return rc; - } - - return RTEMS_SUCCESSFUL; -} - -/* - * sh4uart_set_attributes -- - * This function parse the termios attributes structure and perform - * the appropriate settings in hardware. - * - * PARAMETERS: - * uart - pointer to the UART descriptor structure - * t - pointer to termios parameters - * - * RETURNS: - * RTEMS_SUCCESSFUL - */ -rtems_status_code -sh4uart_set_attributes(sh4uart *uart, const struct termios *t) -{ - int level; - speed_t baud; - uint16_t smr; - - smr = (uint16_t)(*(uint8_t*)SH7750_SCSMR(uart->chn)); - - baud = cfgetospeed(t); - - /* Set flow control XXX*/ - if ((t->c_cflag & CRTSCTS) != 0) { - } - - /* Set character size -- only 7 or 8 bit */ - switch (t->c_cflag & CSIZE) { - case CS5: - case CS6: - case CS7: smr |= SH7750_SCSMR_CHR_7; break; - case CS8: smr &= ~SH7750_SCSMR_CHR_7; break; - } - - /* Set number of stop bits */ - if ((t->c_cflag & CSTOPB) != 0) - smr |= SH7750_SCSMR_STOP_2; - else - smr &= ~SH7750_SCSMR_STOP_2; - - /* Set parity mode */ - if ((t->c_cflag & PARENB) != 0) { - smr |= SH7750_SCSMR_PE; - if ((t->c_cflag & PARODD) != 0) - smr |= SH7750_SCSMR_PM_ODD; - else - smr &= ~SH7750_SCSMR_PM_ODD; - } else - smr &= ~SH7750_SCSMR_PE; - - rtems_interrupt_disable(level); - /* wait untill all data is transmitted */ - /* XXX JOEL says this is broken -- interrupts are OFF so NO ticks */ - rtems_task_wake_after(RTEMS_MILLISECONDS_TO_TICKS(100)); - - if ( uart->chn == 1 ) { - volatile uint8_t *scrP = (volatile uint8_t *)SH7750_SCSCR1; - volatile uint8_t *smrP = (volatile uint8_t *)SH7750_SCSMR1; - - *scrP &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE); /* disable operations */ - sh4uart_set_baudrate(uart, baud); - *smrP = (uint8_t)smr; - *scrP |= SH7750_SCSCR_TE | SH7750_SCSCR_RE; /* enable operations */ - } else { - volatile uint16_t *scrP = (volatile uint16_t *)SH7750_SCSCR2; - volatile uint16_t *smrP = (volatile uint16_t *)SH7750_SCSMR2; - - *scrP &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE); /* disable operations */ - sh4uart_set_baudrate(uart, baud); - *smrP = (uint8_t)smr; - *scrP |= SH7750_SCSCR_TE | SH7750_SCSCR_RE; /* enable operations */ - } - - rtems_interrupt_enable(level); - - return RTEMS_SUCCESSFUL; -} - -/* - * sh4uart_handle_error -- - * Perfoms error (Overrun, Framing & Parity) handling - * - * PARAMETERS: - * uart - pointer to UART descriptor structure - * - * RETURNS: - * nothing - */ -static void -sh4uart_handle_error(sh4uart *uart) -{ - if (uart->chn == SH4_SCI) { - volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1; - *scr &= ~(SH7750_SCSSR1_ORER | SH7750_SCSSR1_FER | SH7750_SCSSR1_PER); - } else { - volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2; - *scr &= ~(SH7750_SCSSR2_ER | SH7750_SCSSR2_BRK | SH7750_SCSSR2_FER); - *scr &= ~(SH7750_SCLSR2_ORER); - } -} - -/* - * sh4uart_poll_read -- - * This function tried to read character from SH-4 UART and perform - * error handling. When parity or framing error occured, return - * value dependent on termios input mode flags: - * - received character, if IGNPAR == 1 - * - 0, if IGNPAR == 0 and PARMRK == 0 - * - 0xff and 0x00 on next poll_read invocation, if IGNPAR == 0 and - * PARMRK == 1 - * - * PARAMETERS: - * uart - pointer to UART descriptor structure - * - * RETURNS: - * code of received character or -1 if no characters received. - */ -int -sh4uart_poll_read(sh4uart *uart) -{ - int chn = uart->chn; - int parity_error = 0; - int break_occured = 0; - int ch; - - if (uart->parerr_mark_flag == true) { - uart->parerr_mark_flag = false; - return 0; - } - - if (chn == SH4_SCI) { - if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER | - SH7750_SCSSR1_ORER)) != 0) { - if (SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER)) - parity_error = 1; - sh4uart_handle_error(uart); - } - if ((SCSSR1 & SH7750_SCSSR1_RDRF) == 0) - return -1; - } else { - if ((SCSSR2 & (SH7750_SCSSR2_ER | SH7750_SCSSR2_DR | - SH7750_SCSSR2_BRK)) != 0 || - (SCLSR2 & SH7750_SCLSR2_ORER) != 0) { - if (SCSSR2 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER)) - parity_error = 1; - if (SCSSR2 & SH7750_SCSSR2_BRK) - break_occured = 1; - sh4uart_handle_error(uart); - } - if ((SCSSR2 & SH7750_SCSSR2_RDF) == 0) - return -1; - } - - if (parity_error && !(uart->c_iflag & IGNPAR)) { - if (uart->c_iflag & PARMRK) { - uart->parerr_mark_flag = true; - return 0xff; - } else - return 0; - } - - if (break_occured && !(uart->c_iflag & BRKINT)) { - if (uart->c_iflag & IGNBRK) - return 0; - else - return 0; /* XXX -- SIGINT */ - } - - ch = SCRDR(chn); - - if (uart->chn == SH4_SCI) { - volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1; - *scr &= ~SH7750_SCSSR1_RDRF; - } else { - volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2; - *scr &= ~SH7750_SCSSR2_RDF; - } - - return ch; -} - -/* - * sh4uart_poll_write -- - * This function transmit buffer byte-by-byte in polling mode. - * - * PARAMETERS: - * uart - pointer to the UART descriptor structure - * buf - pointer to transmit buffer - * len - transmit buffer length - * - * RETURNS: - * 0 - */ -int -sh4uart_poll_write(sh4uart *uart, const char *buf, int len) -{ - volatile uint8_t *ssr1 = (volatile uint8_t *)SH7750_SCSSR1; - volatile uint16_t *ssr2 = (volatile uint16_t *)SH7750_SCSSR2; - - while (len) { - if (uart->chn == SH4_SCI) { - while ((SCSSR1 & SH7750_SCSSR1_TDRE) != 0) { - SCTDR1 = *buf++; - len--; - *ssr1 &= ~SH7750_SCSSR1_TDRE; - } - } else { - while ((SCSSR2 & SH7750_SCSSR2_TDFE) != 0) { - int i; - for (i = 0; - i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 & - SH7750_SCFCR2_TTRG); - i++) { - SCTDR2 = *buf++; - len--; - } - while ((SCSSR2 & SH7750_SCSSR2_TDFE) == 0 || - (SCSSR2 & SH7750_SCSSR2_TEND) == 0); - *ssr2 &= ~(SH7750_SCSSR1_TDRE | SH7750_SCSSR2_TEND); - } - } - } - return 0; -} - -/********************************** - * Functions to handle interrupts * - **********************************/ -/* sh4uart1_interrupt_receive -- - * UART interrupt handler routine -- SCI - * Receiving data - * - * PARAMETERS: - * vec - interrupt vector number - * - * RETURNS: - * none - */ -static rtems_isr -sh4uart1_interrupt_receive(rtems_vector_number vec) -{ - register int bp = 0; - char buf[32]; - volatile uint8_t *ssr1 = (volatile uint8_t *)SH7750_SCSSR1; - - - /* Find UART descriptor from vector number */ - sh4uart *uart = &sh4_uarts[0]; - - while (1) { - if ((bp < sizeof(buf) - 1) && ((SCSSR1 & SH7750_SCSSR1_RDRF) != 0)) { - /* Receive character and handle frame/parity errors */ - if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER | - SH7750_SCSSR1_ORER)) != 0) { - if (SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER)) { - if (!(uart->c_iflag & IGNPAR)) { - if (uart->c_iflag & PARMRK) { - buf[bp++] = 0xff; - buf[bp++] = 0x00; - } else - buf[bp++] = 0x00; - } else - buf[bp++] = SCRDR1; - } - sh4uart_handle_error(uart); - } else - buf[bp++] = SCRDR1; - *ssr1 &= ~SH7750_SCSSR1_RDRF; - } else { - if (bp != 0) - rtems_termios_enqueue_raw_characters(uart->tty, buf, bp); - break; - } - } -} - -/* sh4uart2_interrupt_receive -- - * UART interrupt handler routine -- SCIF - * Receiving data - * - * PARAMETERS: - * vec - interrupt vector number - * - * RETURNS: - * none - */ -static rtems_isr -sh4uart2_interrupt_receive(rtems_vector_number vec) -{ - register int bp = 0; - char buf[32]; - volatile uint16_t *ssr2 = (volatile uint16_t *)SH7750_SCSSR2; - - - /* Find UART descriptor from vector number */ - sh4uart *uart = &sh4_uarts[1]; - - while (1) { - if ((bp < sizeof(buf) - 1) && ((SCSSR2 & SH7750_SCSSR2_RDF) != 0)) { - if ((SCSSR2 & (SH7750_SCSSR2_ER | SH7750_SCSSR2_DR | - SH7750_SCSSR2_BRK)) != 0 || - (SH7750_SCLSR2 & SH7750_SCLSR2_ORER) != 0) { - if (SCSSR2 & SH7750_SCSSR2_ER) { - if (!(uart->c_iflag & IGNPAR)) { - if (uart->c_iflag & PARMRK) { - buf[bp++] = 0xff; - buf[bp++] = 0x00; - } else - buf[bp++] = 0x00; - } else - buf[bp++] = SCRDR1; - } - - if (SCSSR2 & SH7750_SCSSR2_BRK) { - if (uart->c_iflag & IGNBRK) - buf[bp++] = 0x00; - else - buf[bp++] = 0x00; /* XXX -- SIGINT */ - } - - sh4uart_handle_error(uart); - } else - buf[bp++] = SCRDR1; - *ssr2 &= ~SH7750_SCSSR2_RDF; - } else { - if (bp != 0) - rtems_termios_enqueue_raw_characters(uart->tty, buf, bp); - break; - } - } -} - - -/* sh4uart1_interrupt_transmit -- - * UART interrupt handler routine -- SCI - * It continues transmit data when old part of data is transmitted - * - * PARAMETERS: - * vec - interrupt vector number - * - * RETURNS: - * none - */ -static rtems_isr -sh4uart1_interrupt_transmit(rtems_vector_number vec) -{ - volatile uint8_t *scr1 = (volatile uint8_t *)SH7750_SCSCR1; - volatile uint8_t *ssr1 = (volatile uint8_t *)SH7750_SCSSR1; - - /* Find UART descriptor from vector number */ - sh4uart *uart = &sh4_uarts[0]; - - if (uart->tx_buf != NULL && uart->tx_ptr < uart->tx_buf_len) { - while ((SCSSR1 & SH7750_SCSSR1_TDRE) != 0 && - uart->tx_ptr < uart->tx_buf_len) { - SCTDR1 = uart->tx_buf[uart->tx_ptr++]; - *ssr1 &= ~SH7750_SCSSR1_TDRE; - } - } else { - register int dequeue = uart->tx_buf_len; - - uart->tx_buf = NULL; - uart->tx_ptr = uart->tx_buf_len = 0; - - /* Disable interrupts while we do not have any data to transmit */ - *scr1 &= ~SH7750_SCSCR_TIE; - - rtems_termios_dequeue_characters(uart->tty, dequeue); - } -} - -/* sh4uart2_interrupt_transmit -- - * UART interrupt handler routine -- SCI - * It continues transmit data when old part of data is transmitted - * - * PARAMETERS: - * vec - interrupt vector number - * - * RETURNS: - * none - */ -static rtems_isr -sh4uart2_interrupt_transmit(rtems_vector_number vec) -{ - volatile uint8_t *ssr1 = (volatile uint8_t *)SH7750_SCSSR1; - volatile uint16_t *scr2 = (volatile uint16_t *)SH7750_SCSCR2; - - /* Find UART descriptor from vector number */ - sh4uart *uart = &sh4_uarts[1]; - - if (uart->tx_buf != NULL && uart->tx_ptr < uart->tx_buf_len) { - while ((SCSSR2 & SH7750_SCSSR2_TDFE) != 0) { - int i; - for (i = 0; - i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 & SH7750_SCFCR2_TTRG); - i++) - SCTDR2 = uart->tx_buf[uart->tx_ptr++]; - while ((SCSSR1 & SH7750_SCSSR1_TDRE) == 0 || - (SCSSR1 & SH7750_SCSSR1_TEND) == 0); - *ssr1 &= ~(SH7750_SCSSR1_TDRE | SH7750_SCSSR2_TEND); - } - } else { - register int dequeue = uart->tx_buf_len; - - uart->tx_buf = NULL; - uart->tx_ptr = uart->tx_buf_len = 0; - - /* Disable interrupts while we do not have any data to transmit */ - *scr2 &= ~SH7750_SCSCR_TIE; - - rtems_termios_dequeue_characters(uart->tty, dequeue); - } -} - -/* sh4uart_interrupt_write -- - * This function initiate transmitting of the buffer in interrupt mode. - * - * PARAMETERS: - * uart - pointer to the UART descriptor structure - * buf - pointer to transmit buffer - * len - transmit buffer length - * - * RETURNS: - * 0 - */ -rtems_status_code -sh4uart_interrupt_write(sh4uart *uart, const char *buf, int len) -{ - if (len > 0) { - volatile uint8_t *scr1 = (volatile uint8_t *)SH7750_SCSCR1; - volatile uint16_t *scr2 = (volatile uint16_t *)SH7750_SCSCR2; - - while ((SCSSR1 & SH7750_SCSSR1_TEND) == 0); - - uart->tx_buf = buf; - uart->tx_buf_len = len; - uart->tx_ptr = 0; - - if (uart->chn == SH4_SCI) - *scr1 |= SH7750_SCSCR_TIE; - else - *scr2 |= SH7750_SCSCR_TIE; - } - - return RTEMS_SUCCESSFUL; -} - -/* sh4uart_stop_remote_tx -- - * This function stop data flow from remote device. - * - * PARAMETERS: - * uart - pointer to the UART descriptor structure - * - * RETURNS: - * RTEMS_SUCCESSFUL - */ -rtems_status_code -sh4uart_stop_remote_tx(sh4uart *uart) -{ - if ( uart->chn == 1 ) { - volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1; - *scr &= ~(SH7750_SCSCR_RIE | SH7750_SCSCR_RE); - } else { - volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2; - *scr &= ~(SH7750_SCSCR_RIE | SH7750_SCSCR_RE); - } - - return RTEMS_SUCCESSFUL; -} - -/* sh4uart_start_remote_tx -- - * This function resume data flow from remote device. - * - * PARAMETERS: - * uart - pointer to the UART descriptor structure - * - * RETURNS: - * RTEMS_SUCCESSFUL - */ -rtems_status_code -sh4uart_start_remote_tx(sh4uart *uart) -{ - if ( uart->chn == 1 ) { - volatile uint8_t *scr = (volatile uint8_t *)SH7750_SCSCR1; - *scr |= SH7750_SCSCR_RIE | SH7750_SCSCR_RE; - } else { - volatile uint16_t *scr = (volatile uint16_t *)SH7750_SCSCR2; - *scr |= SH7750_SCSCR_RIE | SH7750_SCSCR_RE; - } - - return RTEMS_SUCCESSFUL; -} - -#ifdef SH4_WITH_IPL -/********************************* - * Functions for SH-IPL gdb stub * - *********************************/ - -/* - * ipl_finish -- - * Says gdb that program finished to get out from it. - */ -extern void ipl_finish(void); -__asm__ ( -" .global _ipl_finish\n" -"_ipl_finish:\n" -" mov.l __ipl_finish_value, r0\n" -" trapa #0x3f\n" -" nop\n" -" rts\n" -" nop\n" -" .align 4\n" -"__ipl_finish_value:\n" -" .long 255" -); - -extern int ipl_serial_input(int poll_count); -__asm__ ( -" .global _ipl_serial_input\n" -"_ipl_serial_input:\n" -" mov #1,r0\n" -" trapa #0x3f\n" -" nop\n" -" rts\n" -" nop\n"); - -extern void ipl_serial_output(const char *buf, int len); -__asm__ ( -" .global _ipl_serial_output\n" -"_ipl_serial_output:\n" -" mov #0,r0\n" -" trapa #0x3f\n" -" nop\n" -" rts\n" -" nop\n"); - -/* ipl_console_poll_read -- - * poll read operation for simulator console through ipl mechanism. - * - * PARAMETERS: - * minor - minor device number - * - * RETURNS: - * character code red from UART, or -1 if there is no characters - * available - */ -int -ipl_console_poll_read(int minor) -{ - unsigned char buf; - buf = ipl_serial_input(0x100000); - return buf; -} - -/* ipl_console_poll_write -- - * wrapper for polling mode write function - * - * PARAMETERS: - * minor - minor device number - * buf - output buffer - * len - output buffer length - * - * RETURNS: - * result code (0) - */ -int -ipl_console_poll_write(int minor, const char *buf, int len) -{ - int c; - while (len > 0) { - c = (len < 64 ? len : 64); - ipl_serial_output(buf, c); - len -= c; - buf += c; - } - return 0; -} -#endif diff --git a/bsps/sh/gensh4/include/bsp.h b/bsps/sh/gensh4/include/bsp.h deleted file mode 100644 index 294e8e3ea1..0000000000 --- a/bsps/sh/gensh4/include/bsp.h +++ /dev/null @@ -1,105 +0,0 @@ -/** - * @file - * - * @ingroup RTEMSBSPsSH4 - * - * @brief Global BSP definitions. - */ - -/* - * generic sh4 BSP - * - * This include file contains all board IO definitions. - */ - -/* - * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov - * - * Based on work: - * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Minor adaptations for sh2 by: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - */ - -#ifndef LIBBSP_SH_GENSH4_BSP_H -#define LIBBSP_SH_GENSH4_BSP_H - -/** - * @defgroup RTEMSBSPsSH4 SH-4 - * - * @ingroup RTEMSBSPsSH - * - * @brief SH-4 Board Support Package. - * - * @{ - */ - -#include -#include -#include - -#include "rtems/score/sh7750_regs.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* Constants */ - -/* - * Defined in start.S - */ -extern uint32_t boot_mode; -#define SH4_BOOT_MODE_FLASH 0 -#define SH4_BOOT_MODE_IPL 1 - -/* - * Device Driver Table Entries - */ - -/* - * We redefine CONSOLE_DRIVER_TABLE_ENTRY to redirect /dev/console - */ -#undef CONSOLE_DRIVER_TABLE_ENTRY -#define CONSOLE_DRIVER_TABLE_ENTRY \ - { console_initialize, console_open, console_close, \ - console_read, console_write, console_control } - -/* - * BSP methods that cross file boundaries. - */ -void bsp_hw_init(void); -void early_hw_init(void); -void bsp_cache_on(void); - -#ifdef __cplusplus -} -#endif - -/** @} */ - -#endif diff --git a/bsps/sh/gensh4/include/bsp/irq.h b/bsps/sh/gensh4/include/bsp/irq.h deleted file mode 100644 index 8a97d7a1b0..0000000000 --- a/bsps/sh/gensh4/include/bsp/irq.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/bsps/sh/gensh4/include/rtems/score/iosh7750.h b/bsps/sh/gensh4/include/rtems/score/iosh7750.h deleted file mode 100644 index c5c532dbc2..0000000000 --- a/bsps/sh/gensh4/include/rtems/score/iosh7750.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This include file contains information pertaining to the Hitachi SH - * processor. - * - * NOTE: NOT ALL VALUES HAVE BEEN CHECKED !! - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which - * contained no copyright notice. - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modified to reflect on-chip registers for sh7045 processor, based on - * "Register.h" distributed with Hitachi's EVB7045F tutorials, and which - * contained no copyright notice: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * August, 1999 - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - */ - -#ifndef __IOSH7750_H -#define __IOSH7750_H - -#include - -#endif diff --git a/bsps/sh/gensh4/include/rtems/score/ipl.h b/bsps/sh/gensh4/include/rtems/score/ipl.h deleted file mode 100644 index 9ce2d87e0e..0000000000 --- a/bsps/sh/gensh4/include/rtems/score/ipl.h +++ /dev/null @@ -1,73 +0,0 @@ -/* ipl.h - * - * IPL console driver - * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov - * - * Based on work: - * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __IPL_DRIVER_h -#define __IPL_DRIVER_h - -#ifdef __cplusplus -extern "C" { -#endif - -#define IPL_DRIVER_TABLE_ENTRY \ - { ipl_console_initialize, ipl_console_open, ipl_console_close, \ - ipl_console_read, ipl_console_write, ipl_console_control } - - -#define NULL_SUCCESSFUL RTEMS_SUCCESSFUL - -rtems_device_driver ipl_console_initialize( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -rtems_device_driver ipl_console_open( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -rtems_device_driver ipl_console_close( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -rtems_device_driver ipl_console_read( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -rtems_device_driver ipl_console_write( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -rtems_device_driver ipl_console_control( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/bsps/sh/gensh4/include/rtems/score/ispsh7750.h b/bsps/sh/gensh4/include/rtems/score/ispsh7750.h deleted file mode 100644 index 4197feb9ac..0000000000 --- a/bsps/sh/gensh4/include/rtems/score/ispsh7750.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This include file contains information pertaining to the Hitachi - * SH7750 processor. - * - * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov - * - * Based on work of: - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modified to reflect isp entries for sh7045 processor: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - */ - -#ifndef __CPU_ISPS_H -#define __CPU_ISPS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* dummy ISP */ -extern void _dummy_isp( void ); - -extern void __ISR_Handler( uint32_t vector ); - -/* This variable contains VBR value used to pass control when debug, error - * or virtual memory exceptions occured. - */ -extern void *_VBR_Saved; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsps/sh/gensh4/include/rtems/score/sh4_regs.h b/bsps/sh/gensh4/include/rtems/score/sh4_regs.h deleted file mode 100644 index 074dc6d7a1..0000000000 --- a/bsps/sh/gensh4/include/rtems/score/sh4_regs.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Bits on SH-4 registers. - * See SH-4 Programming manual for more details. - * - * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia - * Author: Alexandra Kossovsky - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __SH4_REGS_H__ -#define __SH4_REGS_H__ - -/* SR -- Status Register */ -#define SH4_SR_MD 0x40000000 /* Priveleged mode */ -#define SH4_SR_RB 0x20000000 /* General register bank specifier */ -#define SH4_SR_BL 0x10000000 /* Exeption/interrupt masking bit */ -#define SH4_SR_FD 0x00008000 /* FPU disable bit */ -#define SH4_SR_M 0x00000200 /* For signed division: - divisor (module) is negative */ -#define SH4_SR_Q 0x00000100 /* For signed division: - dividend (and quotient) is negative */ -#define SH4_SR_IMASK 0x000000f0 /* Interrupt mask level */ -#define SH4_SR_IMASK_S 4 -#define SH4_SR_S 0x00000002 /* Saturation for MAC instruction: - if set, data in MACH/L register - is restricted to 48/32 bits - for MAC.W/L instructions */ -#define SH4_SR_T 0x00000001 /* 1 if last condiyion was true */ -#define SH4_SR_RESERV 0x8fff7d0d /* Reserved bits, read/write as 0 */ - -/* FPSCR -- FPU Starus/Control Register */ -#define SH4_FPSCR_FR 0x00200000 /* FPU register bank specifier */ -#define SH4_FPSCR_SZ 0x00100000 /* FMOV 64-bit transfer mode */ -#define SH4_FPSCR_PR 0x00080000 /* Double-percision floating-point - operations flag */ - /* SH4_FPSCR_SZ & SH4_FPSCR_PR != 1 */ -#define SH4_FPSCR_DN 0x00040000 /* Treat denormalized number as zero */ -#define SH4_FPSCR_CAUSE 0x0003f000 /* FPU exeption cause field */ -#define SH4_FPSCR_CAUSE_S 12 -#define SH4_FPSCR_ENABLE 0x00000f80 /* FPU exeption enable field */ -#define SH4_FPSCR_ENABLE_s 7 -#define SH4_FPSCR_FLAG 0x0000007d /* FPU exeption flag field */ -#define SH4_FPSCR_FLAG_S 2 -#define SH4_FPSCR_RM 0x00000001 /* Rounding mode: - 1/0 -- round to zero/nearest */ -#define SH4_FPSCR_RESERV 0xffd00000 /* Reserved bits, read/write as 0 */ - -#endif diff --git a/bsps/sh/gensh4/include/rtems/score/sh7750_regs.h b/bsps/sh/gensh4/include/rtems/score/sh7750_regs.h deleted file mode 100644 index b65f9b6e51..0000000000 --- a/bsps/sh/gensh4/include/rtems/score/sh7750_regs.h +++ /dev/null @@ -1,1613 +0,0 @@ -/* - * SH-7750 memory-mapped registers - * This file based on information provided in the following document: - * "Hitachi SuperH (tm) RISC engine. SH7750 Series (SH7750, SH7750S) - * Hardware Manual" - * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd. - * - * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia - * Author: Alexandra Kossovsky - * Victor V. Vengerov - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __SH7750_REGS_H__ -#define __SH7750_REGS_H__ - -/* - * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and - * in 0x1f000000 - 0x1fffffff (area 7 address) - */ -#define SH7750_P4_BASE 0xff000000 /* Accessable only in - priveleged mode */ -#define SH7750_A7_BASE 0x1f000000 /* Accessable only using TLB */ - -#define SH7750_P4_REG32(ofs) (SH7750_P4_BASE + (ofs)) -#define SH7750_A7_REG32(ofs) (SH7750_A7_BASE + (ofs)) - -/* - * MMU Registers - */ - -/* Page Table Entry High register - PTEH */ -#define SH7750_PTEH_REGOFS 0x000000 /* offset */ -#define SH7750_PTEH SH7750_P4_REG32(SH7750_PTEH_REGOFS) -#define SH7750_PTEH_A7 SH7750_A7_REG32(SH7750_PTEH_REGOFS) -#define SH7750_PTEH_VPN 0xfffffd00 /* Virtual page number */ -#define SH7750_PTEH_VPN_S 10 -#define SH7750_PTEH_ASID 0x000000ff /* Address space identifier */ -#define SH7750_PTEH_ASID_S 0 - -/* Page Table Entry Low register - PTEL */ -#define SH7750_PTEL_REGOFS 0x000004 /* offset */ -#define SH7750_PTEL SH7750_P4_REG32(SH7750_PTEL_REGOFS) -#define SH7750_PTEL_A7 SH7750_A7_REG32(SH7750_PTEL_REGOFS) -#define SH7750_PTEL_PPN 0x1ffffc00 /* Physical page number */ -#define SH7750_PTEL_PPN_S 10 -#define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */ -#define SH7750_PTEL_SZ1 0x00000080 /* Page size bit 1 */ -#define SH7750_PTEL_SZ0 0x00000010 /* Page size bit 0 */ -#define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */ -#define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */ -#define SH7750_PTEL_SZ_64KB 0x00000080 /* 64-kbyte page */ -#define SH7750_PTEL_SZ_1MB 0x00000090 /* 1-Mbyte page */ -#define SH7750_PTEL_PR 0x00000060 /* Protection Key Data */ -#define SH7750_PTEL_PR_ROPO 0x00000000 /* read-only in priv mode */ -#define SH7750_PTEL_PR_RWPO 0x00000020 /* read-write in priv mode */ -#define SH7750_PTEL_PR_ROPU 0x00000040 /* read-only in priv or user mode*/ -#define SH7750_PTEL_PR_RWPU 0x00000060 /* read-write in priv or user mode*/ -#define SH7750_PTEL_C 0x00000008 /* Cacheability - (0 - page not cacheable) */ -#define SH7750_PTEL_D 0x00000004 /* Dirty bit (1 - write has been - performed to a page) */ -#define SH7750_PTEL_SH 0x00000002 /* Share Status bit (1 - page are - shared by processes) */ -#define SH7750_PTEL_WT 0x00000001 /* Write-through bit, specifies the - cache write mode: - 0 - Copy-back mode - 1 - Write-through mode */ - -/* Page Table Entry Assistance register - PTEA */ -#define SH7750_PTEA_REGOFS 0x000034 /* offset */ -#define SH7750_PTEA SH7750_P4_REG32(SH7750_PTEA_REGOFS) -#define SH7750_PTEA_A7 SH7750_A7_REG32(SH7750_PTEA_REGOFS) -#define SH7750_PTEA_TC 0x00000008 /* Timing Control bit - 0 - use area 5 wait states - 1 - use area 6 wait states */ -#define SH7750_PTEA_SA 0x00000007 /* Space Attribute bits: */ -#define SH7750_PTEA_SA_UNDEF 0x00000000 /* 0 - undefined */ -#define SH7750_PTEA_SA_IOVAR 0x00000001 /* 1 - variable-size I/O space */ -#define SH7750_PTEA_SA_IO8 0x00000002 /* 2 - 8-bit I/O space */ -#define SH7750_PTEA_SA_IO16 0x00000003 /* 3 - 16-bit I/O space */ -#define SH7750_PTEA_SA_CMEM8 0x00000004 /* 4 - 8-bit common memory space*/ -#define SH7750_PTEA_SA_CMEM16 0x00000005 /* 5 - 16-bit common memory space*/ -#define SH7750_PTEA_SA_AMEM8 0x00000006 /* 6 - 8-bit attr memory space */ -#define SH7750_PTEA_SA_AMEM16 0x00000007 /* 7 - 16-bit attr memory space */ - - -/* Translation table base register */ -#define SH7750_TTB_REGOFS 0x000008 /* offset */ -#define SH7750_TTB SH7750_P4_REG32(SH7750_TTB_REGOFS) -#define SH7750_TTB_A7 SH7750_A7_REG32(SH7750_TTB_REGOFS) - -/* TLB exeption address register - TEA */ -#define SH7750_TEA_REGOFS 0x00000c /* offset */ -#define SH7750_TEA SH7750_P4_REG32(SH7750_TEA_REGOFS) -#define SH7750_TEA_A7 SH7750_A7_REG32(SH7750_TEA_REGOFS) - -/* MMU control register - MMUCR */ -#define SH7750_MMUCR_REGOFS 0x000010 /* offset */ -#define SH7750_MMUCR SH7750_P4_REG32(SH7750_MMUCR_REGOFS) -#define SH7750_MMUCR_A7 SH7750_A7_REG32(SH7750_MMUCR_REGOFS) -#define SH7750_MMUCR_AT 0x00000001 /* Address translation bit */ -#define SH7750_MMUCR_TI 0x00000004 /* TLB invalidate */ -#define SH7750_MMUCR_SV 0x00000100 /* Single Virtual Mode bit */ -#define SH7750_MMUCR_SQMD 0x00000200 /* Store Queue Mode bit */ -#define SH7750_MMUCR_URC 0x0000FC00 /* UTLB Replace Counter */ -#define SH7750_MMUCR_URC_S 10 -#define SH7750_MMUCR_URB 0x00FC0000 /* UTLB Replace Boundary */ -#define SH7750_MMUCR_URB_S 18 -#define SH7750_MMUCR_LRUI 0xFC000000 /* Least Recently Used ITLB */ -#define SH7750_MMUCR_LRUI_S 26 - - - - -/* - * Cache registers - * IC -- instructions cache - * OC -- operand cache - */ - -/* Cache Control Register - CCR */ -#define SH7750_CCR_REGOFS 0x00001c /* offset */ -#define SH7750_CCR SH7750_P4_REG32(SH7750_CCR_REGOFS) -#define SH7750_CCR_A7 SH7750_A7_REG32(SH7750_CCR_REGOFS) - -#define SH7750_CCR_IIX 0x00008000 /* IC index enable bit */ -#define SH7750_CCR_ICI 0x00000800 /* IC invalidation bit: - set it to clear IC */ -#define SH7750_CCR_ICE 0x00000100 /* IC enable bit */ -#define SH7750_CCR_OIX 0x00000080 /* OC index enable bit */ -#define SH7750_CCR_ORA 0x00000020 /* OC RAM enable bit - if you set OCE = 0, - you should set ORA = 0 */ -#define SH7750_CCR_OCI 0x00000008 /* OC invalidation bit */ -#define SH7750_CCR_CB 0x00000004 /* Copy-back bit for P1 area */ -#define SH7750_CCR_WT 0x00000002 /* Write-through bit for P0,U0,P3 area */ -#define SH7750_CCR_OCE 0x00000001 /* OC enable bit */ - -/* Queue address control register 0 - QACR0 */ -#define SH7750_QACR0_REGOFS 0x000038 /* offset */ -#define SH7750_QACR0 SH7750_P4_REG32(SH7750_QACR0_REGOFS) -#define SH7750_QACR0_A7 SH7750_A7_REG32(SH7750_QACR0_REGOFS) - -/* Queue address control register 1 - QACR1 */ -#define SH7750_QACR1_REGOFS 0x00003c /* offset */ -#define SH7750_QACR1 SH7750_P4_REG32(SH7750_QACR1_REGOFS) -#define SH7750_QACR1_A7 SH7750_A7_REG32(SH7750_QACR1_REGOFS) - - -/* - * Exeption-related registers - */ - -/* Immediate data for TRAPA instuction - TRA */ -#define SH7750_TRA_REGOFS 0x000020 /* offset */ -#define SH7750_TRA SH7750_P4_REG32(SH7750_TRA_REGOFS) -#define SH7750_TRA_A7 SH7750_A7_REG32(SH7750_TRA_REGOFS) - -#define SH7750_TRA_IMM 0x000003fd /* Immediate data operand */ -#define SH7750_TRA_IMM_S 2 - -/* Exeption event register - EXPEVT */ -#define SH7750_EXPEVT_REGOFS 0x000024 -#define SH7750_EXPEVT SH7750_P4_REG32(SH7750_EXPEVT_REGOFS) -#define SH7750_EXPEVT_A7 SH7750_A7_REG32(SH7750_EXPEVT_REGOFS) - -#define SH7750_EXPEVT_EX 0x00000fff /* Exeption code */ -#define SH7750_EXPEVT_EX_S 0 - -/* Interrupt event register */ -#define SH7750_INTEVT_REGOFS 0x000028 -#define SH7750_INTEVT SH7750_P4_REG32(SH7750_INTEVT_REGOFS) -#define SH7750_INTEVT_A7 SH7750_A7_REG32(SH7750_INTEVT_REGOFS) -#define SH7750_INTEVT_EX 0x00000fff /* Exeption code */ -#define SH7750_INTEVT_EX_S 0 - -/* - * Exception/interrupt codes - */ -#define SH7750_EVT_TO_NUM(evt) ((evt) >> 5) - -/* Reset exception category */ -#define SH7750_EVT_POWER_ON_RST 0x000 /* Power-on reset */ -#define SH7750_EVT_MANUAL_RST 0x020 /* Manual reset */ -#define SH7750_EVT_TLB_MULT_HIT 0x140 /* TLB multiple-hit exception */ - -/* General exception category */ -#define SH7750_EVT_USER_BREAK 0x1E0 /* User break */ -#define SH7750_EVT_IADDR_ERR 0x0E0 /* Instruction address error */ -#define SH7750_EVT_TLB_READ_MISS 0x040 /* ITLB miss exception / - DTLB miss exception (read) */ -#define SH7750_EVT_TLB_READ_PROTV 0x0A0 /* ITLB protection violation / - DTLB protection violation (read)*/ -#define SH7750_EVT_ILLEGAL_INSTR 0x180 /* General Illegal Instruction - exception */ -#define SH7750_EVT_SLOT_ILLEGAL_INSTR 0x1A0 /* Slot Illegal Instruction - exception */ -#define SH7750_EVT_FPU_DISABLE 0x800 /* General FPU disable exception*/ -#define SH7750_EVT_SLOT_FPU_DISABLE 0x820 /* Slot FPU disable exception */ -#define SH7750_EVT_DATA_READ_ERR 0x0E0 /* Data address error (read) */ -#define SH7750_EVT_DATA_WRITE_ERR 0x100 /* Data address error (write) */ -#define SH7750_EVT_DTLB_WRITE_MISS 0x060 /* DTLB miss exception (write) */ -#define SH7750_EVT_DTLB_WRITE_PROTV 0x0C0 /* DTLB protection violation - exception (write) */ -#define SH7750_EVT_FPU_EXCEPTION 0x120 /* FPU exception */ -#define SH7750_EVT_INITIAL_PGWRITE 0x080 /* Initial Page Write exception */ -#define SH7750_EVT_TRAPA 0x160 /* Unconditional trap (TRAPA) */ - -/* Interrupt exception category */ -#define SH7750_EVT_NMI 0x1C0 /* Non-maskable interrupt */ -#define SH7750_EVT_IRQ0 0x200 /* External Interrupt 0 */ -#define SH7750_EVT_IRQ1 0x220 /* External Interrupt 1 */ -#define SH7750_EVT_IRQ2 0x240 /* External Interrupt 2 */ -#define SH7750_EVT_IRQ3 0x260 /* External Interrupt 3 */ -#define SH7750_EVT_IRQ4 0x280 /* External Interrupt 4 */ -#define SH7750_EVT_IRQ5 0x2A0 /* External Interrupt 5 */ -#define SH7750_EVT_IRQ6 0x2C0 /* External Interrupt 6 */ -#define SH7750_EVT_IRQ7 0x2E0 /* External Interrupt 7 */ -#define SH7750_EVT_IRQ8 0x300 /* External Interrupt 8 */ -#define SH7750_EVT_IRQ9 0x320 /* External Interrupt 9 */ -#define SH7750_EVT_IRQA 0x340 /* External Interrupt A */ -#define SH7750_EVT_IRQB 0x360 /* External Interrupt B */ -#define SH7750_EVT_IRQC 0x380 /* External Interrupt C */ -#define SH7750_EVT_IRQD 0x3A0 /* External Interrupt D */ -#define SH7750_EVT_IRQE 0x3C0 /* External Interrupt E */ - -/* Peripheral Module Interrupts - Timer Unit (TMU) */ -#define SH7750_EVT_TUNI0 0x400 /* TMU Underflow Interrupt 0 */ -#define SH7750_EVT_TUNI1 0x420 /* TMU Underflow Interrupt 1 */ -#define SH7750_EVT_TUNI2 0x440 /* TMU Underflow Interrupt 2 */ -#define SH7750_EVT_TICPI2 0x460 /* TMU Input Capture Interrupt 2*/ - -/* Peripheral Module Interrupts - Real-Time Clock (RTC) */ -#define SH7750_EVT_RTC_ATI 0x480 /* Alarm Interrupt Request */ -#define SH7750_EVT_RTC_PRI 0x4A0 /* Periodic Interrupt Request */ -#define SH7750_EVT_RTC_CUI 0x4C0 /* Carry Interrupt Request */ - -/* Peripheral Module Interrupts - Serial Communication Interface (SCI) */ -#define SH7750_EVT_SCI_ERI 0x4E0 /* Receive Error */ -#define SH7750_EVT_SCI_RXI 0x500 /* Receive Data Register Full */ -#define SH7750_EVT_SCI_TXI 0x520 /* Transmit Data Register Empty */ -#define SH7750_EVT_SCI_TEI 0x540 /* Transmit End */ - -/* Peripheral Module Interrupts - Watchdog Timer (WDT) */ -#define SH7750_EVT_WDT_ITI 0x560 /* Interval Timer Interrupt - (used when WDT operates in - interval timer mode) */ - -/* Peripheral Module Interrupts - Memory Refresh Unit (REF) */ -#define SH7750_EVT_REF_RCMI 0x580 /* Compare-match Interrupt */ -#define SH7750_EVT_REF_ROVI 0x5A0 /* Refresh Counter Overflow - interrupt */ - -/* Peripheral Module Interrupts - Hitachi User Debug Interface (H-UDI) */ -#define SH7750_EVT_HUDI 0x600 /* UDI interrupt */ - -/* Peripheral Module Interrupts - General-Purpose I/O (GPIO) */ -#define SH7750_EVT_GPIO 0x620 /* GPIO Interrupt */ - -/* Peripheral Module Interrupts - DMA Controller (DMAC) */ -#define SH7750_EVT_DMAC_DMTE0 0x640 /* DMAC 0 Transfer End Interrupt*/ -#define SH7750_EVT_DMAC_DMTE1 0x660 /* DMAC 1 Transfer End Interrupt*/ -#define SH7750_EVT_DMAC_DMTE2 0x680 /* DMAC 2 Transfer End Interrupt*/ -#define SH7750_EVT_DMAC_DMTE3 0x6A0 /* DMAC 3 Transfer End Interrupt*/ -#define SH7750_EVT_DMAC_DMAE 0x6C0 /* DMAC Address Error Interrupt */ - -/* Peripheral Module Interrupts - Serial Communication Interface with FIFO */ -/* (SCIF) */ -#define SH7750_EVT_SCIF_ERI 0x700 /* Receive Error */ -#define SH7750_EVT_SCIF_RXI 0x720 /* Receive FIFO Data Full or - Receive Data ready interrupt */ -#define SH7750_EVT_SCIF_BRI 0x740 /* Break or overrun error */ -#define SH7750_EVT_SCIF_TXI 0x760 /* Transmit FIFO Data Empty */ - -/* - * Power Management - */ -#define SH7750_STBCR_REGOFS 0xC00004 /* offset */ -#define SH7750_STBCR SH7750_P4_REG32(SH7750_STBCR_REGOFS) -#define SH7750_STBCR_A7 SH7750_A7_REG32(SH7750_STBCR_REGOFS) - -#define SH7750_STBCR_STBY 0x80 /* Specifies a transition to standby mode: - 0 - Transition to SLEEP mode on SLEEP - 1 - Transition to STANDBY mode on SLEEP*/ -#define SH7750_STBCR_PHZ 0x40 /* State of peripheral module pins in - standby mode: - 0 - normal state - 1 - high-impendance state */ - -#define SH7750_STBCR_PPU 0x20 /* Peripheral module pins pull-up controls*/ -#define SH7750_STBCR_MSTP4 0x10 /* Stopping the clock supply to DMAC */ -#define SH7750_STBCR_DMAC_STP SH7750_STBCR_MSTP4 -#define SH7750_STBCR_MSTP3 0x08 /* Stopping the clock supply to SCIF */ -#define SH7750_STBCR_SCIF_STP SH7750_STBCR_MSTP3 -#define SH7750_STBCR_MSTP2 0x04 /* Stopping the clock supply to TMU */ -#define SH7750_STBCR_TMU_STP SH7750_STBCR_MSTP2 -#define SH7750_STBCR_MSTP1 0x02 /* Stopping the clock supply to RTC */ -#define SH7750_STBCR_RTC_STP SH7750_STBCR_MSTP1 -#define SH7750_STBCR_MSPT0 0x01 /* Stopping the clock supply to SCI */ -#define SH7750_STBCR_SCI_STP SH7750_STBCR_MSTP0 - -#define SH7750_STBCR_STBY 0x80 - - -#define SH7750_STBCR2_REGOFS 0xC00010 /* offset */ -#define SH7750_STBCR2 SH7750_P4_REG32(SH7750_STBCR2_REGOFS) -#define SH7750_STBCR2_A7 SH7750_A7_REG32(SH7750_STBCR2_REGOFS) - -#define SH7750_STBCR2_DSLP 0x80 /* Specifies transition to deep sleep mode: - 0 - transition to sleep or standby mode - as it is specified in STBY bit - 1 - transition to deep sleep mode on - execution of SLEEP instruction */ -#define SH7750_STBCR2_MSTP6 0x02 /* Stopping the clock supply to Store Queue - in the cache controller */ -#define SH7750_STBCR2_SQ_STP SH7750_STBCR2_MSTP6 -#define SH7750_STBCR2_MSTP5 0x01 /* Stopping the clock supply to the User - Break Controller (UBC) */ -#define SH7750_STBCR2_UBC_STP SH7750_STBCR2_MSTP5 - -/* - * Clock Pulse Generator (CPG) - */ -#define SH7750_FRQCR_REGOFS 0xC00000 /* offset */ -#define SH7750_FRQCR SH7750_P4_REG32(SH7750_FRQCR_REGOFS) -#define SH7750_FRQCR_A7 SH7750_A7_REG32(SH7750_FRQCR_REGOFS) - -#define SH7750_FRQCR_CKOEN 0x0800 /* Clock Output Enable - 0 - CKIO pin goes to HiZ/pullup - 1 - Clock is output from CKIO */ -#define SH7750_FRQCR_PLL1EN 0x0400 /* PLL circuit 1 enable */ -#define SH7750_FRQCR_PLL2EN 0x0200 /* PLL circuit 2 enable */ - -#define SH7750_FRQCR_IFC 0x01C0 /* CPU clock frequency division ratio: */ -#define SH7750_FRQCR_IFCDIV1 0x0000 /* 0 - * 1 */ -#define SH7750_FRQCR_IFCDIV2 0x0040 /* 1 - * 1/2 */ -#define SH7750_FRQCR_IFCDIV3 0x0080 /* 2 - * 1/3 */ -#define SH7750_FRQCR_IFCDIV4 0x00C0 /* 3 - * 1/4 */ -#define SH7750_FRQCR_IFCDIV6 0x0100 /* 4 - * 1/6 */ -#define SH7750_FRQCR_IFCDIV8 0x0140 /* 5 - * 1/8 */ - -#define SH7750_FRQCR_BFC 0x0038 /* Bus clock frequency division ratio: */ -#define SH7750_FRQCR_BFCDIV1 0x0000 /* 0 - * 1 */ -#define SH7750_FRQCR_BFCDIV2 0x0008 /* 1 - * 1/2 */ -#define SH7750_FRQCR_BFCDIV3 0x0010 /* 2 - * 1/3 */ -#define SH7750_FRQCR_BFCDIV4 0x0018 /* 3 - * 1/4 */ -#define SH7750_FRQCR_BFCDIV6 0x0020 /* 4 - * 1/6 */ -#define SH7750_FRQCR_BFCDIV8 0x0028 /* 5 - * 1/8 */ - -#define SH7750_FRQCR_PFC 0x0007 /* Peripheral module clock frequency - division ratio: */ -#define SH7750_FRQCR_PFCDIV2 0x0000 /* 0 - * 1/2 */ -#define SH7750_FRQCR_PFCDIV3 0x0001 /* 1 - * 1/3 */ -#define SH7750_FRQCR_PFCDIV4 0x0002 /* 2 - * 1/4 */ -#define SH7750_FRQCR_PFCDIV6 0x0003 /* 3 - * 1/6 */ -#define SH7750_FRQCR_PFCDIV8 0x0004 /* 4 - * 1/8 */ - -/* - * Watchdog Timer (WDT) - */ - -/* Watchdog Timer Counter register - WTCNT */ -#define SH7750_WTCNT_REGOFS 0xC00008 /* offset */ -#define SH7750_WTCNT SH7750_P4_REG32(SH7750_WTCNT_REGOFS) -#define SH7750_WTCNT_A7 SH7750_A7_REG32(SH7750_WTCNT_REGOFS) -#define SH7750_WTCNT_KEY 0x5A00 /* When WTCNT byte register written, - you have to set the upper byte to - 0x5A */ - -/* Watchdog Timer Control/Status register - WTCSR */ -#define SH7750_WTCSR_REGOFS 0xC0000C /* offset */ -#define SH7750_WTCSR SH7750_P4_REG32(SH7750_WTCSR_REGOFS) -#define SH7750_WTCSR_A7 SH7750_A7_REG32(SH7750_WTCSR_REGOFS) -#define SH7750_WTCSR_KEY 0xA500 /* When WTCSR byte register written, - you have to set the upper byte to - 0xA5 */ -#define SH7750_WTCSR_TME 0x80 /* Timer enable (1-upcount start) */ -#define SH7750_WTCSR_MODE 0x40 /* Timer Mode Select: */ -#define SH7750_WTCSR_MODE_WT 0x40 /* Watchdog Timer Mode */ -#define SH7750_WTCSR_MODE_IT 0x00 /* Interval Timer Mode */ -#define SH7750_WTCSR_RSTS 0x20 /* Reset Select: */ -#define SH7750_WTCSR_RST_MAN 0x20 /* Manual Reset */ -#define SH7750_WTCSR_RST_PWR 0x00 /* Power-on Reset */ -#define SH7750_WTCSR_WOVF 0x10 /* Watchdog Timer Overflow Flag */ -#define SH7750_WTCSR_IOVF 0x08 /* Interval Timer Overflow Flag */ -#define SH7750_WTCSR_CKS 0x07 /* Clock Select: */ -#define SH7750_WTCSR_CKS_DIV32 0x00 /* 1/32 of frequency divider 2 input */ -#define SH7750_WTCSR_CKS_DIV64 0x01 /* 1/64 */ -#define SH7750_WTCSR_CKS_DIV128 0x02 /* 1/128 */ -#define SH7750_WTCSR_CKS_DIV256 0x03 /* 1/256 */ -#define SH7750_WTCSR_CKS_DIV512 0x04 /* 1/512 */ -#define SH7750_WTCSR_CKS_DIV1024 0x05 /* 1/1024 */ -#define SH7750_WTCSR_CKS_DIV2048 0x06 /* 1/2048 */ -#define SH7750_WTCSR_CKS_DIV4096 0x07 /* 1/4096 */ - -/* - * Real-Time Clock (RTC) - */ -/* 64-Hz Counter Register (byte, read-only) - R64CNT */ -#define SH7750_R64CNT_REGOFS 0xC80000 /* offset */ -#define SH7750_R64CNT SH7750_P4_REG32(SH7750_R64CNT_REGOFS) -#define SH7750_R64CNT_A7 SH7750_A7_REG32(SH7750_R64CNT_REGOFS) - -/* Second Counter Register (byte, BCD-coded) - RSECCNT */ -#define SH7750_RSECCNT_REGOFS 0xC80004 /* offset */ -#define SH7750_RSECCNT SH7750_P4_REG32(SH7750_RSECCNT_REGOFS) -#define SH7750_RSECCNT_A7 SH7750_A7_REG32(SH7750_RSECCNT_REGOFS) - -/* Minute Counter Register (byte, BCD-coded) - RMINCNT */ -#define SH7750_RMINCNT_REGOFS 0xC80008 /* offset */ -#define SH7750_RMINCNT SH7750_P4_REG32(SH7750_RMINCNT_REGOFS) -#define SH7750_RMINCNT_A7 SH7750_A7_REG32(SH7750_RMINCNT_REGOFS) - -/* Hour Counter Register (byte, BCD-coded) - RHRCNT */ -#define SH7750_RHRCNT_REGOFS 0xC8000C /* offset */ -#define SH7750_RHRCNT SH7750_P4_REG32(SH7750_RHRCNT_REGOFS) -#define SH7750_RHRCNT_A7 SH7750_A7_REG32(SH7750_RHRCNT_REGOFS) - -/* Day-of-Week Counter Register (byte) - RWKCNT */ -#define SH7750_RWKCNT_REGOFS 0xC80010 /* offset */ -#define SH7750_RWKCNT SH7750_P4_REG32(SH7750_RWKCNT_REGOFS) -#define SH7750_RWKCNT_A7 SH7750_A7_REG32(SH7750_RWKCNT_REGOFS) - -#define SH7750_RWKCNT_SUN 0 /* Sunday */ -#define SH7750_RWKCNT_MON 1 /* Monday */ -#define SH7750_RWKCNT_TUE 2 /* Tuesday */ -#define SH7750_RWKCNT_WED 3 /* Wednesday */ -#define SH7750_RWKCNT_THU 4 /* Thursday */ -#define SH7750_RWKCNT_FRI 5 /* Friday */ -#define SH7750_RWKCNT_SAT 6 /* Saturday */ - -/* Day Counter Register (byte, BCD-coded) - RDAYCNT */ -#define SH7750_RDAYCNT_REGOFS 0xC80014 /* offset */ -#define SH7750_RDAYCNT SH7750_P4_REG32(SH7750_RDAYCNT_REGOFS) -#define SH7750_RDAYCNT_A7 SH7750_A7_REG32(SH7750_RDAYCNT_REGOFS) - -/* Month Counter Register (byte, BCD-coded) - RMONCNT */ -#define SH7750_RMONCNT_REGOFS 0xC80018 /* offset */ -#define SH7750_RMONCNT SH7750_P4_REG32(SH7750_RMONCNT_REGOFS) -#define SH7750_RMONCNT_A7 SH7750_A7_REG32(SH7750_RMONCNT_REGOFS) - -/* Year Counter Register (half, BCD-coded) - RYRCNT */ -#define SH7750_RYRCNT_REGOFS 0xC8001C /* offset */ -#define SH7750_RYRCNT SH7750_P4_REG32(SH7750_RYRCNT_REGOFS) -#define SH7750_RYRCNT_A7 SH7750_A7_REG32(SH7750_RYRCNT_REGOFS) - -/* Second Alarm Register (byte, BCD-coded) - RSECAR */ -#define SH7750_RSECAR_REGOFS 0xC80020 /* offset */ -#define SH7750_RSECAR SH7750_P4_REG32(SH7750_RSECAR_REGOFS) -#define SH7750_RSECAR_A7 SH7750_A7_REG32(SH7750_RSECAR_REGOFS) -#define SH7750_RSECAR_ENB 0x80 /* Second Alarm Enable */ - -/* Minute Alarm Register (byte, BCD-coded) - RMINAR */ -#define SH7750_RMINAR_REGOFS 0xC80024 /* offset */ -#define SH7750_RMINAR SH7750_P4_REG32(SH7750_RMINAR_REGOFS) -#define SH7750_RMINAR_A7 SH7750_A7_REG32(SH7750_RMINAR_REGOFS) -#define SH7750_RMINAR_ENB 0x80 /* Minute Alarm Enable */ - -/* Hour Alarm Register (byte, BCD-coded) - RHRAR */ -#define SH7750_RHRAR_REGOFS 0xC80028 /* offset */ -#define SH7750_RHRAR SH7750_P4_REG32(SH7750_RHRAR_REGOFS) -#define SH7750_RHRAR_A7 SH7750_A7_REG32(SH7750_RHRAR_REGOFS) -#define SH7750_RHRAR_ENB 0x80 /* Hour Alarm Enable */ - -/* Day-of-Week Alarm Register (byte) - RWKAR */ -#define SH7750_RWKAR_REGOFS 0xC8002C /* offset */ -#define SH7750_RWKAR SH7750_P4_REG32(SH7750_RWKAR_REGOFS) -#define SH7750_RWKAR_A7 SH7750_A7_REG32(SH7750_RWKAR_REGOFS) -#define SH7750_RWKAR_ENB 0x80 /* Day-of-week Alarm Enable */ - -#define SH7750_RWKAR_SUN 0 /* Sunday */ -#define SH7750_RWKAR_MON 1 /* Monday */ -#define SH7750_RWKAR_TUE 2 /* Tuesday */ -#define SH7750_RWKAR_WED 3 /* Wednesday */ -#define SH7750_RWKAR_THU 4 /* Thursday */ -#define SH7750_RWKAR_FRI 5 /* Friday */ -#define SH7750_RWKAR_SAT 6 /* Saturday */ - -/* Day Alarm Register (byte, BCD-coded) - RDAYAR */ -#define SH7750_RDAYAR_REGOFS 0xC80030 /* offset */ -#define SH7750_RDAYAR SH7750_P4_REG32(SH7750_RDAYAR_REGOFS) -#define SH7750_RDAYAR_A7 SH7750_A7_REG32(SH7750_RDAYAR_REGOFS) -#define SH7750_RDAYAR_ENB 0x80 /* Day Alarm Enable */ - -/* Month Counter Register (byte, BCD-coded) - RMONAR */ -#define SH7750_RMONAR_REGOFS 0xC80034 /* offset */ -#define SH7750_RMONAR SH7750_P4_REG32(SH7750_RMONAR_REGOFS) -#define SH7750_RMONAR_A7 SH7750_A7_REG32(SH7750_RMONAR_REGOFS) -#define SH7750_RMONAR_ENB 0x80 /* Month Alarm Enable */ - -/* RTC Control Register 1 (byte) - RCR1 */ -#define SH7750_RCR1_REGOFS 0xC80038 /* offset */ -#define SH7750_RCR1 SH7750_P4_REG32(SH7750_RCR1_REGOFS) -#define SH7750_RCR1_A7 SH7750_A7_REG32(SH7750_RCR1_REGOFS) -#define SH7750_RCR1_CF 0x80 /* Carry Flag */ -#define SH7750_RCR1_CIE 0x10 /* Carry Interrupt Enable */ -#define SH7750_RCR1_AIE 0x08 /* Alarm Interrupt Enable */ -#define SH7750_RCR1_AF 0x01 /* Alarm Flag */ - -/* RTC Control Register 2 (byte) - RCR2 */ -#define SH7750_RCR2_REGOFS 0xC8003C /* offset */ -#define SH7750_RCR2 SH7750_P4_REG32(SH7750_RCR2_REGOFS) -#define SH7750_RCR2_A7 SH7750_A7_REG32(SH7750_RCR2_REGOFS) -#define SH7750_RCR2_PEF 0x80 /* Periodic Interrupt Flag */ -#define SH7750_RCR2_PES 0x70 /* Periodic Interrupt Enable: */ -#define SH7750_RCR2_PES_DIS 0x00 /* Periodic Interrupt Disabled */ -#define SH7750_RCR2_PES_DIV256 0x10 /* Generated at 1/256 sec interval */ -#define SH7750_RCR2_PES_DIV64 0x20 /* Generated at 1/64 sec interval */ -#define SH7750_RCR2_PES_DIV16 0x30 /* Generated at 1/16 sec interval */ -#define SH7750_RCR2_PES_DIV4 0x40 /* Generated at 1/4 sec interval */ -#define SH7750_RCR2_PES_DIV2 0x50 /* Generated at 1/2 sec interval */ -#define SH7750_RCR2_PES_x1 0x60 /* Generated at 1 sec interval */ -#define SH7750_RCR2_PES_x2 0x70 /* Generated at 2 sec interval */ -#define SH7750_RCR2_RTCEN 0x08 /* RTC Crystal Oscillator is Operated */ -#define SH7750_RCR2_ADJ 0x04 /* 30-Second Adjastment */ -#define SH7750_RCR2_RESET 0x02 /* Frequency divider circuits are reset*/ -#define SH7750_RCR2_START 0x01 /* 0 - sec, min, hr, day-of-week, month, - year counters are stopped - 1 - sec, min, hr, day-of-week, month, - year counters operate normally */ - - -/* - * Timer Unit (TMU) - */ -/* Timer Output Control Register (byte) - TOCR */ -#define SH7750_TOCR_REGOFS 0xD80000 /* offset */ -#define SH7750_TOCR SH7750_P4_REG32(SH7750_TOCR_REGOFS) -#define SH7750_TOCR_A7 SH7750_A7_REG32(SH7750_TOCR_REGOFS) -#define SH7750_TOCR_TCOE 0x01 /* Timer Clock Pin Control: - 0 - TCLK is used as external clock - input or input capture control - 1 - TCLK is used as on-chip RTC - output clock pin */ - -/* Timer Start Register (byte) - TSTR */ -#define SH7750_TSTR_REGOFS 0xD80004 /* offset */ -#define SH7750_TSTR SH7750_P4_REG32(SH7750_TSTR_REGOFS) -#define SH7750_TSTR_A7 SH7750_A7_REG32(SH7750_TSTR_REGOFS) -#define SH7750_TSTR_STR2 0x04 /* TCNT2 performs count operations */ -#define SH7750_TSTR_STR1 0x02 /* TCNT1 performs count operations */ -#define SH7750_TSTR_STR0 0x01 /* TCNT0 performs count operations */ -#define SH7750_TSTR_STR(n) (1 << (n)) - -/* Timer Constant Register - TCOR0, TCOR1, TCOR2 */ -#define SH7750_TCOR_REGOFS(n) (0xD80008 + ((n)*12)) /* offset */ -#define SH7750_TCOR(n) SH7750_P4_REG32(SH7750_TCOR_REGOFS(n)) -#define SH7750_TCOR_A7(n) SH7750_A7_REG32(SH7750_TCOR_REGOFS(n)) -#define SH7750_TCOR0 SH7750_TCOR(0) -#define SH7750_TCOR1 SH7750_TCOR(1) -#define SH7750_TCOR2 SH7750_TCOR(2) -#define SH7750_TCOR0_A7 SH7750_TCOR_A7(0) -#define SH7750_TCOR1_A7 SH7750_TCOR_A7(1) -#define SH7750_TCOR2_A7 SH7750_TCOR_A7(2) - -/* Timer Counter Register - TCNT0, TCNT1, TCNT2 */ -#define SH7750_TCNT_REGOFS(n) (0xD8000C + ((n)*12)) /* offset */ -#define SH7750_TCNT(n) SH7750_P4_REG32(SH7750_TCNT_REGOFS(n)) -#define SH7750_TCNT_A7(n) SH7750_A7_REG32(SH7750_TCNT_REGOFS(n)) -#define SH7750_TCNT0 SH7750_TCNT(0) -#define SH7750_TCNT1 SH7750_TCNT(1) -#define SH7750_TCNT2 SH7750_TCNT(2) -#define SH7750_TCNT0_A7 SH7750_TCNT_A7(0) -#define SH7750_TCNT1_A7 SH7750_TCNT_A7(1) -#define SH7750_TCNT2_A7 SH7750_TCNT_A7(2) - -/* Timer Control Register (half) - TCR0, TCR1, TCR2 */ -#define SH7750_TCR_REGOFS(n) (0xD80010 + ((n)*12)) /* offset */ -#define SH7750_TCR(n) SH7750_P4_REG32(SH7750_TCR_REGOFS(n)) -#define SH7750_TCR_A7(n) SH7750_A7_REG32(SH7750_TCR_REGOFS(n)) -#define SH7750_TCR0 SH7750_TCR(0) -#define SH7750_TCR1 SH7750_TCR(1) -#define SH7750_TCR2 SH7750_TCR(2) -#define SH7750_TCR0_A7 SH7750_TCR_A7(0) -#define SH7750_TCR1_A7 SH7750_TCR_A7(1) -#define SH7750_TCR2_A7 SH7750_TCR_A7(2) - -#define SH7750_TCR2_ICPF 0x200 /* Input Capture Interrupt Flag - (1 - input capture has occured) */ -#define SH7750_TCR_UNF 0x100 /* Underflow flag */ -#define SH7750_TCR2_ICPE 0x0C0 /* Input Capture Control: */ -#define SH7750_TCR2_ICPE_DIS 0x000 /* Input Capture function is not used*/ -#define SH7750_TCR2_ICPE_NOINT 0x080 /* Input Capture function is used, but - input capture interrupt is not - enabled */ -#define SH7750_TCR2_ICPE_INT 0x0C0 /* Input Capture function is used, - input capture interrupt enabled */ -#define SH7750_TCR_UNIE 0x020 /* Underflow Interrupt Control - (1 - underflow interrupt enabled) */ -#define SH7750_TCR_CKEG 0x018 /* Clock Edge selection: */ -#define SH7750_TCR_CKEG_RAISE 0x000 /* Count/capture on rising edge */ -#define SH7750_TCR_CKEG_FALL 0x008 /* Count/capture on falling edge */ -#define SH7750_TCR_CKEG_BOTH 0x018 /* Count/capture on both rising and - falling edges */ -#define SH7750_TCR_TPSC 0x007 /* Timer prescaler */ -#define SH7750_TCR_TPSC_DIV4 0x000 /* Counts on peripheral clock/4 */ -#define SH7750_TCR_TPSC_DIV16 0x001 /* Counts on peripheral clock/16 */ -#define SH7750_TCR_TPSC_DIV64 0x002 /* Counts on peripheral clock/64 */ -#define SH7750_TCR_TPSC_DIV256 0x003 /* Counts on peripheral clock/256 */ -#define SH7750_TCR_TPSC_DIV1024 0x004 /* Counts on peripheral clock/1024 */ -#define SH7750_TCR_TPSC_RTC 0x006 /* Counts on on-chip RTC output clk*/ -#define SH7750_TCR_TPSC_EXT 0x007 /* Counts on external clock */ - -/* Input Capture Register (read-only) - TCPR2 */ -#define SH7750_TCPR2_REGOFS 0xD8002C /* offset */ -#define SH7750_TCPR2 SH7750_P4_REG32(SH7750_TCPR2_REGOFS) -#define SH7750_TCPR2_A7 SH7750_A7_REG32(SH7750_TCPR2_REGOFS) - -/* - * Bus State Controller - BSC - */ -/* Bus Control Register 1 - BCR1 */ -#define SH7750_BCR1_REGOFS 0x800000 /* offset */ -#define SH7750_BCR1 SH7750_P4_REG32(SH7750_BCR1_REGOFS) -#define SH7750_BCR1_A7 SH7750_A7_REG32(SH7750_BCR1_REGOFS) -#define SH7750_BCR1_ENDIAN 0x80000000 /* Endianness (1 - little endian) */ -#define SH7750_BCR1_MASTER 0x40000000 /* Master/Slave mode (1-master) */ -#define SH7750_BCR1_A0MPX 0x20000000 /* Area 0 Memory Type (0-SRAM,1-MPX)*/ -#define SH7750_BCR1_IPUP 0x02000000 /* Input Pin Pull-up Control: - 0 - pull-up resistor is on for - control input pins - 1 - pull-up resistor is off */ -#define SH7750_BCR1_OPUP 0x01000000 /* Output Pin Pull-up Control: - 0 - pull-up resistor is on for - control output pins - 1 - pull-up resistor is off */ -#define SH7750_BCR1_A1MBC 0x00200000 /* Area 1 SRAM Byte Control Mode: - 0 - Area 1 SRAM is set to - normal mode - 1 - Area 1 SRAM is set to byte - control mode */ -#define SH7750_BCR1_A4MBC 0x00100000 /* Area 4 SRAM Byte Control Mode: - 0 - Area 4 SRAM is set to - normal mode - 1 - Area 4 SRAM is set to byte - control mode */ -#define SH7750_BCR1_BREQEN 0x00080000 /* BREQ Enable: - 0 - External requests are not - accepted - 1 - External requests are - accepted */ -#define SH7750_BCR1_PSHR 0x00040000 /* Partial Sharing Bit: - 0 - Master Mode - 1 - Partial-sharing Mode */ -#define SH7750_BCR1_MEMMPX 0x00020000 /* Area 1 to 6 MPX Interface: - 0 - SRAM/burst ROM interface - 1 - MPX interface */ -#define SH7750_BCR1_HIZMEM 0x00008000 /* High Impendance Control. Specifies - the state of A[25:0], BS\, CSn\, - RD/WR\, CE2A\, CE2B\ in standby - mode and when bus is released: - 0 - signals go to High-Z mode - 1 - signals driven */ -#define SH7750_BCR1_HIZCNT 0x00004000 /* High Impendance Control. Specifies - the state of the RAS\, RAS2\, WEn\, - CASn\, DQMn, RD\, CASS\, FRAME\, - RD2\ signals in standby mode and - when bus is released: - 0 - signals go to High-Z mode - 1 - signals driven */ -#define SH7750_BCR1_A0BST 0x00003800 /* Area 0 Burst ROM Control */ -#define SH7750_BCR1_A0BST_SRAM 0x0000 /* Area 0 accessed as SRAM i/f */ -#define SH7750_BCR1_A0BST_ROM4 0x0800 /* Area 0 accessed as burst ROM - interface, 4 cosequtive access*/ -#define SH7750_BCR1_A0BST_ROM8 0x1000 /* Area 0 accessed as burst ROM - interface, 8 cosequtive access*/ -#define SH7750_BCR1_A0BST_ROM16 0x1800 /* Area 0 accessed as burst ROM - interface, 16 cosequtive access*/ -#define SH7750_BCR1_A0BST_ROM32 0x2000 /* Area 0 accessed as burst ROM - interface, 32 cosequtive access*/ - -#define SH7750_BCR1_A5BST 0x00000700 /* Area 5 Burst ROM Control */ -#define SH7750_BCR1_A5BST_SRAM 0x0000 /* Area 5 accessed as SRAM i/f */ -#define SH7750_BCR1_A5BST_ROM4 0x0100 /* Area 5 accessed as burst ROM - interface, 4 cosequtive access*/ -#define SH7750_BCR1_A5BST_ROM8 0x0200 /* Area 5 accessed as burst ROM - interface, 8 cosequtive access*/ -#define SH7750_BCR1_A5BST_ROM16 0x0300 /* Area 5 accessed as burst ROM - interface, 16 cosequtive access*/ -#define SH7750_BCR1_A5BST_ROM32 0x0400 /* Area 5 accessed as burst ROM - interface, 32 cosequtive access*/ - -#define SH7750_BCR1_A6BST 0x000000E0 /* Area 6 Burst ROM Control */ -#define SH7750_BCR1_A6BST_SRAM 0x0000 /* Area 6 accessed as SRAM i/f */ -#define SH7750_BCR1_A6BST_ROM4 0x0020 /* Area 6 accessed as burst ROM - interface, 4 cosequtive access*/ -#define SH7750_BCR1_A6BST_ROM8 0x0040 /* Area 6 accessed as burst ROM - interface, 8 cosequtive access*/ -#define SH7750_BCR1_A6BST_ROM16 0x0060 /* Area 6 accessed as burst ROM - interface, 16 cosequtive access*/ -#define SH7750_BCR1_A6BST_ROM32 0x0080 /* Area 6 accessed as burst ROM - interface, 32 cosequtive access*/ - -#define SH7750_BCR1_DRAMTP 0x001C /* Area 2 and 3 Memory Type */ -#define SH7750_BCR1_DRAMTP_2SRAM_3SRAM 0x0000 /* Area 2 and 3 are SRAM or MPX - interface. */ -#define SH7750_BCR1_DRAMTP_2SRAM_3SDRAM 0x0008 /* Area 2 - SRAM/MPX, Area 3 - - synchronous DRAM */ -#define SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM 0x000C /* Area 2 and 3 are synchronous - DRAM interface */ -#define SH7750_BCR1_DRAMTP_2SRAM_3DRAM 0x0010 /* Area 2 - SRAM/MPX, Area 3 - - DRAM interface */ -#define SH7750_BCR1_DRAMTP_2DRAM_3DRAM 0x0014 /* Area 2 and 3 are DRAM - interface */ - -#define SH7750_BCR1_A56PCM 0x00000001 /* Area 5 and 6 Bus Type: - 0 - SRAM interface - 1 - PCMCIA interface */ - -/* Bus Control Register 2 (half) - BCR2 */ -#define SH7750_BCR2_REGOFS 0x800004 /* offset */ -#define SH7750_BCR2 SH7750_P4_REG32(SH7750_BCR2_REGOFS) -#define SH7750_BCR2_A7 SH7750_A7_REG32(SH7750_BCR2_REGOFS) - -#define SH7750_BCR2_A0SZ 0xC000 /* Area 0 Bus Width */ -#define SH7750_BCR2_A0SZ_S 14 -#define SH7750_BCR2_A6SZ 0x3000 /* Area 6 Bus Width */ -#define SH7750_BCR2_A6SZ_S 12 -#define SH7750_BCR2_A5SZ 0x0C00 /* Area 5 Bus Width */ -#define SH7750_BCR2_A5SZ_S 10 -#define SH7750_BCR2_A4SZ 0x0300 /* Area 4 Bus Width */ -#define SH7750_BCR2_A4SZ_S 8 -#define SH7750_BCR2_A3SZ 0x00C0 /* Area 3 Bus Width */ -#define SH7750_BCR2_A3SZ_S 6 -#define SH7750_BCR2_A2SZ 0x0030 /* Area 2 Bus Width */ -#define SH7750_BCR2_A2SZ_S 4 -#define SH7750_BCR2_A1SZ 0x000C /* Area 1 Bus Width */ -#define SH7750_BCR2_A1SZ_S 2 -#define SH7750_BCR2_SZ_64 0 /* 64 bits */ -#define SH7750_BCR2_SZ_8 1 /* 8 bits */ -#define SH7750_BCR2_SZ_16 2 /* 16 bits */ -#define SH7750_BCR2_SZ_32 3 /* 32 bits */ -#define SH7750_BCR2_PORTEN 0x0001 /* Port Function Enable : - 0 - D51-D32 are not used as a port - 1 - D51-D32 are used as a port */ - -/* Wait Control Register 1 - WCR1 */ -#define SH7750_WCR1_REGOFS 0x800008 /* offset */ -#define SH7750_WCR1 SH7750_P4_REG32(SH7750_WCR1_REGOFS) -#define SH7750_WCR1_A7 SH7750_A7_REG32(SH7750_WCR1_REGOFS) -#define SH7750_WCR1_DMAIW 0x70000000 /* DACK Device Inter-Cycle Idle - specification */ -#define SH7750_WCR1_DMAIW_S 28 -#define SH7750_WCR1_A6IW 0x07000000 /* Area 6 Inter-Cycle Idle spec. */ -#define SH7750_WCR1_A6IW_S 24 -#define SH7750_WCR1_A5IW 0x00700000 /* Area 5 Inter-Cycle Idle spec. */ -#define SH7750_WCR1_A5IW_S 20 -#define SH7750_WCR1_A4IW 0x00070000 /* Area 4 Inter-Cycle Idle spec. */ -#define SH7750_WCR1_A4IW_S 16 -#define SH7750_WCR1_A3IW 0x00007000 /* Area 3 Inter-Cycle Idle spec. */ -#define SH7750_WCR1_A3IW_S 12 -#define SH7750_WCR1_A2IW 0x00000700 /* Area 2 Inter-Cycle Idle spec. */ -#define SH7750_WCR1_A2IW_S 8 -#define SH7750_WCR1_A1IW 0x00000070 /* Area 1 Inter-Cycle Idle spec. */ -#define SH7750_WCR1_A1IW_S 4 -#define SH7750_WCR1_A0IW 0x00000007 /* Area 0 Inter-Cycle Idle spec. */ -#define SH7750_WCR1_A0IW_S 0 - -/* Wait Control Register 2 - WCR2 */ -#define SH7750_WCR2_REGOFS 0x80000C /* offset */ -#define SH7750_WCR2 SH7750_P4_REG32(SH7750_WCR2_REGOFS) -#define SH7750_WCR2_A7 SH7750_A7_REG32(SH7750_WCR2_REGOFS) - -#define SH7750_WCR2_A6W 0xE0000000 /* Area 6 Wait Control */ -#define SH7750_WCR2_A6W_S 29 -#define SH7750_WCR2_A6B 0x1C000000 /* Area 6 Burst Pitch */ -#define SH7750_WCR2_A6B_S 26 -#define SH7750_WCR2_A5W 0x03800000 /* Area 5 Wait Control */ -#define SH7750_WCR2_A5W_S 23 -#define SH7750_WCR2_A5B 0x00700000 /* Area 5 Burst Pitch */ -#define SH7750_WCR2_A5B_S 20 -#define SH7750_WCR2_A4W 0x000E0000 /* Area 4 Wait Control */ -#define SH7750_WCR2_A4W_S 17 -#define SH7750_WCR2_A3W 0x0000E000 /* Area 3 Wait Control */ -#define SH7750_WCR2_A3W_S 13 -#define SH7750_WCR2_A2W 0x00000E00 /* Area 2 Wait Control */ -#define SH7750_WCR2_A2W_S 9 -#define SH7750_WCR2_A1W 0x000001C0 /* Area 1 Wait Control */ -#define SH7750_WCR2_A1W_S 6 -#define SH7750_WCR2_A0W 0x00000038 /* Area 0 Wait Control */ -#define SH7750_WCR2_A0W_S 3 -#define SH7750_WCR2_A0B 0x00000007 /* Area 0 Burst Pitch */ -#define SH7750_WCR2_A0B_S 0 - -#define SH7750_WCR2_WS0 0 /* 0 wait states inserted */ -#define SH7750_WCR2_WS1 1 /* 1 wait states inserted */ -#define SH7750_WCR2_WS2 2 /* 2 wait states inserted */ -#define SH7750_WCR2_WS3 3 /* 3 wait states inserted */ -#define SH7750_WCR2_WS6 4 /* 6 wait states inserted */ -#define SH7750_WCR2_WS9 5 /* 9 wait states inserted */ -#define SH7750_WCR2_WS12 6 /* 12 wait states inserted */ -#define SH7750_WCR2_WS15 7 /* 15 wait states inserted */ - -#define SH7750_WCR2_BPWS0 0 /* 0 wait states inserted from 2nd access */ -#define SH7750_WCR2_BPWS1 1 /* 1 wait states inserted from 2nd access */ -#define SH7750_WCR2_BPWS2 2 /* 2 wait states inserted from 2nd access */ -#define SH7750_WCR2_BPWS3 3 /* 3 wait states inserted from 2nd access */ -#define SH7750_WCR2_BPWS4 4 /* 4 wait states inserted from 2nd access */ -#define SH7750_WCR2_BPWS5 5 /* 5 wait states inserted from 2nd access */ -#define SH7750_WCR2_BPWS6 6 /* 6 wait states inserted from 2nd access */ -#define SH7750_WCR2_BPWS7 7 /* 7 wait states inserted from 2nd access */ - -/* DRAM CAS\ Assertion Delay (area 3,2) */ -#define SH7750_WCR2_DRAM_CAS_ASW1 0 /* 1 cycle */ -#define SH7750_WCR2_DRAM_CAS_ASW2 1 /* 2 cycles */ -#define SH7750_WCR2_DRAM_CAS_ASW3 2 /* 3 cycles */ -#define SH7750_WCR2_DRAM_CAS_ASW4 3 /* 4 cycles */ -#define SH7750_WCR2_DRAM_CAS_ASW7 4 /* 7 cycles */ -#define SH7750_WCR2_DRAM_CAS_ASW10 5 /* 10 cycles */ -#define SH7750_WCR2_DRAM_CAS_ASW13 6 /* 13 cycles */ -#define SH7750_WCR2_DRAM_CAS_ASW16 7 /* 16 cycles */ - -/* SDRAM CAS\ Latency Cycles */ -#define SH7750_WCR2_SDRAM_CAS_LAT1 1 /* 1 cycle */ -#define SH7750_WCR2_SDRAM_CAS_LAT2 2 /* 2 cycles */ -#define SH7750_WCR2_SDRAM_CAS_LAT3 3 /* 3 cycles */ -#define SH7750_WCR2_SDRAM_CAS_LAT4 4 /* 4 cycles */ -#define SH7750_WCR2_SDRAM_CAS_LAT5 5 /* 5 cycles */ - -/* Wait Control Register 3 - WCR3 */ -#define SH7750_WCR3_REGOFS 0x800010 /* offset */ -#define SH7750_WCR3 SH7750_P4_REG32(SH7750_WCR3_REGOFS) -#define SH7750_WCR3_A7 SH7750_A7_REG32(SH7750_WCR3_REGOFS) - -#define SH7750_WCR3_A6S 0x04000000 /* Area 6 Write Strobe Setup time */ -#define SH7750_WCR3_A6H 0x03000000 /* Area 6 Data Hold Time */ -#define SH7750_WCR3_A6H_S 24 -#define SH7750_WCR3_A5S 0x00400000 /* Area 5 Write Strobe Setup time */ -#define SH7750_WCR3_A5H 0x00300000 /* Area 5 Data Hold Time */ -#define SH7750_WCR3_A5H_S 20 -#define SH7750_WCR3_A4S 0x00040000 /* Area 4 Write Strobe Setup time */ -#define SH7750_WCR3_A4H 0x00030000 /* Area 4 Data Hold Time */ -#define SH7750_WCR3_A4H_S 16 -#define SH7750_WCR3_A3S 0x00004000 /* Area 3 Write Strobe Setup time */ -#define SH7750_WCR3_A3H 0x00003000 /* Area 3 Data Hold Time */ -#define SH7750_WCR3_A3H_S 12 -#define SH7750_WCR3_A2S 0x00000400 /* Area 2 Write Strobe Setup time */ -#define SH7750_WCR3_A2H 0x00000300 /* Area 2 Data Hold Time */ -#define SH7750_WCR3_A2H_S 8 -#define SH7750_WCR3_A1S 0x00000040 /* Area 1 Write Strobe Setup time */ -#define SH7750_WCR3_A1H 0x00000030 /* Area 1 Data Hold Time */ -#define SH7750_WCR3_A1H_S 4 -#define SH7750_WCR3_A0S 0x00000004 /* Area 0 Write Strobe Setup time */ -#define SH7750_WCR3_A0H 0x00000003 /* Area 0 Data Hold Time */ -#define SH7750_WCR3_A0H_S 0 - -#define SH7750_WCR3_DHWS_0 0 /* 0 wait states data hold time */ -#define SH7750_WCR3_DHWS_1 1 /* 1 wait states data hold time */ -#define SH7750_WCR3_DHWS_2 2 /* 2 wait states data hold time */ -#define SH7750_WCR3_DHWS_3 3 /* 3 wait states data hold time */ - -#define SH7750_MCR_REGOFS 0x800014 /* offset */ -#define SH7750_MCR SH7750_P4_REG32(SH7750_MCR_REGOFS) -#define SH7750_MCR_A7 SH7750_A7_REG32(SH7750_MCR_REGOFS) - -#define SH7750_MCR_RASD 0x80000000 /* RAS Down mode */ -#define SH7750_MCR_MRSET 0x40000000 /* SDRAM Mode Register Set */ -#define SH7750_MCR_PALL 0x00000000 /* SDRAM Precharge All cmd. Mode */ -#define SH7750_MCR_TRC 0x38000000 /* RAS Precharge Time at End of - Refresh: */ -#define SH7750_MCR_TRC_0 0x00000000 /* 0 */ -#define SH7750_MCR_TRC_3 0x08000000 /* 3 */ -#define SH7750_MCR_TRC_6 0x10000000 /* 6 */ -#define SH7750_MCR_TRC_9 0x18000000 /* 9 */ -#define SH7750_MCR_TRC_12 0x20000000 /* 12 */ -#define SH7750_MCR_TRC_15 0x28000000 /* 15 */ -#define SH7750_MCR_TRC_18 0x30000000 /* 18 */ -#define SH7750_MCR_TRC_21 0x38000000 /* 21 */ - -#define SH7750_MCR_TCAS 0x00800000 /* CAS Negation Period */ -#define SH7750_MCR_TCAS_1 0x00000000 /* 1 */ -#define SH7750_MCR_TCAS_2 0x00800000 /* 2 */ - -#define SH7750_MCR_TPC 0x00380000 /* DRAM: RAS Precharge Period - SDRAM: minimum number of cycles - until the next bank active cmd - is output after precharging */ -#define SH7750_MCR_TPC_S 19 -#define SH7750_MCR_TPC_SDRAM_1 0x00000000 /* 1 cycle */ -#define SH7750_MCR_TPC_SDRAM_2 0x00080000 /* 2 cycles */ -#define SH7750_MCR_TPC_SDRAM_3 0x00100000 /* 3 cycles */ -#define SH7750_MCR_TPC_SDRAM_4 0x00180000 /* 4 cycles */ -#define SH7750_MCR_TPC_SDRAM_5 0x00200000 /* 5 cycles */ -#define SH7750_MCR_TPC_SDRAM_6 0x00280000 /* 6 cycles */ -#define SH7750_MCR_TPC_SDRAM_7 0x00300000 /* 7 cycles */ -#define SH7750_MCR_TPC_SDRAM_8 0x00380000 /* 8 cycles */ - -#define SH7750_MCR_RCD 0x00030000 /* DRAM: RAS-CAS Assertion Delay time - SDRAM: bank active-read/write cmd - delay time */ -#define SH7750_MCR_RCD_DRAM_2 0x00000000 /* DRAM delay 2 clocks */ -#define SH7750_MCR_RCD_DRAM_3 0x00010000 /* DRAM delay 3 clocks */ -#define SH7750_MCR_RCD_DRAM_4 0x00020000 /* DRAM delay 4 clocks */ -#define SH7750_MCR_RCD_DRAM_5 0x00030000 /* DRAM delay 5 clocks */ -#define SH7750_MCR_RCD_SDRAM_2 0x00010000 /* DRAM delay 2 clocks */ -#define SH7750_MCR_RCD_SDRAM_3 0x00020000 /* DRAM delay 3 clocks */ -#define SH7750_MCR_RCD_SDRAM_4 0x00030000 /* DRAM delay 4 clocks */ - -#define SH7750_MCR_TRWL 0x0000E000 /* SDRAM Write Precharge Delay */ -#define SH7750_MCR_TRWL_1 0x00000000 /* 1 */ -#define SH7750_MCR_TRWL_2 0x00002000 /* 2 */ -#define SH7750_MCR_TRWL_3 0x00004000 /* 3 */ -#define SH7750_MCR_TRWL_4 0x00006000 /* 4 */ -#define SH7750_MCR_TRWL_5 0x00008000 /* 5 */ - -#define SH7750_MCR_TRAS 0x00001C00 /* DRAM: CAS-Before-RAS Refresh RAS - asserting period - SDRAM: Command interval after - synchronous DRAM refresh */ -#define SH7750_MCR_TRAS_DRAM_2 0x00000000 /* 2 */ -#define SH7750_MCR_TRAS_DRAM_3 0x00000400 /* 3 */ -#define SH7750_MCR_TRAS_DRAM_4 0x00000800 /* 4 */ -#define SH7750_MCR_TRAS_DRAM_5 0x00000C00 /* 5 */ -#define SH7750_MCR_TRAS_DRAM_6 0x00001000 /* 6 */ -#define SH7750_MCR_TRAS_DRAM_7 0x00001400 /* 7 */ -#define SH7750_MCR_TRAS_DRAM_8 0x00001800 /* 8 */ -#define SH7750_MCR_TRAS_DRAM_9 0x00001C00 /* 9 */ - -#define SH7750_MCR_TRAS_SDRAM_TRC_4 0x00000000 /* 4 + TRC */ -#define SH7750_MCR_TRAS_SDRAM_TRC_5 0x00000400 /* 5 + TRC */ -#define SH7750_MCR_TRAS_SDRAM_TRC_6 0x00000800 /* 6 + TRC */ -#define SH7750_MCR_TRAS_SDRAM_TRC_7 0x00000C00 /* 7 + TRC */ -#define SH7750_MCR_TRAS_SDRAM_TRC_8 0x00001000 /* 8 + TRC */ -#define SH7750_MCR_TRAS_SDRAM_TRC_9 0x00001400 /* 9 + TRC */ -#define SH7750_MCR_TRAS_SDRAM_TRC_10 0x00001800 /* 10 + TRC */ -#define SH7750_MCR_TRAS_SDRAM_TRC_11 0x00001C00 /* 11 + TRC */ - -#define SH7750_MCR_BE 0x00000200 /* Burst Enable */ -#define SH7750_MCR_SZ 0x00000180 /* Memory Data Size */ -#define SH7750_MCR_SZ_64 0x00000000 /* 64 bits */ -#define SH7750_MCR_SZ_16 0x00000100 /* 16 bits */ -#define SH7750_MCR_SZ_32 0x00000180 /* 32 bits */ - -#define SH7750_MCR_AMX 0x00000078 /* Address Multiplexing */ -#define SH7750_MCR_AMX_S 3 -#define SH7750_MCR_AMX_DRAM_8BIT_COL 0x00000000 /* 8-bit column addr */ -#define SH7750_MCR_AMX_DRAM_9BIT_COL 0x00000008 /* 9-bit column addr */ -#define SH7750_MCR_AMX_DRAM_10BIT_COL 0x00000010 /* 10-bit column addr */ -#define SH7750_MCR_AMX_DRAM_11BIT_COL 0x00000018 /* 11-bit column addr */ -#define SH7750_MCR_AMX_DRAM_12BIT_COL 0x00000020 /* 12-bit column addr */ -/* See SH7750 Hardware Manual for SDRAM address multiplexor selection */ - -#define SH7750_MCR_RFSH 0x00000004 /* Refresh Control */ -#define SH7750_MCR_RMODE 0x00000002 /* Refresh Mode: */ -#define SH7750_MCR_RMODE_NORMAL 0x00000000 /* Normal Refresh Mode */ -#define SH7750_MCR_RMODE_SELF 0x00000002 /* Self-Refresh Mode */ -#define SH7750_MCR_RMODE_EDO 0x00000001 /* EDO Mode */ - -/* SDRAM Mode Set address */ -#define SH7750_SDRAM_MODE_A2_BASE 0xFF900000 -#define SH7750_SDRAM_MODE_A3_BASE 0xFF940000 -#define SH7750_SDRAM_MODE_A2_32BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 2)) -#define SH7750_SDRAM_MODE_A3_32BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 2)) -#define SH7750_SDRAM_MODE_A2_64BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 3)) -#define SH7750_SDRAM_MODE_A3_64BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 3)) - - -/* PCMCIA Control Register (half) - PCR */ -#define SH7750_PCR_REGOFS 0x800018 /* offset */ -#define SH7750_PCR SH7750_P4_REG32(SH7750_PCR_REGOFS) -#define SH7750_PCR_A7 SH7750_A7_REG32(SH7750_PCR_REGOFS) - -#define SH7750_PCR_A5PCW 0xC000 /* Area 5 PCMCIA Wait - Number of wait - states to be added to the number of - waits specified by WCR2 in a low-speed - PCMCIA wait cycle */ -#define SH7750_PCR_A5PCW_0 0x0000 /* 0 waits inserted */ -#define SH7750_PCR_A5PCW_15 0x4000 /* 15 waits inserted */ -#define SH7750_PCR_A5PCW_30 0x8000 /* 30 waits inserted */ -#define SH7750_PCR_A5PCW_50 0xC000 /* 50 waits inserted */ - -#define SH7750_PCR_A6PCW 0x3000 /* Area 6 PCMCIA Wait - Number of wait - states to be added to the number of - waits specified by WCR2 in a low-speed - PCMCIA wait cycle */ -#define SH7750_PCR_A6PCW_0 0x0000 /* 0 waits inserted */ -#define SH7750_PCR_A6PCW_15 0x1000 /* 15 waits inserted */ -#define SH7750_PCR_A6PCW_30 0x2000 /* 30 waits inserted */ -#define SH7750_PCR_A6PCW_50 0x3000 /* 50 waits inserted */ - -#define SH7750_PCR_A5TED 0x0E00 /* Area 5 Address-OE\/WE\ Assertion Delay, - delay time from address output to - OE\/WE\ assertion on the connected - PCMCIA interface */ -#define SH7750_PCR_A5TED_S 9 -#define SH7750_PCR_A6TED 0x01C0 /* Area 6 Address-OE\/WE\ Assertion Delay*/ -#define SH7750_PCR_A6TED_S 6 - -#define SH7750_PCR_TED_0WS 0 /* 0 Waits inserted */ -#define SH7750_PCR_TED_1WS 1 /* 1 Waits inserted */ -#define SH7750_PCR_TED_2WS 2 /* 2 Waits inserted */ -#define SH7750_PCR_TED_3WS 3 /* 3 Waits inserted */ -#define SH7750_PCR_TED_6WS 4 /* 6 Waits inserted */ -#define SH7750_PCR_TED_9WS 5 /* 9 Waits inserted */ -#define SH7750_PCR_TED_12WS 6 /* 12 Waits inserted */ -#define SH7750_PCR_TED_15WS 7 /* 15 Waits inserted */ - -#define SH7750_PCR_A5TEH 0x0038 /* Area 5 OE\/WE\ Negation Address delay, - address hold delay time from OE\/WE\ - negation in a write on the connected - PCMCIA interface */ -#define SH7750_PCR_A5TEH_S 3 - -#define SH7750_PCR_A6TEH 0x0007 /* Area 6 OE\/WE\ Negation Address delay*/ -#define SH7750_PCR_A6TEH_S 0 - -#define SH7750_PCR_TEH_0WS 0 /* 0 Waits inserted */ -#define SH7750_PCR_TEH_1WS 1 /* 1 Waits inserted */ -#define SH7750_PCR_TEH_2WS 2 /* 2 Waits inserted */ -#define SH7750_PCR_TEH_3WS 3 /* 3 Waits inserted */ -#define SH7750_PCR_TEH_6WS 4 /* 6 Waits inserted */ -#define SH7750_PCR_TEH_9WS 5 /* 9 Waits inserted */ -#define SH7750_PCR_TEH_12WS 6 /* 12 Waits inserted */ -#define SH7750_PCR_TEH_15WS 7 /* 15 Waits inserted */ - -/* Refresh Timer Control/Status Register (half) - RTSCR */ -#define SH7750_RTCSR_REGOFS 0x80001C /* offset */ -#define SH7750_RTCSR SH7750_P4_REG32(SH7750_RTCSR_REGOFS) -#define SH7750_RTCSR_A7 SH7750_A7_REG32(SH7750_RTCSR_REGOFS) - -#define SH7750_RTCSR_KEY 0xA500 /* RTCSR write key */ -#define SH7750_RTCSR_CMF 0x0080 /* Compare-Match Flag (indicates a - match between the refresh timer - counter and refresh time constant) */ -#define SH7750_RTCSR_CMIE 0x0040 /* Compare-Match Interrupt Enable */ -#define SH7750_RTCSR_CKS 0x0038 /* Refresh Counter Clock Selects */ -#define SH7750_RTCSR_CKS_DIS 0x0000 /* Clock Input Disabled */ -#define SH7750_RTCSR_CKS_CKIO_DIV4 0x0008 /* Bus Clock / 4 */ -#define SH7750_RTCSR_CKS_CKIO_DIV16 0x0010 /* Bus Clock / 16 */ -#define SH7750_RTCSR_CKS_CKIO_DIV64 0x0018 /* Bus Clock / 64 */ -#define SH7750_RTCSR_CKS_CKIO_DIV256 0x0020 /* Bus Clock / 256 */ -#define SH7750_RTCSR_CKS_CKIO_DIV1024 0x0028 /* Bus Clock / 1024 */ -#define SH7750_RTCSR_CKS_CKIO_DIV2048 0x0030 /* Bus Clock / 2048 */ -#define SH7750_RTCSR_CKS_CKIO_DIV4096 0x0038 /* Bus Clock / 4096 */ - -#define SH7750_RTCSR_OVF 0x0004 /* Refresh Count Overflow Flag */ -#define SH7750_RTCSR_OVIE 0x0002 /* Refresh Count Overflow Interrupt - Enable */ -#define SH7750_RTCSR_LMTS 0x0001 /* Refresh Count Overflow Limit Select */ -#define SH7750_RTCSR_LMTS_1024 0x0000 /* Count Limit is 1024 */ -#define SH7750_RTCSR_LMTS_512 0x0001 /* Count Limit is 512 */ - -/* Refresh Timer Counter (half) - RTCNT */ -#define SH7750_RTCNT_REGOFS 0x800020 /* offset */ -#define SH7750_RTCNT SH7750_P4_REG32(SH7750_RTCNT_REGOFS) -#define SH7750_RTCNT_A7 SH7750_A7_REG32(SH7750_RTCNT_REGOFS) - -#define SH7750_RTCNT_KEY 0xA500 /* RTCNT write key */ - -/* Refresh Time Constant Register (half) - RTCOR */ -#define SH7750_RTCOR_REGOFS 0x800024 /* offset */ -#define SH7750_RTCOR SH7750_P4_REG32(SH7750_RTCOR_REGOFS) -#define SH7750_RTCOR_A7 SH7750_A7_REG32(SH7750_RTCOR_REGOFS) - -#define SH7750_RTCOR_KEY 0xA500 /* RTCOR write key */ - -/* Refresh Count Register (half) - RFCR */ -#define SH7750_RFCR_REGOFS 0x800028 /* offset */ -#define SH7750_RFCR SH7750_P4_REG32(SH7750_RFCR_REGOFS) -#define SH7750_RFCR_A7 SH7750_A7_REG32(SH7750_RFCR_REGOFS) - -#define SH7750_RFCR_KEY 0xA400 /* RFCR write key */ - -/* - * Direct Memory Access Controller (DMAC) - */ - -/* DMA Source Address Register - SAR0, SAR1, SAR2, SAR3 */ -#define SH7750_SAR_REGOFS(n) (0xA00000 + ((n)*16)) /* offset */ -#define SH7750_SAR(n) SH7750_P4_REG32(SH7750_SAR_REGOFS(n)) -#define SH7750_SAR_A7(n) SH7750_A7_REG32(SH7750_SAR_REGOFS(n)) -#define SH7750_SAR0 SH7750_SAR(0) -#define SH7750_SAR1 SH7750_SAR(1) -#define SH7750_SAR2 SH7750_SAR(2) -#define SH7750_SAR3 SH7750_SAR(3) -#define SH7750_SAR0_A7 SH7750_SAR_A7(0) -#define SH7750_SAR1_A7 SH7750_SAR_A7(1) -#define SH7750_SAR2_A7 SH7750_SAR_A7(2) -#define SH7750_SAR3_A7 SH7750_SAR_A7(3) - -/* DMA Destination Address Register - DAR0, DAR1, DAR2, DAR3 */ -#define SH7750_DAR_REGOFS(n) (0xA00004 + ((n)*16)) /* offset */ -#define SH7750_DAR(n) SH7750_P4_REG32(SH7750_DAR_REGOFS(n)) -#define SH7750_DAR_A7(n) SH7750_A7_REG32(SH7750_DAR_REGOFS(n)) -#define SH7750_DAR0 SH7750_DAR(0) -#define SH7750_DAR1 SH7750_DAR(1) -#define SH7750_DAR2 SH7750_DAR(2) -#define SH7750_DAR3 SH7750_DAR(3) -#define SH7750_DAR0_A7 SH7750_DAR_A7(0) -#define SH7750_DAR1_A7 SH7750_DAR_A7(1) -#define SH7750_DAR2_A7 SH7750_DAR_A7(2) -#define SH7750_DAR3_A7 SH7750_DAR_A7(3) - -/* DMA Transfer Count Register - DMATCR0, DMATCR1, DMATCR2, DMATCR3 */ -#define SH7750_DMATCR_REGOFS(n) (0xA00008 + ((n)*16)) /* offset */ -#define SH7750_DMATCR(n) SH7750_P4_REG32(SH7750_DMATCR_REGOFS(n)) -#define SH7750_DMATCR_A7(n) SH7750_A7_REG32(SH7750_DMATCR_REGOFS(n)) -#define SH7750_DMATCR0_P4 SH7750_DMATCR(0) -#define SH7750_DMATCR1_P4 SH7750_DMATCR(1) -#define SH7750_DMATCR2_P4 SH7750_DMATCR(2) -#define SH7750_DMATCR3_P4 SH7750_DMATCR(3) -#define SH7750_DMATCR0_A7 SH7750_DMATCR_A7(0) -#define SH7750_DMATCR1_A7 SH7750_DMATCR_A7(1) -#define SH7750_DMATCR2_A7 SH7750_DMATCR_A7(2) -#define SH7750_DMATCR3_A7 SH7750_DMATCR_A7(3) - -/* DMA Channel Control Register - CHCR0, CHCR1, CHCR2, CHCR3 */ -#define SH7750_CHCR_REGOFS(n) (0xA0000C + ((n)*16)) /* offset */ -#define SH7750_CHCR(n) SH7750_P4_REG32(SH7750_CHCR_REGOFS(n)) -#define SH7750_CHCR_A7(n) SH7750_A7_REG32(SH7750_CHCR_REGOFS(n)) -#define SH7750_CHCR0 SH7750_CHCR(0) -#define SH7750_CHCR1 SH7750_CHCR(1) -#define SH7750_CHCR2 SH7750_CHCR(2) -#define SH7750_CHCR3 SH7750_CHCR(3) -#define SH7750_CHCR0_A7 SH7750_CHCR_A7(0) -#define SH7750_CHCR1_A7 SH7750_CHCR_A7(1) -#define SH7750_CHCR2_A7 SH7750_CHCR_A7(2) -#define SH7750_CHCR3_A7 SH7750_CHCR_A7(3) - -#define SH7750_CHCR_SSA 0xE0000000 /* Source Address Space Attribute */ -#define SH7750_CHCR_SSA_PCMCIA 0x00000000 /* Reserved in PCMCIA access */ -#define SH7750_CHCR_SSA_DYNBSZ 0x20000000 /* Dynamic Bus Sizing I/O space */ -#define SH7750_CHCR_SSA_IO8 0x40000000 /* 8-bit I/O space */ -#define SH7750_CHCR_SSA_IO16 0x60000000 /* 16-bit I/O space */ -#define SH7750_CHCR_SSA_CMEM8 0x80000000 /* 8-bit common memory space */ -#define SH7750_CHCR_SSA_CMEM16 0xA0000000 /* 16-bit common memory space */ -#define SH7750_CHCR_SSA_AMEM8 0xC0000000 /* 8-bit attribute memory space */ -#define SH7750_CHCR_SSA_AMEM16 0xE0000000 /* 16-bit attribute memory space */ - -#define SH7750_CHCR_STC 0x10000000 /* Source Address Wait Control Select, - specifies CS5 or CS6 space wait - control for PCMCIA access */ - -#define SH7750_CHCR_DSA 0x0E000000 /* Source Address Space Attribute */ -#define SH7750_CHCR_DSA_PCMCIA 0x00000000 /* Reserved in PCMCIA access */ -#define SH7750_CHCR_DSA_DYNBSZ 0x02000000 /* Dynamic Bus Sizing I/O space */ -#define SH7750_CHCR_DSA_IO8 0x04000000 /* 8-bit I/O space */ -#define SH7750_CHCR_DSA_IO16 0x06000000 /* 16-bit I/O space */ -#define SH7750_CHCR_DSA_CMEM8 0x08000000 /* 8-bit common memory space */ -#define SH7750_CHCR_DSA_CMEM16 0x0A000000 /* 16-bit common memory space */ -#define SH7750_CHCR_DSA_AMEM8 0x0C000000 /* 8-bit attribute memory space */ -#define SH7750_CHCR_DSA_AMEM16 0x0E000000 /* 16-bit attribute memory space */ - -#define SH7750_CHCR_DTC 0x01000000 /* Destination Address Wait Control - Select, specifies CS5 or CS6 - space wait control for PCMCIA - access */ - -#define SH7750_CHCR_DS 0x00080000 /* DREQ\ Select : */ -#define SH7750_CHCR_DS_LOWLVL 0x00000000 /* Low Level Detection */ -#define SH7750_CHCR_DS_FALL 0x00080000 /* Falling Edge Detection */ - -#define SH7750_CHCR_RL 0x00040000 /* Request Check Level: */ -#define SH7750_CHCR_RL_ACTH 0x00000000 /* DRAK is an active high out */ -#define SH7750_CHCR_RL_ACTL 0x00040000 /* DRAK is an active low out */ - -#define SH7750_CHCR_AM 0x00020000 /* Acknowledge Mode: */ -#define SH7750_CHCR_AM_RD 0x00000000 /* DACK is output in read cycle */ -#define SH7750_CHCR_AM_WR 0x00020000 /* DACK is output in write cycle*/ - -#define SH7750_CHCR_AL 0x00010000 /* Acknowledge Level: */ -#define SH7750_CHCR_AL_ACTH 0x00000000 /* DACK is an active high out */ -#define SH7750_CHCR_AL_ACTL 0x00010000 /* DACK is an active low out */ - -#define SH7750_CHCR_DM 0x0000C000 /* Destination Address Mode: */ -#define SH7750_CHCR_DM_FIX 0x00000000 /* Destination Addr Fixed */ -#define SH7750_CHCR_DM_INC 0x00004000 /* Destination Addr Incremented */ -#define SH7750_CHCR_DM_DEC 0x00008000 /* Destination Addr Decremented */ - -#define SH7750_CHCR_SM 0x00003000 /* Source Address Mode: */ -#define SH7750_CHCR_SM_FIX 0x00000000 /* Source Addr Fixed */ -#define SH7750_CHCR_SM_INC 0x00001000 /* Source Addr Incremented */ -#define SH7750_CHCR_SM_DEC 0x00002000 /* Source Addr Decremented */ - -#define SH7750_CHCR_RS 0x00000F00 /* Request Source Select: */ -#define SH7750_CHCR_RS_ER_DA_EA_TO_EA 0x000 /* External Request, Dual Address - Mode (External Addr Space-> - External Addr Space) */ -#define SH7750_CHCR_RS_ER_SA_EA_TO_ED 0x200 /* External Request, Single - Address Mode (External Addr - Space -> External Device) */ -#define SH7750_CHCR_RS_ER_SA_ED_TO_EA 0x300 /* External Request, Single - Address Mode, (External - Device -> External Addr - Space)*/ -#define SH7750_CHCR_RS_AR_EA_TO_EA 0x400 /* Auto-Request (External Addr - Space -> External Addr Space)*/ - -#define SH7750_CHCR_RS_AR_EA_TO_OCP 0x500 /* Auto-Request (External Addr - Space -> On-chip Peripheral - Module) */ -#define SH7750_CHCR_RS_AR_OCP_TO_EA 0x600 /* Auto-Request (On-chip - Peripheral Module -> - External Addr Space */ -#define SH7750_CHCR_RS_SCITX_EA_TO_SC 0x800 /* SCI Transmit-Data-Empty intr - transfer request (external - address space -> SCTDR1) */ -#define SH7750_CHCR_RS_SCIRX_SC_TO_EA 0x900 /* SCI Receive-Data-Full intr - transfer request (SCRDR1 -> - External Addr Space) */ -#define SH7750_CHCR_RS_SCIFTX_EA_TO_SC 0xA00 /* SCIF Transmit-Data-Empty intr - transfer request (external - address space -> SCFTDR1) */ -#define SH7750_CHCR_RS_SCIFRX_SC_TO_EA 0xB00 /* SCIF Receive-Data-Full intr - transfer request (SCFRDR2 -> - External Addr Space) */ -#define SH7750_CHCR_RS_TMU2_EA_TO_EA 0xC00 /* TMU Channel 2 (input capture - interrupt), (external address - space -> external address - space) */ -#define SH7750_CHCR_RS_TMU2_EA_TO_OCP 0xD00 /* TMU Channel 2 (input capture - interrupt), (external address - space -> on-chip peripheral - module) */ -#define SH7750_CHCR_RS_TMU2_OCP_TO_EA 0xE00 /* TMU Channel 2 (input capture - interrupt), (on-chip - peripheral module -> external - address space) */ - -#define SH7750_CHCR_TM 0x00000080 /* Transmit mode: */ -#define SH7750_CHCR_TM_CSTEAL 0x00000000 /* Cycle Steal Mode */ -#define SH7750_CHCR_TM_BURST 0x00000080 /* Burst Mode */ - -#define SH7750_CHCR_TS 0x00000070 /* Transmit Size: */ -#define SH7750_CHCR_TS_QUAD 0x00000000 /* Quadword Size (64 bits) */ -#define SH7750_CHCR_TS_BYTE 0x00000010 /* Byte Size (8 bit) */ -#define SH7750_CHCR_TS_WORD 0x00000020 /* Word Size (16 bit) */ -#define SH7750_CHCR_TS_LONG 0x00000030 /* Longword Size (32 bit) */ -#define SH7750_CHCR_TS_BLOCK 0x00000040 /* 32-byte block transfer */ - -#define SH7750_CHCR_IE 0x00000004 /* Interrupt Enable */ -#define SH7750_CHCR_TE 0x00000002 /* Transfer End */ -#define SH7750_CHCR_DE 0x00000001 /* DMAC Enable */ - -/* DMA Operation Register - DMAOR */ -#define SH7750_DMAOR_REGOFS 0xA00040 /* offset */ -#define SH7750_DMAOR SH7750_P4_REG32(SH7750_DMAOR_REGOFS) -#define SH7750_DMAOR_A7 SH7750_A7_REG32(SH7750_DMAOR_REGOFS) - -#define SH7750_DMAOR_DDT 0x00008000 /* On-Demand Data Transfer Mode */ - -#define SH7750_DMAOR_PR 0x00000300 /* Priority Mode: */ -#define SH7750_DMAOR_PR_0123 0x00000000 /* CH0 > CH1 > CH2 > CH3 */ -#define SH7750_DMAOR_PR_0231 0x00000100 /* CH0 > CH2 > CH3 > CH1 */ -#define SH7750_DMAOR_PR_2013 0x00000200 /* CH2 > CH0 > CH1 > CH3 */ -#define SH7750_DMAOR_PR_RR 0x00000300 /* Round-robin mode */ - -#define SH7750_DMAOR_COD 0x00000010 /* Check Overrun for DREQ\ */ -#define SH7750_DMAOR_AE 0x00000004 /* Address Error flag */ -#define SH7750_DMAOR_NMIF 0x00000002 /* NMI Flag */ -#define SH7750_DMAOR_DME 0x00000001 /* DMAC Master Enable */ - -/* - * Serial Communication Interface - SCI - * Serial Communication Interface with FIFO - SCIF - */ -/* SCI Receive Data Register (byte, read-only) - SCRDR1, SCFRDR2 */ -#define SH7750_SCRDR_REGOFS(n) ((n) == 1 ? 0xE00014 : 0xE80014) /* offset */ -#define SH7750_SCRDR(n) SH7750_P4_REG32(SH7750_SCRDR_REGOFS(n)) -#define SH7750_SCRDR1 SH7750_SCRDR(1) -#define SH7750_SCRDR2 SH7750_SCRDR(2) -#define SH7750_SCRDR_A7(n) SH7750_A7_REG32(SH7750_SCRDR_REGOFS(n)) -#define SH7750_SCRDR1_A7 SH7750_SCRDR_A7(1) -#define SH7750_SCRDR2_A7 SH7750_SCRDR_A7(2) - -/* SCI Transmit Data Register (byte) - SCTDR1, SCFTDR2 */ -#define SH7750_SCTDR_REGOFS(n) ((n) == 1 ? 0xE0000C : 0xE8000C) /* offset */ -#define SH7750_SCTDR(n) SH7750_P4_REG32(SH7750_SCTDR_REGOFS(n)) -#define SH7750_SCTDR1 SH7750_SCTDR(1) -#define SH7750_SCTDR2 SH7750_SCTDR(2) -#define SH7750_SCTDR_A7(n) SH7750_A7_REG32(SH7750_SCTDR_REGOFS(n)) -#define SH7750_SCTDR1_A7 SH7750_SCTDR_A7(1) -#define SH7750_SCTDR2_A7 SH7750_SCTDR_A7(2) - -/* SCI Serial Mode Register - SCSMR1(byte), SCSMR2(half) */ -#define SH7750_SCSMR_REGOFS(n) ((n) == 1 ? 0xE00000 : 0xE80000) /* offset */ -#define SH7750_SCSMR(n) SH7750_P4_REG32(SH7750_SCSMR_REGOFS(n)) -#define SH7750_SCSMR1 SH7750_SCSMR(1) -#define SH7750_SCSMR2 SH7750_SCSMR(2) -#define SH7750_SCSMR_A7(n) SH7750_A7_REG32(SH7750_SCSMR_REGOFS(n)) -#define SH7750_SCSMR1_A7 SH7750_SCSMR_A7(1) -#define SH7750_SCSMR2_A7 SH7750_SCSMR_A7(2) - -#define SH7750_SCSMR1_CA 0x80 /* Communication Mode (C/A\): */ -#define SH7750_SCSMR1_CA_ASYNC 0x00 /* Asynchronous Mode */ -#define SH7750_SCSMR1_CA_SYNC 0x80 /* Synchronous Mode */ -#define SH7750_SCSMR_CHR 0x40 /* Character Length: */ -#define SH7750_SCSMR_CHR_8 0x00 /* 8-bit data */ -#define SH7750_SCSMR_CHR_7 0x40 /* 7-bit data */ -#define SH7750_SCSMR_PE 0x20 /* Parity Enable */ -#define SH7750_SCSMR_PM 0x10 /* Parity Mode: */ -#define SH7750_SCSMR_PM_EVEN 0x00 /* Even Parity */ -#define SH7750_SCSMR_PM_ODD 0x10 /* Odd Parity */ -#define SH7750_SCSMR_STOP 0x08 /* Stop Bit Length: */ -#define SH7750_SCSMR_STOP_1 0x00 /* 1 stop bit */ -#define SH7750_SCSMR_STOP_2 0x08 /* 2 stop bit */ -#define SH7750_SCSMR1_MP 0x04 /* Multiprocessor Mode */ -#define SH7750_SCSMR_CKS 0x03 /* Clock Select */ -#define SH7750_SCSMR_CKS_S 0 -#define SH7750_SCSMR_CKS_DIV1 0x00 /* Periph clock */ -#define SH7750_SCSMR_CKS_DIV4 0x01 /* Periph clock / 4 */ -#define SH7750_SCSMR_CKS_DIV16 0x02 /* Periph clock / 16 */ -#define SH7750_SCSMR_CKS_DIV64 0x03 /* Periph clock / 64 */ - -/* SCI Serial Control Register - SCSCR1(byte), SCSCR2(half) */ -#define SH7750_SCSCR_REGOFS(n) ((n) == 1 ? 0xE00008 : 0xE80008) /* offset */ -#define SH7750_SCSCR(n) SH7750_P4_REG32(SH7750_SCSCR_REGOFS(n)) -#define SH7750_SCSCR1 SH7750_SCSCR(1) -#define SH7750_SCSCR2 SH7750_SCSCR(2) -#define SH7750_SCSCR_A7(n) SH7750_A7_REG32(SH7750_SCSCR_REGOFS(n)) -#define SH7750_SCSCR1_A7 SH7750_SCSCR_A7(1) -#define SH7750_SCSCR2_A7 SH7750_SCSCR_A7(2) - -#define SH7750_SCSCR_TIE 0x80 /* Transmit Interrupt Enable */ -#define SH7750_SCSCR_RIE 0x40 /* Receive Interrupt Enable */ -#define SH7750_SCSCR_TE 0x20 /* Transmit Enable */ -#define SH7750_SCSCR_RE 0x10 /* Receive Enable */ -#define SH7750_SCSCR1_MPIE 0x08 /* Multiprocessor Interrupt Enable */ -#define SH7750_SCSCR2_REIE 0x08 /* Receive Error Interrupt Enable */ -#define SH7750_SCSCR1_TEIE 0x04 /* Transmit End Interrupt Enable */ -#define SH7750_SCSCR1_CKE 0x03 /* Clock Enable: */ -#define SH7750_SCSCR_CKE_INTCLK 0x00 /* Use Internal Clock */ -#define SH7750_SCSCR_CKE_EXTCLK 0x02 /* Use External Clock from SCK*/ -#define SH7750_SCSCR1_CKE_ASYNC_SCK_CLKOUT 0x01 /* Use SCK as a clock output - in asynchronous mode */ - -/* SCI Serial Status Register - SCSSR1(byte), SCSSR2(half) */ -#define SH7750_SCSSR_REGOFS(n) ((n) == 1 ? 0xE00010 : 0xE80010) /* offset */ -#define SH7750_SCSSR(n) SH7750_P4_REG32(SH7750_SCSSR_REGOFS(n)) -#define SH7750_SCSSR1 SH7750_SCSSR(1) -#define SH7750_SCSSR2 SH7750_SCSSR(2) -#define SH7750_SCSSR_A7(n) SH7750_A7_REG32(SH7750_SCSSR_REGOFS(n)) -#define SH7750_SCSSR1_A7 SH7750_SCSSR_A7(1) -#define SH7750_SCSSR2_A7 SH7750_SCSSR_A7(2) - -#define SH7750_SCSSR1_TDRE 0x80 /* Transmit Data Register Empty */ -#define SH7750_SCSSR1_RDRF 0x40 /* Receive Data Register Full */ -#define SH7750_SCSSR1_ORER 0x20 /* Overrun Error */ -#define SH7750_SCSSR1_FER 0x10 /* Framing Error */ -#define SH7750_SCSSR1_PER 0x08 /* Parity Error */ -#define SH7750_SCSSR1_TEND 0x04 /* Transmit End */ -#define SH7750_SCSSR1_MPB 0x02 /* Multiprocessor Bit */ -#define SH7750_SCSSR1_MPBT 0x01 /* Multiprocessor Bit Transfer */ - -#define SH7750_SCSSR2_PERN 0xF000 /* Number of Parity Errors */ -#define SH7750_SCSSR2_PERN_S 12 -#define SH7750_SCSSR2_FERN 0x0F00 /* Number of Framing Errors */ -#define SH7750_SCSSR2_FERN_S 8 -#define SH7750_SCSSR2_ER 0x0080 /* Receive Error */ -#define SH7750_SCSSR2_TEND 0x0040 /* Transmit End */ -#define SH7750_SCSSR2_TDFE 0x0020 /* Transmit FIFO Data Empty */ -#define SH7750_SCSSR2_BRK 0x0010 /* Break Detect */ -#define SH7750_SCSSR2_FER 0x0008 /* Framing Error */ -#define SH7750_SCSSR2_PER 0x0004 /* Parity Error */ -#define SH7750_SCSSR2_RDF 0x0002 /* Receive FIFO Data Full */ -#define SH7750_SCSSR2_DR 0x0001 /* Receive Data Ready */ - -/* SCI Serial Port Register - SCSPTR1(byte) */ -#define SH7750_SCSPTR1_REGOFS 0xE0001C /* offset */ -#define SH7750_SCSPTR1 SH7750_P4_REG32(SH7750_SCSPTR1_REGOFS) -#define SH7750_SCSPTR1_A7 SH7750_A7_REG32(SH7750_SCSPTR1_REGOFS) - -#define SH7750_SCSPTR1_EIO 0x80 /* Error Interrupt Only */ -#define SH7750_SCSPTR1_SPB1IO 0x08 /* 1: Output SPB1DT bit to SCK pin */ -#define SH7750_SCSPTR1_SPB1DT 0x04 /* Serial Port Clock Port Data */ -#define SH7750_SCSPTR1_SPB0IO 0x02 /* 1: Output SPB0DT bit to TxD pin */ -#define SH7750_SCSPTR1_SPB0DT 0x01 /* Serial Port Break Data */ - -/* SCIF Serial Port Register - SCSPTR2(half) */ -#define SH7750_SCSPTR2_REGOFS 0xE80020 /* offset */ -#define SH7750_SCSPTR2 SH7750_P4_REG32(SH7750_SCSPTR2_REGOFS) -#define SH7750_SCSPTR2_A7 SH7750_A7_REG32(SH7750_SCSPTR2_REGOFS) - -#define SH7750_SCSPTR2_RTSIO 0x80 /* 1: Output RTSDT bit to RTS2\ pin */ -#define SH7750_SCSPTR2_RTSDT 0x40 /* RTS Port Data */ -#define SH7750_SCSPTR2_CTSIO 0x20 /* 1: Output CTSDT bit to CTS2\ pin */ -#define SH7750_SCSPTR2_CTSDT 0x10 /* CTS Port Data */ -#define SH7750_SCSPTR2_SPB2IO 0x02 /* 1: Output SPBDT bit to TxD2 pin */ -#define SH7750_SCSPTR2_SPB2DT 0x01 /* Serial Port Break Data */ - -/* SCI Bit Rate Register - SCBRR1(byte), SCBRR2(byte) */ -#define SH7750_SCBRR_REGOFS(n) ((n) == 1 ? 0xE00004 : 0xE80004) /* offset */ -#define SH7750_SCBRR(n) SH7750_P4_REG32(SH7750_SCBRR_REGOFS(n)) -#define SH7750_SCBRR1 SH7750_SCBRR_P4(1) -#define SH7750_SCBRR2 SH7750_SCBRR_P4(2) -#define SH7750_SCBRR_A7(n) SH7750_A7_REG32(SH7750_SCBRR_REGOFS(n)) -#define SH7750_SCBRR1_A7 SH7750_SCBRR(1) -#define SH7750_SCBRR2_A7 SH7750_SCBRR(2) - -/* SCIF FIFO Control Register - SCFCR2(half) */ -#define SH7750_SCFCR2_REGOFS 0xE80018 /* offset */ -#define SH7750_SCFCR2 SH7750_P4_REG32(SH7750_SCFCR2_REGOFS) -#define SH7750_SCFCR2_A7 SH7750_A7_REG32(SH7750_SCFCR2_REGOFS) - -#define SH7750_SCFCR2_RSTRG 0x700 /* RTS2\ Output Active Trigger; RTS2\ - signal goes to high level when the - number of received data stored in - FIFO exceeds the trigger number */ -#define SH7750_SCFCR2_RSTRG_15 0x000 /* 15 bytes */ -#define SH7750_SCFCR2_RSTRG_1 0x000 /* 1 byte */ -#define SH7750_SCFCR2_RSTRG_4 0x000 /* 4 bytes */ -#define SH7750_SCFCR2_RSTRG_6 0x000 /* 6 bytes */ -#define SH7750_SCFCR2_RSTRG_8 0x000 /* 8 bytes */ -#define SH7750_SCFCR2_RSTRG_10 0x000 /* 10 bytes */ -#define SH7750_SCFCR2_RSTRG_14 0x000 /* 14 bytes */ - -#define SH7750_SCFCR2_RTRG 0x0C0 /* Receive FIFO Data Number Trigger, - Receive Data Full (RDF) Flag sets - when number of receive data bytes is - equal or greater than the trigger - number */ -#define SH7750_SCFCR2_RTRG_1 0x000 /* 1 byte */ -#define SH7750_SCFCR2_RTRG_4 0x040 /* 4 bytes */ -#define SH7750_SCFCR2_RTRG_8 0x080 /* 8 bytes */ -#define SH7750_SCFCR2_RTRG_14 0x0C0 /* 14 bytes */ - -#define SH7750_SCFCR2_TTRG 0x030 /* Transmit FIFO Data Number Trigger, - Transmit FIFO Data Register Empty (TDFE) - flag sets when the number of remaining - transmit data bytes is equal or less - than the trigger number */ -#define SH7750_SCFCR2_TTRG_8 0x000 /* 8 bytes */ -#define SH7750_SCFCR2_TTRG_4 0x010 /* 4 bytes */ -#define SH7750_SCFCR2_TTRG_2 0x020 /* 2 bytes */ -#define SH7750_SCFCR2_TTRG_1 0x030 /* 1 byte */ - -#define SH7750_SCFCR2_MCE 0x008 /* Modem Control Enable */ -#define SH7750_SCFCR2_TFRST 0x004 /* Transmit FIFO Data Register Reset, - invalidates the transmit data in the - transmit FIFO */ -#define SH7750_SCFCR2_RFRST 0x002 /* Receive FIFO Data Register Reset, - invalidates the receive data in the - receive FIFO data register and resets - it to the empty state */ -#define SH7750_SCFCR2_LOOP 0x001 /* Loopback Test */ - -/* SCIF FIFO Data Count Register - SCFDR2(half, read-only) */ -#define SH7750_SCFDR2_REGOFS 0xE8001C /* offset */ -#define SH7750_SCFDR2 SH7750_P4_REG32(SH7750_SCFDR2_REGOFS) -#define SH7750_SCFDR2_A7 SH7750_A7_REG32(SH7750_SCFDR2_REGOFS) - -#define SH7750_SCFDR2_T 0x1F00 /* Number of untransmitted data bytes - in transmit FIFO */ -#define SH7750_SCFDR2_T_S 8 -#define SH7750_SCFDR2_R 0x001F /* Number of received data bytes in - receive FIFO */ -#define SH7750_SCFDR2_R_S 0 - -/* SCIF Line Status Register - SCLSR2(half, read-only) */ -#define SH7750_SCLSR2_REGOFS 0xE80024 /* offset */ -#define SH7750_SCLSR2 SH7750_P4_REG32(SH7750_SCLSR2_REGOFS) -#define SH7750_SCLSR2_A7 SH7750_A7_REG32(SH7750_SCLSR2_REGOFS) - -#define SH7750_SCLSR2_ORER 0x0001 /* Overrun Error */ - -/* - * SCI-based Smart Card Interface - */ -/* Smart Card Mode Register - SCSCMR1(byte) */ -#define SH7750_SCSCMR1_REGOFS 0xE00018 /* offset */ -#define SH7750_SCSCMR1 SH7750_P4_REG32(SH7750_SCSCMR1_REGOFS) -#define SH7750_SCSCMR1_A7 SH7750_A7_REG32(SH7750_SCSCMR1_REGOFS) - -#define SH7750_SCSCMR1_SDIR 0x08 /* Smart Card Data Transfer Direction: */ -#define SH7750_SCSCMR1_SDIR_LSBF 0x00 /* LSB-first */ -#define SH7750_SCSCMR1_SDIR_MSBF 0x08 /* MSB-first */ - -#define SH7750_SCSCMR1_SINV 0x04 /* Smart Card Data Inversion */ -#define SH7750_SCSCMR1_SMIF 0x01 /* Smart Card Interface Mode Select */ - -/* Smart-card specific bits in other registers */ -/* SCSMR1: */ -#define SH7750_SCSMR1_GSM 0x80 /* GSM mode select */ - -/* SCSSR1: */ -#define SH7750_SCSSR1_ERS 0x10 /* Error Signal Status */ - -/* - * I/O Ports - */ -/* Port Control Register A - PCTRA */ -#define SH7750_PCTRA_REGOFS 0x80002C /* offset */ -#define SH7750_PCTRA SH7750_P4_REG32(SH7750_PCTRA_REGOFS) -#define SH7750_PCTRA_A7 SH7750_A7_REG32(SH7750_PCTRA_REGOFS) - -#define SH7750_PCTRA_PBPUP(n) 0 /* Bit n is pulled up */ -#define SH7750_PCTRA_PBNPUP(n) (1 << ((n)*2+1)) /* Bit n is not pulled up */ -#define SH7750_PCTRA_PBINP(n) 0 /* Bit n is an input */ -#define SH7750_PCTRA_PBOUT(n) (1 << ((n)*2)) /* Bit n is an output */ - -/* Port Data Register A - PDTRA(half) */ -#define SH7750_PDTRA_REGOFS 0x800030 /* offset */ -#define SH7750_PDTRA SH7750_P4_REG32(SH7750_PDTRA_REGOFS) -#define SH7750_PDTRA_A7 SH7750_A7_REG32(SH7750_PDTRA_REGOFS) - -#define SH7750_PDTRA_BIT(n) (1 << (n)) - -/* Port Control Register B - PCTRB */ -#define SH7750_PCTRB_REGOFS 0x800040 /* offset */ -#define SH7750_PCTRB SH7750_P4_REG32(SH7750_PCTRB_REGOFS) -#define SH7750_PCTRB_A7 SH7750_A7_REG32(SH7750_PCTRB_REGOFS) - -#define SH7750_PCTRB_PBPUP(n) 0 /* Bit n is pulled up */ -#define SH7750_PCTRB_PBNPUP(n) (1 << ((n-16)*2+1)) /* Bit n is not pulled up */ -#define SH7750_PCTRB_PBINP(n) 0 /* Bit n is an input */ -#define SH7750_PCTRB_PBOUT(n) (1 << ((n-16)*2)) /* Bit n is an output */ - -/* Port Data Register B - PDTRB(half) */ -#define SH7750_PDTRB_REGOFS 0x800044 /* offset */ -#define SH7750_PDTRB SH7750_P4_REG32(SH7750_PDTRB_REGOFS) -#define SH7750_PDTRB_A7 SH7750_A7_REG32(SH7750_PDTRB_REGOFS) - -#define SH7750_PDTRB_BIT(n) (1 << ((n)-16)) - -/* GPIO Interrupt Control Register - GPIOIC(half) */ -#define SH7750_GPIOIC_REGOFS 0x800048 /* offset */ -#define SH7750_GPIOIC SH7750_P4_REG32(SH7750_GPIOIC_REGOFS) -#define SH7750_GPIOIC_A7 SH7750_A7_REG32(SH7750_GPIOIC_REGOFS) - -#define SH7750_GPIOIC_PTIREN(n) (1 << (n)) /* Port n is used as a GPIO int */ - -/* - * Interrupt Controller - INTC - */ -/* Interrupt Control Register - ICR (half) */ -#define SH7750_ICR_REGOFS 0xD00000 /* offset */ -#define SH7750_ICR SH7750_P4_REG32(SH7750_ICR_REGOFS) -#define SH7750_ICR_A7 SH7750_A7_REG32(SH7750_ICR_REGOFS) - -#define SH7750_ICR_NMIL 0x8000 /* NMI Input Level */ -#define SH7750_ICR_MAI 0x4000 /* NMI Interrupt Mask */ - -#define SH7750_ICR_NMIB 0x0200 /* NMI Block Mode: */ -#define SH7750_ICR_NMIB_BLK 0x0000 /* NMI requests held pending while - SR.BL bit is set to 1 */ -#define SH7750_ICR_NMIB_NBLK 0x0200 /* NMI requests detected when SR.BL bit - set to 1 */ - -#define SH7750_ICR_NMIE 0x0100 /* NMI Edge Select: */ -#define SH7750_ICR_NMIE_FALL 0x0000 /* Interrupt request detected on falling - edge of NMI input */ -#define SH7750_ICR_NMIE_RISE 0x0100 /* Interrupt request detected on rising - edge of NMI input */ - -#define SH7750_ICR_IRLM 0x0080 /* IRL Pin Mode: */ -#define SH7750_ICR_IRLM_ENC 0x0000 /* IRL\ pins used as a level-encoded - interrupt requests */ -#define SH7750_ICR_IRLM_RAW 0x0080 /* IRL\ pins used as a four independent - interrupt requests */ - -/* Interrupt Priority Register A - IPRA (half) */ -#define SH7750_IPRA_REGOFS 0xD00004 /* offset */ -#define SH7750_IPRA SH7750_P4_REG32(SH7750_IPRA_REGOFS) -#define SH7750_IPRA_A7 SH7750_A7_REG32(SH7750_IPRA_REGOFS) - -#define SH7750_IPRA_TMU0 0xF000 /* TMU0 interrupt priority */ -#define SH7750_IPRA_TMU0_S 12 -#define SH7750_IPRA_TMU1 0x0F00 /* TMU1 interrupt priority */ -#define SH7750_IPRA_TMU1_S 8 -#define SH7750_IPRA_TMU2 0x00F0 /* TMU2 interrupt priority */ -#define SH7750_IPRA_TMU2_S 4 -#define SH7750_IPRA_RTC 0x000F /* RTC interrupt priority */ -#define SH7750_IPRA_RTC_S 0 - -/* Interrupt Priority Register B - IPRB (half) */ -#define SH7750_IPRB_REGOFS 0xD00008 /* offset */ -#define SH7750_IPRB SH7750_P4_REG32(SH7750_IPRB_REGOFS) -#define SH7750_IPRB_A7 SH7750_A7_REG32(SH7750_IPRB_REGOFS) - -#define SH7750_IPRB_WDT 0xF000 /* WDT interrupt priority */ -#define SH7750_IPRB_WDT_S 12 -#define SH7750_IPRB_REF 0x0F00 /* Memory Refresh unit interrupt - priority */ -#define SH7750_IPRB_REF_S 8 -#define SH7750_IPRB_SCI1 0x00F0 /* SCI1 interrupt priority */ -#define SH7750_IPRB_SCI1_S 4 - -/* Interrupt Priority Register C - IPRC (half) */ -#define SH7750_IPRC_REGOFS 0xD00004 /* offset */ -#define SH7750_IPRC SH7750_P4_REG32(SH7750_IPRC_REGOFS) -#define SH7750_IPRC_A7 SH7750_A7_REG32(SH7750_IPRC_REGOFS) - -#define SH7750_IPRC_GPIO 0xF000 /* GPIO interrupt priority */ -#define SH7750_IPRC_GPIO_S 12 -#define SH7750_IPRC_DMAC 0x0F00 /* DMAC interrupt priority */ -#define SH7750_IPRC_DMAC_S 8 -#define SH7750_IPRC_SCIF 0x00F0 /* SCIF interrupt priority */ -#define SH7750_IPRC_SCIF_S 4 -#define SH7750_IPRC_HUDI 0x000F /* H-UDI interrupt priority */ -#define SH7750_IPRC_HUDI_S 0 - - -/* - * User Break Controller registers - */ -#define SH7750_BARA 0x200000 /* Break address regiser A */ -#define SH7750_BAMRA 0x200004 /* Break address mask regiser A */ -#define SH7750_BBRA 0x200008 /* Break bus cycle regiser A */ -#define SH7750_BARB 0x20000c /* Break address regiser B */ -#define SH7750_BAMRB 0x200010 /* Break address mask regiser B */ -#define SH7750_BBRB 0x200014 /* Break bus cycle regiser B */ -#define SH7750_BASRB 0x000018 /* Break ASID regiser B */ -#define SH7750_BDRB 0x200018 /* Break data regiser B */ -#define SH7750_BDMRB 0x20001c /* Break data mask regiser B */ -#define SH7750_BRCR 0x200020 /* Break control register */ - -#define SH7750_BRCR_UDBE 0x0001 /* User break debug enable bit */ - -#endif diff --git a/bsps/sh/gensh4/include/sdram.h b/bsps/sh/gensh4/include/sdram.h deleted file mode 100644 index 52acaa61db..0000000000 --- a/bsps/sh/gensh4/include/sdram.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * SDRAM Mode Register - * Based on Fujitsu MB81F643242B data sheet. - * - * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __SDRAM_H__ -#define __SDRAM_H__ - -/* SDRAM Mode Register */ -#define SDRAM_MODE_BL 0x0007 /* Burst Length: */ -#define SDRAM_MODE_BL_1 0x0000 /* 0 */ -#define SDRAM_MODE_BL_2 0x0001 /* 2 */ -#define SDRAM_MODE_BL_4 0x0002 /* 4 */ -#define SDRAM_MODE_BL_8 0x0003 /* 8 */ -#define SDRAM_MODE_BL_16 0x0004 /* 16 */ -#define SDRAM_MODE_BL_32 0x0005 /* 32 */ -#define SDRAM_MODE_BL_64 0x0006 /* 64 */ -#define SDRAM_MODE_BL_FULL 0x0007 /* Full column */ - -#define SDRAM_MODE_BT 0x0008 /* Burst Type: */ -#define SDRAM_MODE_BT_SEQ 0x0000 /* Sequential */ -#define SDRAM_MODE_BT_ILV 0x0008 /* Interleave */ - -#define SDRAM_MODE_CL 0x0070 /* CAS Latency: */ -#define SDRAM_MODE_CL_1 0x0010 /* 1 */ -#define SDRAM_MODE_CL_2 0x0020 /* 2 */ -#define SDRAM_MODE_CL_3 0x0030 /* 3 */ - -#define SDRAM_MODE_OPC 0x0200 /* Opcode: */ -#define SDRAM_MODE_OPC_BRBW 0x0000 /* Burst read & Burst write */ -#define SDRAM_MODE_OPC_BRSW 0x0200 /* Burst read & Single write */ - -#endif diff --git a/bsps/sh/gensh4/include/sh/sh4uart.h b/bsps/sh/gensh4/include/sh/sh4uart.h deleted file mode 100644 index 1e7a486eb8..0000000000 --- a/bsps/sh/gensh4/include/sh/sh4uart.h +++ /dev/null @@ -1,174 +0,0 @@ -/* - * Generic UART Serial driver for SH-4 processors definitions - * - * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russian Fed. - * Author: Alexandra Kossovsky - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __SH4UART_H__ -#define __SH4UART_H__ - -#include - - -/* - * Define this to work from gdb stub - */ - -/* FIXME: This is BSP-specific */ -#define SH4_WITH_IPL - -#define SH4_SCI 1 /* Serial Communication Interface - SCI */ -#define SH4_SCIF 2 /* Serial Communication Interface with FIFO - SCIF */ -#define TRANSMIT_TRIGGER_VALUE(ttrg) ((ttrg) == SH7750_SCFCR2_RTRG_1 ? 1 : \ - (ttrg) == SH7750_SCFCR2_RTRG_4 ? 4 : \ - (ttrg) == SH7750_SCFCR2_RTRG_8 ? 8 : 14) - -/* - * Macros to call UART registers - */ -#define SCRDR(n) (*(volatile uint8_t*)SH7750_SCRDR(n)) -#define SCRDR1 SCRDR(1) -#define SCRDR2 SCRDR(2) -#define SCTDR(n) (*(volatile uint8_t*)SH7750_SCTDR(n)) -#define SCTDR1 SCTDR(1) -#define SCTDR2 SCTDR(2) -#define SCSMR(n) ((n) == 1 ? *(volatile uint8_t*)SH7750_SCSMR1 : \ - *(volatile uint16_t*)SH7750_SCSMR2) -#define SCSMR1 SCSMR(1) -#define SCSMR2 SCSMR(2) -#define SCSCR(n) ((n) == 1 ? *(volatile uint8_t*)SH7750_SCSCR1 : \ - *(volatile uint16_t*)SH7750_SCSCR2) -#define SCSCR1 SCSCR(1) -#define SCSCR2 SCSCR(2) -#define SCSSR(n) ((n) == 1 ? *(volatile uint8_t*)SH7750_SCSSR1 : \ - *(volatile uint16_t*)SH7750_SCSSR2) -#define SCSSR1 SCSSR(1) -#define SCSSR2 SCSSR(2) -#define SCSPTR1 (*(volatile uint8_t*)SH7750_SCSPTR1) -#define SCSPTR2 (*(volatile uint16_t*)SH7750_SCSPTR2) -#define SCBRR(n) (*(volatile uint8_t*)SH7750_SCBRR(n)) -#define SCBRR1 SCBRR(1) -#define SCBRR2 SCBRR(2) -#define SCFCR2 (*(volatile uint16_t*)SH7750_SCFCR2) -#define SCFDR2 (*(volatile uint16_t*)SH7750_SCFDR2) -#define SCLSR2 (*(volatile uint16_t*)SH7750_SCLSR2) - -#define IPRB (*(volatile uint16_t*)SH7750_IPRB) -#define IPRC (*(volatile uint16_t*)SH7750_IPRC) - -/* - * The following structure is a descriptor of single UART channel. - * It contains the initialization information about channel and - * current operating values - */ -typedef struct sh4uart { - uint8_t chn; /* UART channel number */ - uint8_t int_driven; /* UART interrupt vector number, or - 0 if polled I/O */ - void *tty; /* termios channel descriptor */ - - volatile const char *tx_buf; /* Transmit buffer from termios */ - volatile uint32_t tx_buf_len; /* Transmit buffer length */ - volatile uint32_t tx_ptr; /* Index of next char to transmit*/ - - rtems_isr_entry old_handler_transmit; /* Saved interrupt handlers */ - rtems_isr_entry old_handler_receive; - - tcflag_t c_iflag; /* termios input mode flags */ - bool parerr_mark_flag; /* Parity error processing state */ -} sh4uart; - -/* - * Functions from sh4uart.c - */ - -/* sh4uart_init -- - * This function verifies the input parameters and perform initialization - * of the Motorola Coldfire on-chip UART descriptor structure. - * - */ -rtems_status_code -sh4uart_init(sh4uart *uart, void *tty, int chn, int int_driven); - -/* sh4uart_reset -- - * This function perform the hardware initialization of Motorola - * Coldfire processor on-chip UART controller using parameters - * filled by the sh4uart_init function. - */ -rtems_status_code -sh4uart_reset(sh4uart *uart); - -/* sh4uart_disable -- - * This function disable the operations on Motorola Coldfire UART - * controller - */ -rtems_status_code -sh4uart_disable(sh4uart *uart, int disable_port); - -/* sh4uart_set_attributes -- - * This function parse the termios attributes structure and perform - * the appropriate settings in hardware. - */ -rtems_status_code -sh4uart_set_attributes(sh4uart *mcf, const struct termios *t); - -/* sh4uart_poll_read -- - * This function tried to read character from MCF UART and perform - * error handling. - */ -int -sh4uart_poll_read(sh4uart *uart); - -#ifdef SH4_WITH_IPL -/* ipl_console_poll_read -- - * This function tried to read character from MCF UART over SH-IPL. - */ -int -ipl_console_poll_read(int minor); - -/* sh4uart_interrupt_write -- - * This function initiate transmitting of the buffer in interrupt mode. - */ -rtems_status_code -sh4uart_interrupt_write(sh4uart *uart, const char *buf, int len); - -/* sh4uart_poll_write -- - * This function transmit buffer byte-by-byte in polling mode. - */ -int -sh4uart_poll_write(sh4uart *uart, const char *buf, int len); - -/* ipl_console_poll_write -- - * This function transmit buffer byte-by-byte in polling mode over SH-IPL. - */ -int -ipl_console_poll_write(int minor, const char *buf, int len); - -/* - * ipl_finish -- - * Says gdb that program finished to get out from it. - */ -extern void ipl_finish(void); -#endif - -/* sh4uart_stop_remote_tx -- - * This function stop data flow from remote device. - */ -rtems_status_code -sh4uart_stop_remote_tx(sh4uart *uart); - -/* sh4uart_start_remote_tx -- - * This function resume data flow from remote device. - */ -rtems_status_code -sh4uart_start_remote_tx(sh4uart *uart); - -/* Descriptor structures for two on-chip UART channels */ -extern sh4uart sh4_uarts[2]; - -#endif diff --git a/bsps/sh/gensh4/include/tm27.h b/bsps/sh/gensh4/include/tm27.h deleted file mode 100644 index 978bf8505a..0000000000 --- a/bsps/sh/gensh4/include/tm27.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * @file - * @ingroup sh_gensh4 - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Stuff for Time Test 27 - */ - -#define MUST_WAIT_FOR_INTERRUPT 1 - -#ifndef SH7750_EVT_WDT_ITI -# error "..." -#endif - -#define TM27_USE_VECTOR_HANDLER - -#define Install_tm27_vector( handler ) \ -{ \ - rtems_isr_entry old_handler; \ - rtems_status_code status; \ - status = rtems_interrupt_catch( (handler), \ - SH7750_EVT_TO_NUM(SH7750_EVT_WDT_ITI), &old_handler); \ - if (status != RTEMS_SUCCESSFUL) \ - printf("Status of rtems_interrupt_catch = %d", status); \ -} - -#define Cause_tm27_intr() \ -{ \ - *(volatile uint16_t*)SH7750_IPRB |= 0xf000; \ - *(volatile uint16_t*)SH7750_WTCSR = SH7750_WTCSR_KEY; \ - *(volatile uint16_t*)SH7750_WTCNT = SH7750_WTCNT_KEY | 0xfe; \ - *(volatile uint16_t*)SH7750_WTCSR = \ - SH7750_WTCSR_KEY | SH7750_WTCSR_TME; \ -} - -#define Clear_tm27_intr() \ -{ \ - *(volatile uint16_t*)SH7750_WTCSR = SH7750_WTCSR_KEY; \ -} - -#define Lower_tm27_intr() \ -{ \ - sh_set_interrupt_level((SH7750_IPRB & 0xf000) << SH4_SR_IMASK_S); \ -} - -#endif diff --git a/bsps/sh/gensh4/start/cpu_asm.c b/bsps/sh/gensh4/start/cpu_asm.c deleted file mode 100644 index a2738532ab..0000000000 --- a/bsps/sh/gensh4/start/cpu_asm.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file contains the basic algorithms for all assembly code used - * in an specific CPU port of RTEMS. These algorithms must be implemented - * in assembly language - * - * NOTE: This port uses a C file with inline assembler instructions - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/* - * This is supposed to be an assembly file. This means that system.h - * and cpu.h should not be included in a "real" cpu_asm file. An - * implementation in assembly should include "cpu_asm.h" - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -unsigned long *_old_stack_ptr; - -register unsigned long *stack_ptr __asm__ ("r15"); - -/* - * This routine provides the RTEMS interrupt management. - */ - -void __ISR_Handler( uint32_t vector) -{ - ISR_Level level; - - _ISR_Local_disable( level ); - - _Thread_Dispatch_disable(); - - if ( _ISR_Nest_level == 0 ) - { - /* Install irq stack */ - _old_stack_ptr = stack_ptr; - stack_ptr = _CPU_Interrupt_stack_high; - } - - _ISR_Nest_level++; - - _ISR_Local_enable( level ); - - /* call isp */ - if ( _ISR_Vector_table[ vector]) - (*_ISR_Vector_table[ vector ])( vector ); - - _ISR_Local_disable( level ); - - _Thread_Dispatch_enable( _Per_CPU_Get() ); - - _ISR_Nest_level--; - - if ( _ISR_Nest_level == 0 ) - /* restore old stack pointer */ - stack_ptr = _old_stack_ptr; - - _ISR_Local_enable( level ); - - if ( _ISR_Nest_level ) - return; - - if ( !_Thread_Dispatch_is_enabled() ) { - return; - } - - if ( _Thread_Dispatch_necessary ) { - _Thread_Dispatch(); - } -} diff --git a/bsps/sh/gensh4/start/hw_init.c b/bsps/sh/gensh4/start/hw_init.c deleted file mode 100644 index 4bf673ece7..0000000000 --- a/bsps/sh/gensh4/start/hw_init.c +++ /dev/null @@ -1,283 +0,0 @@ -/* - * SMFD board hardware initialization. - */ - -/* - * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov - * Alexandra Kossovsky - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include "rtems/score/sh7750_regs.h" -#include "rtems/score/sh_io.h" -#include "sdram.h" -#include "bsp.h" - -/* early_hw_init -- - * Perform initial hardware initialization: - * - setup clock generator - * - initialize bus state controller, memory settings, SDRAM - * - disable DMA - * - setup external ports, etc. - * - initialize interrupt controller - * - * This function should not access the memory! It should be compiled - * with -fomit-frame-pointer to avoid stack access. - */ -void early_hw_init(void) -{ - /* Explicitly turn off the MMU */ - write32(0, SH7750_MMUCR); - - /* Disable instruction and operand caches */ - write32(0, SH7750_CCR); - - /* Setup Clock Generator */ - /* - * Input clock frequency is 16 MHz, MD0=1, - * CPU clock frequency already selected to 96MHz. - * Bus clock frequency should be set to 48 MHz, therefore divider 2 - * should be applied (bus frequency is 48 MHz, clock period is 20.84ns). - * Peripheral frequency should be set to 24 MHz, therefore divider 4 - * should be used. - */ - /* Prepare watchdog timer for frequency changing */ - write16((read8(SH7750_WTCSR) & ~SH7750_WTCSR_TME) | - SH7750_WTCSR_KEY, SH7750_WTCSR); - write16(SH7750_WTCSR_MODE_IT | SH7750_WTCSR_CKS_DIV4096 | - SH7750_WTCSR_KEY, SH7750_WTCSR); - - /* Turn PLL1 on */ - write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT); - write16(read16(SH7750_FRQCR) | SH7750_FRQCR_PLL1EN, SH7750_FRQCR); - - /* Perform Frequency Selection */ - write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT); - write16(SH7750_FRQCR_CKOEN | SH7750_FRQCR_PLL1EN | - SH7750_FRQCR_IFCDIV1 | SH7750_FRQCR_BFCDIV2 | SH7750_FRQCR_PFCDIV4, - SH7750_FRQCR); - - /* Turn PLL2 on */ - write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT); - write16(read16(SH7750_FRQCR) | SH7750_FRQCR_PLL2EN, SH7750_FRQCR); - - /* Bus State Controller Initialization */ - /* - * Area assignments: - * Area 0: Flash memory, SRAM interface - * Area 1: GDC - * Area 2: SDRAM - * Area 3-6: unused - */ - write32( - /* Pull-ups (IPUP, OPUP) enabled */ - /* No Byte-Control SRAM mode for Area 1 and Area 3 */ - SH7750_BCR1_BREQEN | /* Enable external bus requests */ - /* No Partial Sharing Mode */ - /* No MPX interface */ - /* Memory and Control Signals are in HiZ */ - SH7750_BCR1_A0BST_SRAM | /* No burst ROM in flash */ - SH7750_BCR1_A5BST_SRAM | /* Area 5 is not in use */ - SH7750_BCR1_A6BST_SRAM | /* Area 6 is not in use */ - SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM /* Select Area 2 SDRAM type */ - /* Area 5,6 programmed as a SRAM interface (not PCMCIA) */, - SH7750_BCR1); - - write16( - (SH7750_BCR2_SZ_8 << SH7750_BCR2_A0SZ_S) | /* These bits is read-only - and set during reset */ - (SH7750_BCR2_SZ_32 << SH7750_BCR2_A6SZ_S) | /* Area 6 not used */ - (SH7750_BCR2_SZ_32 << SH7750_BCR2_A5SZ_S) | /* Area 5 not used */ - (SH7750_BCR2_SZ_32 << SH7750_BCR2_A4SZ_S) | /* Area 4 not used */ - (SH7750_BCR2_SZ_32 << SH7750_BCR2_A3SZ_S) | /* Area 3 not used */ - (SH7750_BCR2_SZ_32 << SH7750_BCR2_A2SZ_S) | /* SDRAM is 32-bit width */ - (SH7750_BCR2_SZ_32 << SH7750_BCR2_A1SZ_S) | /* GDC is 32-bit width */ - SH7750_BCR2_PORTEN, /* Use D32-D51 as a port */ - SH7750_BCR2); - - write32( - (0 << SH7750_WCR1_DMAIW_S) | /* 0 required for SDRAM RAS down mode */ - (7 << SH7750_WCR1_A6IW_S) | /* Area 6 not used */ - (7 << SH7750_WCR1_A5IW_S) | /* Area 5 not used */ - (7 << SH7750_WCR1_A4IW_S) | /* Area 4 not used */ - (7 << SH7750_WCR1_A3IW_S) | /* Area 3 not used */ - (1 << SH7750_WCR1_A2IW_S) | /* 1 idle cycles inserted between acc */ - (7 << SH7750_WCR1_A1IW_S) | /* Don't have GDC specs... Set safer. */ - (1 << SH7750_WCR1_A0IW_S), /* 1 idle cycles inserted between acc */ - SH7750_WCR1); - - write32( - (SH7750_WCR2_WS15 << SH7750_WCR2_A6W_S) | /* Area 6 not used */ - (SH7750_WCR2_BPWS7 << SH7750_WCR2_A6B_S) | - (SH7750_WCR2_WS15 << SH7750_WCR2_A5W_S) | /* Area 5 not used */ - (SH7750_WCR2_BPWS7 << SH7750_WCR2_A5B_S) | - (SH7750_WCR2_WS15 << SH7750_WCR2_A4W_S) | /* Area 4 not used */ - (SH7750_WCR2_WS15 << SH7750_WCR2_A3W_S) | /*Area 3 not used*/ - (SH7750_WCR2_SDRAM_CAS_LAT2 << SH7750_WCR2_A2W_S) | /* SDRAM CL = 2 */ - (SH7750_WCR2_WS15 << SH7750_WCR2_A1W_S) | /* Area 1 (GDC) - requirements not known*/ - (SH7750_WCR2_WS6 << SH7750_WCR2_A0W_S) | /* 4 wait states required - at 48MHz for 70ns mem., - set closest greater */ - (SH7750_WCR2_BPWS7 << SH7750_WCR2_A0B_S), /* burst mode disabled for - Area 0 flash ROM */ - SH7750_WCR2); - write32( - SH7750_WCR3_A6S | /* Area 6 not used */ - (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A6H_S) | - SH7750_WCR3_A5S | /* Area 5 not used */ - (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A5H_S) | - SH7750_WCR3_A4S | /* Area 4 not used */ - (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A4H_S) | - SH7750_WCR3_A3S | /* Area 3 not used */ - (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A3H_S) | - SH7750_WCR3_A2S | /* SDRAM - ignored */ - (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A2H_S) | - SH7750_WCR3_A1S | /* GDC - unknown, set max*/ - (SH7750_WCR3_DHWS_3 << SH7750_WCR3_A1H_S) | - 0 | /* flash ROM - no write strobe setup time required */ - (SH7750_WCR3_DHWS_0 << SH7750_WCR3_A0H_S), - SH7750_WCR3); - - #define MCRDEF \ - /* SH7750_MCR_RASD | */ /* Set RAS Down mode */ \ - (SH7750_MCR_TRC_0 | SH7750_MCR_TRAS_SDRAM_TRC_4 | \ - /* RAS precharge time is 63ns; it corresponds to 4 clocks */ \ - /* TCAS valid only for DRAM interface */ \ - SH7750_MCR_TPC_SDRAM_1 | /* TPC = 20ns = 1 clock */ \ - SH7750_MCR_RCD_SDRAM_2 | /* RCD = 21ns = 2 clock */ \ - /* After write, next active command is not issued for a period of \ - TPC + TRWL. SDRAM specifies that it should be BL+Trp clocks when \ - CL=2. Trp = 20ns = 1clock; BL=8. Therefore we should wait 9 \ - clocks. Don't know why, but 6 clocks (TRWL=5 and TPC=1) seems \ - working. May be, something wrong in documentation? */ \ - SH7750_MCR_TRWL_5 | /* TRWL = 5 clock */ \ - SH7750_MCR_BE | /* Always enabled for SDRAM */ \ - SH7750_MCR_SZ_32 | /* Memory data size is 32 bit */ \ - (4 << SH7750_MCR_AMX_S) | /* Select memory device type */ \ - SH7750_MCR_RFSH | /* Refresh is performed */ \ - SH7750_MCR_RMODE_NORMAL) /* Auto-Refresh mode */ - - /* Clear refresh timer counter */ - write16(SH7750_RTCNT_KEY | 0, SH7750_RTCNT); - - /* Time between auto-refresh commands is 15.6 microseconds; refresh - timer counter frequency is 12 MHz; 1.56e-5*1.2e7= 187.2, therefore - program the refresh timer divider to 187 */ - write16(SH7750_RTCOR_KEY | 187, SH7750_RTCOR); - - /* Clear refresh counter */ - write16(SH7750_RFCR_KEY | 0, SH7750_RFCR); - - /* Select refresh counter base frequency as bus frequency/4 = 12 MHz */ - write16(SH7750_RTCSR_CKS_CKIO_DIV4 | SH7750_RTCSR_KEY, SH7750_RTCSR); - - /* Initialize Memory Control Register; disable refresh */ - write32((MCRDEF & ~SH7750_MCR_RFSH) | SH7750_MCR_PALL, SH7750_MCR); - - /* SDRAM power-up initialization require 100 microseconds delay after - stable power and clock fed; 100 microseconds corresponds to 7 refresh - intervals */ - while (read16(SH7750_RFCR) <= 7); - - /* Clear refresh timer counter */ - write16(SH7750_RTCNT_KEY | 0, SH7750_RTCNT); - - /* Clear refresh counter */ - write16(SH7750_RFCR_KEY | 0, SH7750_RFCR); - - /* Execute Precharge All command */ - write32(0, SH7750_SDRAM_MODE_A2_32BIT(0)); - - /* Initialize Memory Control Register; enable refresh, prepare to - SDRAM mode register setting */ - write32(MCRDEF | SH7750_MCR_MRSET, SH7750_MCR); - - /* Wait until at least 2 auto-refresh commands to be executed */ - while (read16(SH7750_RFCR) <= 10); - - /* SDRAM data width is 32 bit (4 bytes), cache line size is 32 bytes, - therefore burst length is 8 (32 / 4) */ - write8(0,SH7750_SDRAM_MODE_A2_32BIT( - SDRAM_MODE_BL_8 | - SDRAM_MODE_BT_SEQ | /* Only sequential burst mode supported - in SH7750 */ - SDRAM_MODE_CL_2 | /* CAS latency is 2 */ - SDRAM_MODE_OPC_BRBW) /* Burst read/burst write */ - ); - /* Bus State Controller initialized now */ - - /* Disable DMA controller */ - write32(0, SH7750_DMAOR); - - /* I/O port setup */ - /* Configure all port bits as output - to fasciliate debugging */ - write32( - SH7750_PCTRA_PBOUT(0) | SH7750_PCTRA_PBOUT(1) | - SH7750_PCTRA_PBOUT(2) | SH7750_PCTRA_PBOUT(3) | - SH7750_PCTRA_PBOUT(4) | SH7750_PCTRA_PBOUT(5) | - SH7750_PCTRA_PBOUT(6) | SH7750_PCTRA_PBOUT(7) | - SH7750_PCTRA_PBOUT(8) | SH7750_PCTRA_PBOUT(9) | - SH7750_PCTRA_PBOUT(10) | SH7750_PCTRA_PBOUT(11) | - SH7750_PCTRA_PBOUT(12) | SH7750_PCTRA_PBOUT(13) | - SH7750_PCTRA_PBOUT(14) | SH7750_PCTRA_PBOUT(15), - SH7750_PCTRA); - write32( - SH7750_PCTRB_PBOUT(16) | SH7750_PCTRB_PBOUT(17) | - SH7750_PCTRB_PBOUT(18) | SH7750_PCTRB_PBOUT(19), - SH7750_PCTRB); - /* Clear data in port */ - write32(0, SH7750_PDTRA); - write32(0, SH7750_PDTRB); - - /* Interrupt Controller Initialization */ - write16(SH7750_ICR_IRLM, SH7750_ICR); /* IRLs serves as an independent - interrupt request lines */ - /* Mask all requests at this time */ - write16( - (0 << SH7750_IPRA_TMU0_S) | - (0 << SH7750_IPRA_TMU1_S) | - (0 << SH7750_IPRA_TMU2_S) | - (0 << SH7750_IPRA_RTC_S), - SH7750_IPRA); - write16( - (0 << SH7750_IPRB_WDT_S) | - (0 << SH7750_IPRB_REF_S) | - (0 << SH7750_IPRB_SCI1_S), - SH7750_IPRB); - write16( - (0 << SH7750_IPRC_GPIO_S) | - (0 << SH7750_IPRC_DMAC_S) | - (0 << SH7750_IPRC_SCIF_S) | - (0 << SH7750_IPRC_HUDI_S), - SH7750_IPRC); - -} - -/* - * cache_on -- - * Enable instruction and operand caches - */ -void bsp_cache_on(void) -{ - switch (boot_mode) { - case SH4_BOOT_MODE_FLASH: - write32(SH7750_CCR_ICI | SH7750_CCR_ICE | - SH7750_CCR_OCI | SH7750_CCR_CB | SH7750_CCR_OCE, - SH7750_CCR); - break; - case SH4_BOOT_MODE_IPL: - __asm__ volatile ( - "mov #6, r0\n" - "xor r4, r4\n" - "trapa #0x3f\n" - : : : "r0", "r4"); - break; - default: /* unreachable */ - break; - } -} diff --git a/bsps/sh/gensh4/start/ispsh7750.c b/bsps/sh/gensh4/start/ispsh7750.c deleted file mode 100644 index edce9569fc..0000000000 --- a/bsps/sh/gensh4/start/ispsh7750.c +++ /dev/null @@ -1,316 +0,0 @@ -/* - * SH7750 interrupt support. - * - * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov - * - * Based on work: - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modified to reflect isp entries for sh7045 processor: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * August, 1999 - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - */ - -#include - -/* - * This is a exception vector table - * - * It has the same structure as the actual vector table (vectab) - */ - - -#include -#include -#include - -/* VBR register contents saved on startup -- used to hook exception by debug - * agent */ -void *_VBR_Saved; - -#define __STRINGIFY1__(x) #x -#define __STRINGIFY__(x) __STRINGIFY1__(x) - -#define STOP_TIMER \ - " mov.l TSTR_k,r0 \n" \ - " mov.b @r0,r1 \n" \ - " and #" __STRINGIFY__(~SH7750_TSTR_STR0) ",r1\n" \ - " mov.b r1,@r0 \n" - -#define START_TIMER \ - " mov.l TSTR_k,r0 \n" \ - " mov.b @r0,r1 \n" \ - " or #" __STRINGIFY__(SH7750_TSTR_STR0) ",r1\n" \ - " mov.b r1,@r0 \n" - -__asm__ (" .text\n" - " .balign 256\n" - " .global __vbr_base\n" - "__vbr_base:\n" - " .org __vbr_base + 0x100\n" - "vbr_100:\n" - " mov.l r0,@-r15\n" - " mov.l r1,@-r15\n" - " mov.l __VBR_Saved100_k, r0\n" - " mov.l offset100_k,r1\n" - " mov.l @r0,r0\n" - " add r1,r0\n" - " mov.l @r15+,r1\n" - " jmp @r0\n" - " mov.l @r15+,r0\n" - " .align 2\n" - "__VBR_Saved100_k:\n" - " .long __VBR_Saved\n" - "offset100_k:\n" - " .long 0x100\n" - - " .org __vbr_base + 0x400\n" - "vbr_400:\n" - " mov.l r0,@-r15\n" - " mov.l r1,@-r15\n" - " mov.l __VBR_Saved400_k, r0\n" - " mov.l offset400_k,r1\n" - " mov.l @r0,r0\n" - " add r1,r0\n" - " mov.l @r15+,r1\n" - " jmp @r0\n" - " mov.l @r15+,r0\n" - " .align 2\n" - "__VBR_Saved400_k:\n" - " .long __VBR_Saved\n" - "offset400_k:\n" - " .long 0x400\n" - - " .org __vbr_base + 0x600\n" - "vbr_600:\n" - " mov.l r0,@-r15 \n" - " mov.l r1,@-r15 \n" - " stc sr,r0 \n" - " mov.l __vbr_600_sr_and_k,r1\n" - " and r1,r0 \n" - " mov.l __vbr_600_sr_or_k,r1\n" - " or r1,r0 \n" - " ldc r0,sr \n" - " ldc.l @r15+,r1_bank\n" - " ldc.l @r15+,r0_bank\n" - " mov.l r0,@-r15 \n" - " mov.l r1,@-r15 \n" - " mov.l r2,@-r15 \n" - " mov.l r3,@-r15 \n" - " mov.l r4,@-r15 \n" - " mov.l r5,@-r15 \n" - " mov.l r6,@-r15 \n" - " mov.l r7,@-r15 \n" -#if 0 - " mov.l r8,@-r15 \n" - " mov.l r9,@-r15 \n" - " mov.l r10,@-r15 \n" - " mov.l r11,@-r15 \n" - " mov.l r12,@-r15 \n" - " mov.l r13,@-r15 \n" -#endif - " mov.l r14,@-r15 \n" - " sts.l fpscr,@-r15\n" - " sts.l fpul,@-r15 \n" - " mov.l __ISR_temp_fpscr_k,r0 \n" - " lds r0,fpscr \n" - " fmov fr0,@-r15 \n" - " fmov fr1,@-r15 \n" - " fmov fr2,@-r15 \n" - " fmov fr3,@-r15 \n" - " fmov fr4,@-r15 \n" - " fmov fr5,@-r15 \n" - " fmov fr6,@-r15 \n" - " fmov fr7,@-r15 \n" - " fmov fr8,@-r15 \n" - " fmov fr9,@-r15 \n" - " fmov fr10,@-r15 \n" - " fmov fr11,@-r15 \n" - " fmov fr12,@-r15 \n" - " fmov fr13,@-r15 \n" - " fmov fr14,@-r15 \n" - " fmov fr15,@-r15 \n" - - " sts.l pr,@-r15 \n" - " sts.l mach,@-r15 \n" - " sts.l macl,@-r15 \n" - " stc.l spc,@-r15 \n" - " stc.l ssr,@-r15 \n" - " mov r15,r14 \n" -#if 0 - " stc ssr,r0 \n" - " ldc r0,sr \n" -#endif - " mov.l __ISR_Handler_k, r1\n" - " mov.l _INTEVT_k,r4\n" - " mov.l @r4,r4 \n" - " shlr2 r4 \n" - " shlr r4 \n" - - " mov.l _ISR_Table_k,r0\n" - " mov.l @r0,r0 \n" - " add r4,r0 \n" - " mov.l @r0,r0 \n" - " cmp/eq #0,r0 \n" - " bt _ipl_hook \n" - - - " jsr @r1 \n" - " shlr2 r4 \n" - " mov r14,r15 \n" - " ldc.l @r15+,ssr \n" - " ldc.l @r15+,spc \n" - " lds.l @r15+,macl \n" - " lds.l @r15+,mach \n" - " lds.l @r15+,pr \n" - " mov.l __ISR_temp_fpscr_k,r0 \n" - " lds r0,fpscr \n" - - " fmov @r15+,fr15 \n" - " fmov @r15+,fr14 \n" - " fmov @r15+,fr13 \n" - " fmov @r15+,fr12 \n" - " fmov @r15+,fr11 \n" - " fmov @r15+,fr10 \n" - " fmov @r15+,fr9 \n" - " fmov @r15+,fr8 \n" - " fmov @r15+,fr7 \n" - " fmov @r15+,fr6 \n" - " fmov @r15+,fr5 \n" - " fmov @r15+,fr4 \n" - " fmov @r15+,fr3 \n" - " fmov @r15+,fr2 \n" - " fmov @r15+,fr1 \n" - " fmov @r15+,fr0 \n" - " lds.l @r15+,fpul \n" - " lds.l @r15+,fpscr\n" - " mov.l @r15+,r14 \n" -#if 0 - " mov.l @r15+,r13 \n" - " mov.l @r15+,r12 \n" - " mov.l @r15+,r11 \n" - " mov.l @r15+,r10 \n" - " mov.l @r15+,r9 \n" - " mov.l @r15+,r8 \n" -#endif - - " mov.l @r15+,r7 \n" - " mov.l @r15+,r6 \n" - " mov.l @r15+,r5 \n" - " mov.l @r15+,r4 \n" - " mov.l @r15+,r3 \n" - " mov.l @r15+,r2 \n" - " mov.l @r15+,r1 \n" - " mov.l @r15+,r0 \n" - " rte \n" - " nop \n" - " .align 2 \n" - "__vbr_600_sr_and_k: \n" - " .long " __STRINGIFY__(~(SH4_SR_RB | SH4_SR_BL)) "\n" - "__vbr_600_sr_or_k: \n" - " .long " __STRINGIFY__(SH4_SR_IMASK) "\n" - "__ISR_Handler_k: \n" - " .long ___ISR_Handler\n" - "_INTEVT_k: \n" - " .long " __STRINGIFY__(SH7750_INTEVT) "\n" - "_ISR_Table_k: \n" - " .long __ISR_Vector_table\n" - - "_ipl_hook: \n" - " mov r14,r15 \n" - " ldc.l @r15+,ssr \n" - " ldc.l @r15+,spc \n" - " lds.l @r15+,macl \n" - " lds.l @r15+,mach \n" - " lds.l @r15+,pr \n" - " mov.l __ISR_temp_fpscr_k,r0 \n" - " lds r0,fpscr \n" - " fmov @r15+,fr15 \n" - " fmov @r15+,fr14 \n" - " fmov @r15+,fr13 \n" - " fmov @r15+,fr12 \n" - " fmov @r15+,fr11 \n" - " fmov @r15+,fr10 \n" - " fmov @r15+,fr9 \n" - " fmov @r15+,fr8 \n" - " fmov @r15+,fr7 \n" - " fmov @r15+,fr6 \n" - " fmov @r15+,fr5 \n" - " fmov @r15+,fr4 \n" - " fmov @r15+,fr3 \n" - " fmov @r15+,fr2 \n" - " fmov @r15+,fr1 \n" - " fmov @r15+,fr0 \n" - " lds.l @r15+,fpul \n" - " lds.l @r15+,fpscr\n" - " mov.l @r15+,r14 \n" - - " mov.l @r15+,r13 \n" - " mov.l @r15+,r12 \n" - " mov.l @r15+,r11 \n" - " mov.l @r15+,r10 \n" - " mov.l @r15+,r9 \n" - " mov.l @r15+,r8 \n" - - - " mov.l @r15+,r7 \n" - " mov.l @r15+,r6 \n" - " mov.l @r15+,r5 \n" - " mov.l @r15+,r4 \n" - " mov.l @r15+,r3 \n" - " mov.l @r15+,r2 \n" - " mov.l __VBR_Saved600_k, r0\n" - " mov.l offset600_k,r1\n" - " mov.l @r0,r0\n" - " add r1,r0\n" - " mov.l @r15+,r1\n" - " jmp @r0\n" - " mov.l @r15+,r0\n" - " .align 2\n" - "__ISR_temp_fpscr_k: \n" - " .long " __STRINGIFY__(SH4_FPSCR_PR) " \n" - "__VBR_Saved600_k:\n" - " .long __VBR_Saved\n" - "offset600_k:\n" - " .long 0x600\n" - - ); - - -/************************************************ - * Dummy interrupt service procedure for - * interrupts being not allowed --> Trap 2 - ************************************************/ -__asm__ (" .section .text\n\ -.global __dummy_isp\n\ -__dummy_isp:\n\ - mov.l r14,@-r15\n\ - mov r15, r14\n\ - trapa #2\n\ - mov.l @r15+,r14\n\ - rte\n\ - nop"); diff --git a/bsps/sh/gensh4/start/linkcmds b/bsps/sh/gensh4/start/linkcmds deleted file mode 100644 index 1b356439f7..0000000000 --- a/bsps/sh/gensh4/start/linkcmds +++ /dev/null @@ -1,195 +0,0 @@ -/* - * This file contains GNU linker directives for an general SH4 - * board. - * - * Variations in memory size and allocation can be made by - * overriding some values with linker command-line arguments. - * - * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * - * http://www.rtems.org/license/LICENSE. - */ - - -OUTPUT_ARCH(sh) -ENTRY(_start) -STARTUP(start.o) - -/* Do we need any of these for elf? - __DYNAMIC = 0; */ - -_RamBase = DEFINED(_RamBase) ? _RamBase : 0x80000000; -_RamSize = DEFINED(_RamSize) ? _RamSize : 4M; -_RamEnd = _RamBase + _RamSize; -_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0; - -/* - * Area assignments: - * Area 0: Flash memory, SRAM interface - * Area 1: GDC - * Area 2: SDRAM - * Area 3-6: unused - */ -MEMORY -{ - ram : o = 0x88100000, l = 7M - rom : o = 0x80000000, l = 4M -} - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .text : - { - _start = .; - *(.text*) - - /* - * Special FreeBSD sysctl sections. - */ - . = ALIGN (16); - ___start_set_sysctl_set = .; - *(set_sysc*); /* set_sysctl_* but name is truncated by SH-coff */ - ___stop_set_sysctl_set = ABSOLUTE(.); - *(set_doma*); /* set_domain_* but name is truncated by SH-coff */ - *(set_pseu*); /* set_pseudo_* but name is truncated by SH-coff */ - - /* .gnu.warning sections are handled specially by elf32.em. */ - *(.gnu.warning) - *(.gnu.linkonce.t*) - } > ram - .rela.dyn : - { - *(.rela.init) - *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) - *(.rela.fini) - *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) - *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) - *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) - *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) - *(.rela.ctors) - *(.rela.dtors) - *(.rela.got) - *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) - *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) - *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) - *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) - *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) - } >ram - _etext = .; - PROVIDE (etext = .); - .init . : { KEEP(*(.init)) } > ram =0 - .fini . : { KEEP(*(.fini)) } > ram =0 - .ctors . : { KEEP(*(.ctors)) } > ram =0 - .dtors . : { KEEP(*(.dtors)) } > ram =0 - .rodata : - { - *(.rodata) - *(.rodata.*) - KEEP (*(SORT(.rtemsroset.*))) - *(.gnu.linkonce.r*) - } > ram - .tdata : { - __TLS_Data_begin = .; - *(.tdata .tdata.* .gnu.linkonce.td.*) - __TLS_Data_end = .; - } > ram - .tbss : { - __TLS_BSS_begin = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) - __TLS_BSS_end = .; - } > ram - __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin; - __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin; - __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin; - __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin; - __TLS_Size = __TLS_BSS_end - __TLS_Data_begin; - __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); - - /* Adjust the address for the data segment. We want to adjust up to - the same address within the page on the next page up. */ - . = ALIGN(128) + (. & (128 - 1)); - .data : - { - copy_start = .; - *(.data*) - KEEP (*(SORT(.rtemsrwset.*))) - *(.gcc_exc*) - ___EH_FRAME_BEGIN__ = .; - *(.eh_fram*) - ___EH_FRAME_END__ = .; - LONG(0); - *(.gcc_except_table*) - *(.gnu.linkonce.d*) - SORT(CONSTRUCTORS) - copy_end = .; - } > ram - .eh_frame : { *(.eh_frame) } > ram - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - .bss : - { - __bss_start = .; - *(.dynbss) - *(.bss .bss* .gnu.linkonce.b*) - *(COMMON) - /* Align here to ensure that the .bss section occupies space up to - _end. Align after .bss to ensure correct alignment even if the - .bss section disappears because there are no input sections. */ - . = ALIGN(32 / 8); - __bss_end = .; - } > ram - - .noinit (NOLOAD) : { - *(SORT_BY_NAME (SORT_BY_ALIGNMENT (.noinit*))) - } > ram - - .rtemsstack (NOLOAD) : { - *(SORT(.rtemsstack.*)) - } > ram - - _WorkAreaBase = . ; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* These must appear regardless of . */ - - /* Addition to let linker know about custom section for GDB pretty-printing support. */ - .debug_gdb_scripts 0 : { *(.debug_gdb_scripts) } -} diff --git a/bsps/sh/gensh4/start/linkcmds.rom b/bsps/sh/gensh4/start/linkcmds.rom deleted file mode 100644 index 127bc38763..0000000000 --- a/bsps/sh/gensh4/start/linkcmds.rom +++ /dev/null @@ -1,235 +0,0 @@ -/* - * This file contains GNU linker directives for an general SH4 - * board. - * - * Variations in memory size and allocation can be made by - * overriding some values with linker command-line arguments. - * - * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * - * http://www.rtems.org/license/LICENSE. - */ - - -OUTPUT_FORMAT("elf32-shl", "elf32-shl", - "elf32-shl") -OUTPUT_ARCH(sh) -ENTRY(_start) -STARTUP(start.o) - -/* Do we need any of these for elf? - __DYNAMIC = 0; */ - -_RamBase = DEFINED(_RamBase) ? _RamBase : 0x88000000; -_RamSize = DEFINED(_RamSize) ? _RamSize : 8M; -_RamEnd = _RamBase + _RamSize; -_HeapSize = DEFINED(_HeapSize) ? _HeapSize : (2 * 1024 * 1024); - -/* - * Area assignments: - * Area 0: Flash memory, SRAM interface - * Area 1: GDC - * Area 2: SDRAM - * Area 3-6: unused - */ -MEMORY -{ -/* - * Real values - */ - ram : o = 0x88000000, l = 8M - rom : o = 0x80000000, l = 4M -/* - * Fake values to test from gdb - */ -/* - ram : o = 0x88100000, l = 4M - rom : o = 0x88500000, l = 3M -*/ -} - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .init : - { - KEEP (*(.init)) - } =0 - .text : - { - *(.text*) - - /* - * Special FreeBSD sysctl sections. - */ - . = ALIGN (16); - ___start_set_sysctl_set = .; - *(set_sysc*); /* set_sysctl_* but name is truncated by SH-coff */ - ___stop_set_sysctl_set = ABSOLUTE(.); - *(set_doma*); /* set_domain_* but name is truncated by SH-coff */ - *(set_pseudo_*); - - /* .gnu.warning sections are handled specially by elf32.em. */ - *(.gnu.warning) - *(.gnu.linkonce.t*) - } > rom - _etext = .; - PROVIDE (etext = .); - .rela.dyn : - { - *(.rela.init) - *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) - *(.rela.fini) - *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) - *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) - *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) - *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) - *(.rela.ctors) - *(.rela.dtors) - *(.rela.got) - *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) - *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) - *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) - *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) - *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) - } >ram - .fini : - { - KEEP (*(.fini)) - } =0 - .rodata : - { - *(.rodata) - *(.rodata.*) - KEEP (*(SORT(.rtemsroset.*))) - *(.gnu.linkonce.r*) - . = ALIGN(32); - } > rom - .tdata : { - __TLS_Data_begin = .; - *(.tdata .tdata.* .gnu.linkonce.td.*) - __TLS_Data_end = .; - } > rom - .tbss : { - __TLS_BSS_begin = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) - __TLS_BSS_end = .; - } > rom - __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin; - __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin; - __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin; - __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin; - __TLS_Size = __TLS_BSS_end - __TLS_Data_begin; - __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); - .ctors : - { - ___ctors = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - ___ctors_end = .; - } > rom - .dtors : - { - ___dtors = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - ___dtors_end = .; - copy_start_in_rom = .; - } > rom - - /* Adjust the address for the data segment. We want to adjust up to - the same address within the page on the next page up. */ - . = ALIGN(128) + (. & (128 - 1)); - .data : AT(LOADADDR(.dtors) + SIZEOF(.dtors)) - { - copy_start = .; - *(.data) - *(.data.*) - KEEP (*(SORT(.rtemsrwset.*))) - *(.gnu.linkonce.d*) - SORT(CONSTRUCTORS) - copy_end = .; - } > ram - .eh_frame : { *(.eh_frame) } > ram - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - .bss : - { - __bss_start = .; - *(.dynbss) - *(.bss .bss* .gnu.linkonce.b*) - *(COMMON) - /* Align here to ensure that the .bss section occupies space up to - _end. Align after .bss to ensure correct alignment even if the - .bss section disappears because there are no input sections. */ - . = ALIGN(32 / 8); - __bss_end = .; - } > ram - - .noinit (NOLOAD) : { - *(SORT_BY_NAME (SORT_BY_ALIGNMENT (.noinit*))) - } > ram - - .rtemsstack (NOLOAD) : { - *(SORT(.rtemsstack.*)) - } > ram - - _WorkAreaBase = . ; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* These must appear regardless of . */ -} diff --git a/bsps/sh/gensh4/start/linkcmds.rom2ram b/bsps/sh/gensh4/start/linkcmds.rom2ram deleted file mode 100644 index 89d8c59bd1..0000000000 --- a/bsps/sh/gensh4/start/linkcmds.rom2ram +++ /dev/null @@ -1,239 +0,0 @@ -/* - * This file contains GNU linker directives for an general SH4 - * board. - * - * Variations in memory size and allocation can be made by - * overriding some values with linker command-line arguments. - * - * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * - * http://www.rtems.org/license/LICENSE. - */ - - -OUTPUT_FORMAT("elf32-shl", "elf32-shl", - "elf32-shl") -OUTPUT_ARCH(sh) -ENTRY(_start) -STARTUP(start.o) - -/* Do we need any of these for elf? - __DYNAMIC = 0; */ - -_RamBase = DEFINED(_RamBase) ? _RamBase : 0x88000000; -_RamSize = DEFINED(_RamSize) ? _RamSize : 8M; -_RamEnd = _RamBase + _RamSize; -_HeapSize = DEFINED(_HeapSize) ? _HeapSize : (2 * 1024 * 1024); - -/* - * Area assignments: - * Area 0: Flash memory, SRAM interface - * Area 1: GDC - * Area 2: SDRAM - * Area 3-6: unused - */ -MEMORY -{ -/* - * Real values - */ - ram : o = 0x88000000, l = 8M - rom : o = 0x80000000, l = 4M -/* - * Fake values to test from gdb - */ -/* - ram : o = 0x88100000, l = 4M - rom : o = 0x88500000, l = 3M -*/ -} - -SECTIONS -{ - rom : { - copy_start_in_rom = .; - } >rom - - /* Read-only sections, merged into text segment: */ - .init : - { - KEEP (*(.init)) - } =0 - .text : AT(copy_start_in_rom) - { - copy_start = .; - *(.text*) - - /* - * Special FreeBSD sysctl sections. - */ - . = ALIGN (16); - ___start_set_sysctl_set = .; - *(set_sysc*); /* set_sysctl_* but name is truncated by SH-coff */ - ___stop_set_sysctl_set = ABSOLUTE(.); - *(set_doma*); /* set_domain_* but name is truncated by SH-coff */ - *(set_pseudo_*); - - /* .gnu.warning sections are handled specially by elf32.em. */ - *(.gnu.warning) - *(.gnu.linkonce.t*) - } > ram - _etext = .; - PROVIDE (etext = .); - .fini : - { - KEEP (*(.fini)) - } =0 - .rodata : AT(LOADADDR(.text) + SIZEOF(.text)) - { - *(.rodata) - *(.rodata.*) - KEEP (*(SORT(.rtemsroset.*))) - *(.gnu.linkonce.r*) - . = ALIGN(32); - } > ram - .tdata : { - __TLS_Data_begin = .; - *(.tdata .tdata.* .gnu.linkonce.td.*) - __TLS_Data_end = .; - } > ram - .tbss : { - __TLS_BSS_begin = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) - __TLS_BSS_end = .; - } > ram - __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin; - __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin; - __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin; - __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin; - __TLS_Size = __TLS_BSS_end - __TLS_Data_begin; - __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); - .ctors : AT(LOADADDR(.rodata) + SIZEOF(.rodata)) - { - ___ctors = .; - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - /* We don't want to include the .ctor section from - from the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - ___ctors_end = .; - } > ram - .dtors : AT(LOADADDR(.ctors) + SIZEOF(.ctors)) - { - ___dtors = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - ___dtors_end = .; - } > ram - - /* Adjust the address for the data segment. We want to adjust up to - the same address within the page on the next page up. */ - . = ALIGN(128) + (. & (128 - 1)); - .data : AT(LOADADDR(.dtors) + SIZEOF(.dtors)) - { - *(.data) - *(.data.*) - KEEP (*(SORT(.rtemsrwset.*))) - *(.gnu.linkonce.d*) - SORT(CONSTRUCTORS) - copy_end = .; - } > ram - .eh_frame : { *(.eh_frame) } > ram - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - .bss : - { - __bss_start = .; - *(.dynbss) - *(.bss .bss* .gnu.linkonce.b*) - *(COMMON) - /* Align here to ensure that the .bss section occupies space up to - _end. Align after .bss to ensure correct alignment even if the - .bss section disappears because there are no input sections. */ - . = ALIGN(32 / 8); - __bss_end = .; - } > ram - - .rela.dyn : - { - *(.rela.init) - *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) - *(.rela.fini) - *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) - *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) - *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) - *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) - *(.rela.ctors) - *(.rela.dtors) - *(.rela.got) - *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) - *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) - *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) - *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) - *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) - } >ram - - .noinit (NOLOAD) : { - *(SORT_BY_NAME (SORT_BY_ALIGNMENT (.noinit*))) - } > ram - - .rtemsstack (NOLOAD) : { - *(SORT(.rtemsstack.*)) - } > ram - - _WorkAreaBase = . ; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* These must appear regardless of . */ -} diff --git a/bsps/sh/gensh4/start/start.S b/bsps/sh/gensh4/start/start.S deleted file mode 100644 index 57b23b6845..0000000000 --- a/bsps/sh/gensh4/start/start.S +++ /dev/null @@ -1,270 +0,0 @@ -/* - * start.S -- Initialization code for SH7750 generic BSP - * - * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov - * - * Based on work: - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * Modified to reflect Hitachi EDK SH7045F: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - * - * COPYRIGHT (c) 1999-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include -#include "rtems/score/sh4_regs.h" -#include "rtems/score/sh7750_regs.h" - - BEGIN_CODE - PUBLIC(start) - -/* - * Algorithm of the first part of the start(): - * - * 1. Initialize stack - * 2. Are we from reset or from gdb? Set value for boot_mode in r9. - * 3. Initialize hardware if we are from reset. Cache is off. - * 4. Copy data from flash to ram; set up boot mode and jump to real address. - * 5. Zero out bss. - * 6. Turn memory cach on. - */ - -SYM (start): - ! install the stack pointer - mov.l stack_k,r15 - - mov.l initial_sr_k,r0 - ldc r0,ssr - ldc r0,sr - - ! let us see if we are from gdb stub or from power-on reset - bsr fake_func - nop -fake_func: - - sts pr, r0 - shlr8 r0 - mov.l reset_pc_value_shift_8_k, r1 - cmp/eq r0, r1 - movt r9 ! r9 == ! boot_mode - neg r9, r9 - add #1, r9 ! r9 == boot_mode - - ! what is in boot_mode? - cmp/pl r9 ! r9 > 0 -> T = 1 - - ! if boot_mode != SH4_BOOT_MODE_FLASH - bt hw_init_end - nop - -#if START_HW_INIT /* from $RTEMS_BSP.cfg */ - ! Initialize minimal hardware - ! to run hw_init we need to calculate its address - ! as it is before data copying - mov.l hw_init_k, r0 - mov.l copy_start_k, r1 - mov.l copy_end_k, r2 - cmp/ge r0, r1 - bt 0f - cmp/ge r0, r2 - bf 0f - ! if copy_start <= hw_init <= copy_end then - neg r1, r1 - mov.l copy_start_in_rom_k, r3 - add r1,r0 - add r3, r0 -0: - jsr @r0 - nop !delay slot -#endif /* START_HW_INIT */ -hw_init_end: - -#if COPY_DATA_FROM_ROM - ! copy data from rom to ram - mov.l copy_start_k, r0 - mov.l copy_end_k, r1 - mov.l copy_start_in_rom_k, r2 - - ! if copy_from == copy_to do not copy anything - cmp/eq r0, r2 - bt real_address - nop - -copy_data_cycle: - cmp/ge r1, r0 - bt end_of_copy_data_cycle - nop - mov.l @r2+, r3 - mov.l r3, @r0 - add #4, r0 - bra copy_data_cycle - nop - -end_of_copy_data_cycle: -#endif - ! go to 0x8....... adresses - mov.l real_address_k, r0 - lds r0, pr - rts - nop -real_address: - ! write boot_mode to ram - mov.l boot_mode_k, r5 - mov.l r9, @r5 - -zero_bss: - ! zero out bss - mov.l __bss_start_k,r0 - mov.l __bss_end_k,r1 - mov #0,r2 -0: - mov.l r2,@r0 - add #4,r0 - cmp/ge r0,r1 - bt 0b - nop - - ! Turn cache on - mov.l cache_on_k, r0 - jsr @r0 - nop !delay slot - - ! Save old value of VBR register. We will need it to allow - ! debugger agent hook exceptions. - mov.l __VBR_Saved_k,r0 - stc vbr,r5 - mov.l r5,@r0 - ! Set up VBR register - mov.l _vbr_base_k,r0 - ldc r0,vbr - - ! initialise fpscr for gcc - mov.l set_fpscr_k, r1 - jsr @r1 - nop - - ! Set FPSCR register - mov.l initial_fpscr_k,r0 - lds r0,fpscr - - ! call the mainline - mov #0,r4 ! argc - mov.l main_k,r0 - jsr @r0 - nop - - ! call exit - mov r0,r4 - mov.l exit_k,r0 - jsr @r0 - or r0,r0 - - .global _stop -_stop: - mov #11,r0 - mov #0,r4 - trapa #0x3f - nop -__stop: - bra __stop - nop - - END_CODE - - .align 2 -#if START_HW_INIT -copy_start_k: - .long copy_start -copy_end_k: - .long copy_end -#endif -#if COPY_DATA_FROM_ROM -copy_start_in_rom_k: - .long copy_start_in_rom -#endif - -real_address_k: - .long real_address -set_fpscr_k: - .long ___set_fpscr -_vbr_base_k: - .long SYM(_vbr_base) -__VBR_Saved_k: - .long SYM(_VBR_Saved) -stack_k: - .long SYM(_ISR_Stack_area_end) -__bss_start_k: - .long __bss_start -__bss_end_k: - .LONG __bss_end -main_k: - .long SYM(boot_card) -exit_k: - .long SYM(_exit) - -#if START_HW_INIT /* from $RTEMS_BSP.cfg */ -hw_init_k: - .long SYM(early_hw_init) -#endif /* START_HW_INIT */ - -cache_on_k: - .long SYM(bsp_cache_on) - -vects_k: - .long SYM(vectab) -vects_size: - .word 255 - - .align 2 -initial_sr_k: - .long SH4_SR_MD | SH4_SR_IMASK -initial_fpscr_k: -#ifdef __SH4__ - .long SH4_FPSCR_DN | SH4_FPSCR_PR | SH4_FPSCR_RM -#else - .long SH4_FPSCR_DN | SH4_FPSCR_RM -#endif - -reset_pc_value_shift_8_k: - .long 0xa00000 - -boot_mode_k: - .long _boot_mode - -#ifdef __ELF__ - .section .bss,"aw" -#else - .section .bss -#endif - - .global __sh4sim_dummy_register -__sh4sim_dummy_register: - .long 0 - - .section .data - .global _boot_mode -_boot_mode: - .long 0 diff --git a/bsps/sh/shared/console/console.c b/bsps/sh/shared/console/console.c deleted file mode 100644 index 5547696fed..0000000000 --- a/bsps/sh/shared/console/console.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * /dev/console for Hitachi SH 703X - * - * This driver installs an alternate device name (e.g. /dev/console for - * the designated console device /dev/console. - */ - -/* - * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * COPYRIGHT (c) 1998, 2014. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include -#include -#include -#include - -#include - -#ifndef BSP_CONSOLE_DEVNAME -#error Missing BSP_CONSOLE_DEVNAME -#endif - -/* console_initialize - * - * This routine initializes the console IO driver. - */ -rtems_device_driver console_initialize( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg -) -{ - rtems_device_driver status; - struct stat st; - int rv; - - rv = stat( BSP_CONSOLE_DEVNAME, &st ); - if ( rv != 0 ) - rtems_fatal_error_occurred(rv); - - status = rtems_io_register_name( - "/dev/console", - rtems_filesystem_dev_major_t( st.st_rdev ), - rtems_filesystem_dev_minor_t( st.st_rdev ) - ); - if (status != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred(status); - - return RTEMS_SUCCESSFUL; -} - -/* - * Open entry point - */ -rtems_device_driver console_open( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - rtems_fatal_error_occurred(-1); -} - -/* - * Close entry point - */ -rtems_device_driver console_close( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - rtems_fatal_error_occurred(-1); -} - -/* - * read bytes from the serial port. We only have stdin. - */ -rtems_device_driver console_read( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - rtems_fatal_error_occurred(-1); -} - -/* - * write bytes to the serial port. Stdout and stderr are the same. - */ -rtems_device_driver console_write( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - rtems_fatal_error_occurred(-1); -} - -/* - * IO Control entry point - */ -rtems_device_driver console_control( - rtems_device_major_number major, - rtems_device_minor_number minor, - void * arg -) -{ - rtems_fatal_error_occurred(-1); -} diff --git a/bsps/sh/shared/doxygen.h b/bsps/sh/shared/doxygen.h deleted file mode 100644 index e529f13080..0000000000 --- a/bsps/sh/shared/doxygen.h +++ /dev/null @@ -1,15 +0,0 @@ -/** - * @file - * - * @ingroup RTEMSImplDoxygen - * - * @brief This header file defines sh-specific groups. - */ - -/** - * @defgroup RTEMSBSPsSH SuperH (sh) - * - * @ingroup RTEMSBSPs - * - * @brief SuperH Board Support Packages. - */ diff --git a/bsps/sh/shared/start/bsphwinit.c b/bsps/sh/shared/start/bsphwinit.c deleted file mode 100644 index 66786be8f9..0000000000 --- a/bsps/sh/shared/start/bsphwinit.c +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * This is a dummy bsp_hw_init routine. - */ - -/* - * COPYRIGHT (c) 1989-2014. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -void bsp_hw_init( void ) -{ -} diff --git a/bsps/sh/shared/start/bspstart.c b/bsps/sh/shared/start/bspstart.c deleted file mode 100644 index a2b0110874..0000000000 --- a/bsps/sh/shared/start/bspstart.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This routine does the bulk of the system initialization. - */ - -/* - * COPYRIGHT (c) 2001. - * Ralf Corsepius (corsepiu@faw.uni-ulm.de). - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * COPYRIGHT (c) 2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include -#include -#include - -uint32_t bsp_clicks_per_second; - -#ifndef START_HW_INIT - void bsp_hw_init(void); -#endif - -/* - * bsp_start - * - * This routine does the bulk of the system initialization. - */ -void bsp_start( void ) -{ - /* - * For real boards you need to setup the hardware - * and need to copy the vector table from rom to ram. - * - * Depending on the board this can either be done from inside the rom - * startup code, rtems startup code or here. - */ - - #ifndef START_HW_INIT - /* board hardware setup here, or from 'start.S' */ - bsp_hw_init(); - #endif - - /* - * initialize the device driver parameters - */ - bsp_clicks_per_second = CPU_CLOCK_RATE_HZ; -} diff --git a/bsps/sh/shared/start/setvec.c b/bsps/sh/shared/start/setvec.c deleted file mode 100644 index 5d11e64f72..0000000000 --- a/bsps/sh/shared/start/setvec.c +++ /dev/null @@ -1,55 +0,0 @@ -/* set_vector - * - * NOTE: This function is considered OBSOLETE and may vanish soon. - * Calls to set_vector should be replaced by calls to - * rtems_interrupt_catch or _CPU_ISR_install_raw_handler. - * - * This routine installs an interrupt vector on the target Board/CPU. - * This routine is allowed to be as board dependent as necessary. - * - * INPUT: - * handler - interrupt handler entry point - * vector - vector number - * type - 0 indicates raw hardware connect - * 1 indicates RTEMS interrupt connect - * - * RETURNS: - * address of previous interrupt handler - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include -#include - -sh_isr_entry set_vector( /* returns old vector */ - rtems_isr_entry handler, /* isr routine */ - rtems_vector_number vector, /* vector number */ - int type /* RTEMS or RAW intr */ -) -{ - sh_isr_entry previous_isr; - - if ( type ) - rtems_interrupt_catch( handler, vector, (rtems_isr_entry *) &previous_isr ); - else { - _CPU_ISR_install_raw_handler( vector, handler, &previous_isr ); - } - - return previous_isr; -} diff --git a/bsps/sh/shsim/README.md b/bsps/sh/shsim/README.md deleted file mode 100644 index 564f936d95..0000000000 --- a/bsps/sh/shsim/README.md +++ /dev/null @@ -1,46 +0,0 @@ -shsim -===== - -Simple BSP for the SH simulator built into gdb. - -Simulator Invocation --------------------- -```shell -sh-rtems[elf|]-gdb -(gdb) target sim -(gdb) set archi [sh|sh2] -(gdb) load -(gdb) run -``` - -Status ------- -* The simulator invocation procedure outlined above produces error messages -with gdb-5.0, nevertheless seems to work. With gdb versions > 5.0 these -error messages are gone. I.e. if you plan to seriously work with the gdb -simulator better use gdb versions > 5.0. - -* gdb's simulator is not able to correctly emulate memory areas esp. shadowing -and non-consecutive memory. I.e. access to memory areas besides area 0 will -(bogusly) generate SIGBUS exceptions. This includes access to area 5 -(On-chip peripherials) and prevents simulation of configuration and access -to on-chip peripherials. - -* Due to limitations of the simulator you will only be able to run -applications which do not try to access any SH control registers. - -Currently, this excludes all applications, which apply timers and serial -devices, i.e. almost any real world application. - -* This BSP supports 3 different console devices (cf. configure --help): -- trap34, an interface base on gdb's trap34 emulation. Known to work with - gdb-5.0. -- gdbsci1, a stripped down sci device driver adapted to apply gdb's sci1 -emulation. This is known to fail with gdb-5.0, because of a bug in gdb-5.0's -sh-sim, a patch is submitted, but .. ~== -- devnull, redirection of console io to /dev/null. Try to single step this, -if you want to understand the details on how SH-RTEMS console redirection -works. - -NOTE: the trap34 interface is incomplete and is temporarily disabled -inside of configure.in. diff --git a/bsps/sh/shsim/config/simsh1-testsuite.tcfg b/bsps/sh/shsim/config/simsh1-testsuite.tcfg deleted file mode 100644 index 675894d12d..0000000000 --- a/bsps/sh/shsim/config/simsh1-testsuite.tcfg +++ /dev/null @@ -1,16 +0,0 @@ -# -# simsh1 RTEMS Test Database. -# -# Format is one line per test that is _NOT_ built. -# - -include: testdata/require-tick-isr.tcfg -include: testdata/disable-intrcritical-tests.tcfg -include: testdata/disable-iconv-tests.tcfg - -exclude: fileio -exclude: fsdosfsname01 -exclude: iostream -exclude: linpack -exclude: record02 -exclude: utf8proc01 diff --git a/bsps/sh/shsim/config/simsh1.cfg b/bsps/sh/shsim/config/simsh1.cfg deleted file mode 100644 index 0f1da687a8..0000000000 --- a/bsps/sh/shsim/config/simsh1.cfg +++ /dev/null @@ -1,18 +0,0 @@ -# -# simsh1.cfg -# -# default configuration for gdb-simulation of Hitachi sh1 processors - -include $(RTEMS_ROOT)/make/custom/default.cfg - -RTEMS_CPU=sh - -# This contains the compiler options necessary to select the CPU model -# and (hopefully) optimize for it. -CPU_CFLAGS = -m1 - -# optimize flag: typically -O2 -CFLAGS_OPTIMIZE_V = -O2 -g -CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections - -LDFLAGS = -Wl,--gc-sections diff --git a/bsps/sh/shsim/config/simsh2-testsuite.tcfg b/bsps/sh/shsim/config/simsh2-testsuite.tcfg deleted file mode 100644 index b3d57083e0..0000000000 --- a/bsps/sh/shsim/config/simsh2-testsuite.tcfg +++ /dev/null @@ -1,16 +0,0 @@ -# -# simsh2 RTEMS Test Database. -# -# Format is one line per test that is _NOT_ built. -# - -include: testdata/require-tick-isr.tcfg -include: testdata/disable-intrcritical-tests.tcfg -include: testdata/disable-iconv-tests.tcfg - -exclude: fileio -exclude: fsdosfsname01 -exclude: iostream -exclude: linpack -exclude: record02 -exclude: utf8proc01 diff --git a/bsps/sh/shsim/config/simsh2.cfg b/bsps/sh/shsim/config/simsh2.cfg deleted file mode 100644 index cde1fb2fbf..0000000000 --- a/bsps/sh/shsim/config/simsh2.cfg +++ /dev/null @@ -1,18 +0,0 @@ -# -# simsh2.cfg -# -# default configuration for gdb-simulation of Hitachi sh2 processors - -include $(RTEMS_ROOT)/make/custom/default.cfg - -RTEMS_CPU=sh - -# This contains the compiler options necessary to select the CPU model -# and (hopefully) optimize for it. -CPU_CFLAGS = -m2 - -# optimize flag: typically -O2 -CFLAGS_OPTIMIZE_V = -O2 -g -CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections - -LDFLAGS = -Wl,--gc-sections diff --git a/bsps/sh/shsim/config/simsh2e-testsuite.tcfg b/bsps/sh/shsim/config/simsh2e-testsuite.tcfg deleted file mode 100644 index c7fbb4a8bc..0000000000 --- a/bsps/sh/shsim/config/simsh2e-testsuite.tcfg +++ /dev/null @@ -1,15 +0,0 @@ -# -# The GDB SH Simulator does not have a tick interrupt -# and the simsh2e configuration has limited memory. -# - -include: testdata/require-tick-isr.tcfg -include: testdata/disable-intrcritical-tests.tcfg -include: testdata/disable-iconv-tests.tcfg - -exclude: fileio -exclude: fsdosfsname01 -exclude: iostream -exclude: linpack -exclude: record02 -exclude: utf8proc01 diff --git a/bsps/sh/shsim/config/simsh2e.cfg b/bsps/sh/shsim/config/simsh2e.cfg deleted file mode 100644 index ce34d26d78..0000000000 --- a/bsps/sh/shsim/config/simsh2e.cfg +++ /dev/null @@ -1,17 +0,0 @@ -# -# Config file for the sh simulator in gdb as SH2E -# - -include $(RTEMS_ROOT)/make/custom/default.cfg - -RTEMS_CPU=sh - -# This contains the compiler options necessary to select the CPU model -# and (hopefully) optimize for it. -CPU_CFLAGS = -m2e -ml - -# optimize flag: typically -O2 -CFLAGS_OPTIMIZE_V = -O2 -g -CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections - -LDFLAGS = -Wl,--gc-sections diff --git a/bsps/sh/shsim/config/simsh4-testsuite.tcfg b/bsps/sh/shsim/config/simsh4-testsuite.tcfg deleted file mode 100644 index 5b768d100a..0000000000 --- a/bsps/sh/shsim/config/simsh4-testsuite.tcfg +++ /dev/null @@ -1,15 +0,0 @@ -# -# The GDB SH Simulator does not have a tick interrupt -# and the simsh4 configuration has limited memory. -# - -include: testdata/require-tick-isr.tcfg -include: testdata/disable-intrcritical-tests.tcfg -include: testdata/disable-iconv-tests.tcfg - -exclude: fileio -exclude: fsdosfsname01 -exclude: iostream -exclude: linpack -exclude: record02 -exclude: utf8proc01 diff --git a/bsps/sh/shsim/config/simsh4.cfg b/bsps/sh/shsim/config/simsh4.cfg deleted file mode 100644 index c23a8b93b5..0000000000 --- a/bsps/sh/shsim/config/simsh4.cfg +++ /dev/null @@ -1,17 +0,0 @@ -# -# Config file for the sh simulator in gdb -# - -include $(RTEMS_ROOT)/make/custom/default.cfg - -RTEMS_CPU=sh - -# This contains the compiler options necessary to select the CPU model -# and (hopefully) optimize for it. -CPU_CFLAGS = -m4 -ml - -# optimize flag: typically -O2 -CFLAGS_OPTIMIZE_V = -O2 -g -CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections - -LDFLAGS = -Wl,--gc-sections diff --git a/bsps/sh/shsim/console/console-debugio.c b/bsps/sh/shsim/console/console-debugio.c deleted file mode 100644 index 24d37dcc49..0000000000 --- a/bsps/sh/shsim/console/console-debugio.c +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/** - * @file - * @brief Stub printk() support - */ - -/* - * COPYRIGHT (c) 1989-2014. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * To support printk - */ - -#include -#include - -void console_outbyte_polled( - int port, - char ch -); - -static void BSP_output_char_f(char c) -{ - console_outbyte_polled( 0, c ); -} - -BSP_output_char_function_type BSP_output_char = BSP_output_char_f; -BSP_polling_getchar_function_type BSP_poll_char = NULL; diff --git a/bsps/sh/shsim/console/console-io.c b/bsps/sh/shsim/console/console-io.c deleted file mode 100644 index ee4fadca0c..0000000000 --- a/bsps/sh/shsim/console/console-io.c +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * This file contains the hardware specific portions of the TTY driver - * for the simulators stdin/out. - */ - -/* - * COPYRIGHT (c) 1989-2011. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include - -/* - * console_initialize_hardware - * - * This routine initializes the console hardware. - */ -void console_initialize_hardware(void) -{ -} - -/* - * console_outbyte_polled - * - * This routine transmits a character using polling. - */ -void console_outbyte_polled( - int port, - char ch -) -{ - __trap34 (SYS_write, 1, &ch, 1); -} - -/* - * console_inbyte_nonblocking - * - * This routine polls for a character. - */ -int console_inbyte_nonblocking( - int port -) -{ - unsigned char c; - - return __trap34 (SYS_read, 0, &c, 1); -} diff --git a/bsps/sh/shsim/console/console-support.S b/bsps/sh/shsim/console/console-support.S deleted file mode 100644 index 63f72f794b..0000000000 --- a/bsps/sh/shsim/console/console-support.S +++ /dev/null @@ -1,18 +0,0 @@ -/* - * newlib-1.8.2/newlib/libc/sys/sh/trap.S - */ - .text - .global ___trap34 -___trap34: - trapa #34 - tst r1,r1 ! r1 is errno - bt ret - mov.l perrno,r2 - mov.l r1,@r2 -ret: - rts - nop - - .align 2 -perrno: - .long _errno diff --git a/bsps/sh/shsim/include/bsp.h b/bsps/sh/shsim/include/bsp.h deleted file mode 100644 index 80e2f096ea..0000000000 --- a/bsps/sh/shsim/include/bsp.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - * @file - * - * @ingroup RTEMSBSPsSHSim - * - * @brief Global BSP definitions. - */ - -/* - * SH-gdb simulator BSP - * - * This include file contains all board IO definitions. - */ - -/* - * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) - * - * COPYRIGHT (c) 2001, Ralf Corsepius, Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * COPYRIGHT (c) 2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_SH_SHSIM_BSP_H -#define LIBBSP_SH_SHSIM_BSP_H - -/** - * @defgroup RTEMSBSPsSHSim Simulator - * - * @ingroup RTEMSBSPsSH - * - * @brief Simulator Board Support Package. - * - * @{ - */ - -#ifndef ASM - -#include - -#include -#include - -/* - * FIXME: One of these would be enough. - */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* Constants */ - -void *clock_driver_sim_idle_body(uintptr_t); -#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body - -/* - * BSP methods that cross file boundaries. - */ -int _sys_exit (int n); -void bsp_hw_init(void); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -/** @} */ - -#endif diff --git a/bsps/sh/shsim/include/bsp/irq.h b/bsps/sh/shsim/include/bsp/irq.h deleted file mode 100644 index 8a97d7a1b0..0000000000 --- a/bsps/sh/shsim/include/bsp/irq.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/bsps/sh/shsim/include/bsp/syscall.h b/bsps/sh/shsim/include/bsp/syscall.h deleted file mode 100644 index e5cde7217b..0000000000 --- a/bsps/sh/shsim/include/bsp/syscall.h +++ /dev/null @@ -1,32 +0,0 @@ -#define SYS_exit 1 -#define SYS_fork 2 - -#define SYS_read 3 -#define SYS_write 4 -#define SYS_open 5 -#define SYS_close 6 -#define SYS_wait4 7 -#define SYS_creat 8 -#define SYS_link 9 -#define SYS_unlink 10 -#define SYS_execv 11 -#define SYS_chdir 12 -#define SYS_mknod 14 -#define SYS_chmod 15 -#define SYS_chown 16 -#define SYS_lseek 19 -#define SYS_getpid 20 -#define SYS_isatty 21 -#define SYS_fstat 22 -#define SYS_time 23 - -#define SYS_ARG 24 -#define SYS_stat 38 - -#define SYS_pipe 42 -#define SYS_execve 59 - -#define SYS_utime 201 /* not really a system call */ -#define SYS_wait 202 /* nor is this */ - -int __trap34(int, int, void*, int ); diff --git a/bsps/sh/shsim/include/tm27.h b/bsps/sh/shsim/include/tm27.h deleted file mode 100644 index 0dfa7bf628..0000000000 --- a/bsps/sh/shsim/include/tm27.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/bsps/sh/shsim/start/cpu_asm.c b/bsps/sh/shsim/start/cpu_asm.c deleted file mode 100644 index e92b8dd87b..0000000000 --- a/bsps/sh/shsim/start/cpu_asm.c +++ /dev/null @@ -1,93 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * Support for SuperH Simulator in GDB - */ - -/* - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -unsigned long *_old_stack_ptr; - -register unsigned long *stack_ptr __asm__ ("r15"); - -void __ISR_Handler(uint32_t vector); - -/* - * This routine provides the RTEMS interrupt management. - */ -void __ISR_Handler( uint32_t vector) -{ - ISR_Level level; - - _ISR_Local_disable( level ); - - _Thread_Dispatch_disable(); - - if ( _ISR_Nest_level == 0 ) - { - /* Install irq stack */ - _old_stack_ptr = stack_ptr; - stack_ptr = _CPU_Interrupt_stack_high; - } - - _ISR_Nest_level++; - - _ISR_Local_enable( level ); - - /* call isp */ - if ( _ISR_Vector_table[ vector]) - (*_ISR_Vector_table[ vector ])( vector ); - - _ISR_Local_disable( level ); - - _Thread_Dispatch_unnest( _Per_CPU_Get() ); - - _ISR_Nest_level--; - - if ( _ISR_Nest_level == 0 ) - /* restore old stack pointer */ - stack_ptr = _old_stack_ptr; - - _ISR_Local_enable( level ); - - if ( _ISR_Nest_level ) - return; - - if ( !_Thread_Dispatch_is_enabled() ) { - return; - } - - if ( _Thread_Dispatch_necessary ) { - _Thread_Dispatch(); - } -} diff --git a/bsps/sh/shsim/start/ispshgdb.c b/bsps/sh/shsim/start/ispshgdb.c deleted file mode 100644 index f69ea10955..0000000000 --- a/bsps/sh/shsim/start/ispshgdb.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * This file contains the isp frames for the user interrupts. - * From these procedures __ISR_Handler is called with the vector number - * as argument. - * - * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in - * some releases of gcc doesn't properly handle #pragma interrupt, if a - * file contains both isrs and normal functions. - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modified to reflect dummy isp entries for GDB SH simulator by Joel. - */ - -#include - -/* - * This is a exception vector table - * - * It has the same structure as the actual vector table (vectab) - */ - -void _dummy_isp(uint32_t); - -CPU_ISR_raw_handler _Hardware_isr_Table[256]={ -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* PWRon Reset, Maual Reset,...*/ -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -/* trapa 0 -31 */ -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, -_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* irq 152-155*/ -_dummy_isp -}; - -#define Str(a)#a - -/* - * Some versions of gcc and all version of egcs at least until egcs-1.1b - * are not able to handle #pragma interrupt correctly if more than 1 isr is - * contained in a file and when optimizing. - * We try to work around this problem by using the macro below. - */ -#define isp( name, number, func)\ -__asm__ (".global _"Str(name)"\n\t"\ - "_"Str(name)": \n\t"\ - " mov.l r0,@-r15 \n\t"\ - " mov.l r1,@-r15 \n\t"\ - " mov.l r2,@-r15 \n\t"\ - " mov.l r3,@-r15 \n\t"\ - " mov.l r4,@-r15 \n\t"\ - " mov.l r5,@-r15 \n\t"\ - " mov.l r6,@-r15 \n\t"\ - " mov.l r7,@-r15 \n\t"\ - " mov.l r14,@-r15 \n\t"\ - " sts.l pr,@-r15 \n\t"\ - " sts.l mach,@-r15 \n\t"\ - " sts.l macl,@-r15 \n\t"\ - " mov r15,r14 \n\t"\ - " mov.l "Str(name)"_v, r2 \n\t"\ - " mov.l "Str(name)"_k, r1\n\t"\ - " jsr @r1 \n\t"\ - " mov r2,r4 \n\t"\ - " mov r14,r15 \n\t"\ - " lds.l @r15+,macl \n\t"\ - " lds.l @r15+,mach \n\t"\ - " lds.l @r15+,pr \n\t"\ - " mov.l @r15+,r14 \n\t"\ - " mov.l @r15+,r7 \n\t"\ - " mov.l @r15+,r6 \n\t"\ - " mov.l @r15+,r5 \n\t"\ - " mov.l @r15+,r4 \n\t"\ - " mov.l @r15+,r3 \n\t"\ - " mov.l @r15+,r2 \n\t"\ - " mov.l @r15+,r1 \n\t"\ - " mov.l @r15+,r0 \n\t"\ - " rte \n\t"\ - " nop \n\t"\ - " .align 2 \n\t"\ - #name"_k: \n\t"\ - ".long "Str(func)"\n\t"\ - #name"_v: \n\t"\ - ".long "Str(number)); - -/************************************************ - * Dummy interrupt service procedure for - * interrupts being not allowed --> Trap 34 - ************************************************/ -__asm__ (" .section .text\n\ -.global __dummy_isp\n\ -__dummy_isp:\n\ - mov.l r14,@-r15\n\ - mov r15, r14\n\ - trapa #34\n\ - mov.l @r15+,r14\n\ - rte\n\ - nop"); - diff --git a/bsps/sh/shsim/start/linkcmds b/bsps/sh/shsim/start/linkcmds deleted file mode 100644 index 722ddd8ee9..0000000000 --- a/bsps/sh/shsim/start/linkcmds +++ /dev/null @@ -1,253 +0,0 @@ -/* - * Memory layout for an SH 7032 with main memory in area 0 - * - * NOTES: - * + All RAM/ROM areas are mapped onto area 0, because gdb's simulator - * is not able to simulate memory areas but area 0. Area 5 (on-chip - * peripherials) can not be mapped onto area 0 and will cause SIGILL - * exceptions. - * + Assumed to be compatible with other SH-cpu family members (eg. SH7045) - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) - * - * COPYRIGHT (c) 2001, Ralf Corsepius, Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - */ - -OUTPUT_ARCH(sh) -ENTRY(_start) -STARTUP(start.o) - -_RamBase = DEFINED(_RamBase) ? _RamBase : 0x00000000; -_RamSize = DEFINED(_RamSize) ? _RamSize : 16M; -_RamEnd = _RamBase + _RamSize; -_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0; - -MEMORY -{ -/* Real memory layout submitted - rom : o = 0x00000000, l = 128k - ram : o = 0x00040000, l = 256k -*/ - -/* Memory layout which links all tests */ - rom : o = 0x01000000, l = 512k - ram : o = 0x00040000, l = 512k - - onchip_peri : o = 0x05000000, l = 512 -} - -SECTIONS -{ - /* boot vector table */ - .monvects (NOLOAD) : - { - _monvects = . ; - } > rom - - /* monitor play area */ - .monram 0x00040000 (NOLOAD) : - { - _ramstart = .; - } > ram - - /* monitor vector table */ - .vects 0x00042000 (NOLOAD) : { - _vectab = . ; - *(.vects); - } - - /* Read-only sections, merged into text segment: */ - - . = 0x00044000 ; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .gnu.version : { *(.gnu.version) } - .gnu.version_d : { *(.gnu.version_d) } - .gnu.version_r : { *(.gnu.version_r) } - .rela.dyn : - { - *(.rela.init) - *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) - *(.rela.fini) - *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) - *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) - *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) - *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) - *(.rela.ctors) - *(.rela.dtors) - *(.rela.got) - *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) - *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) - *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) - *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) - *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) - } >ram - .rel.text : - { *(.rel.text) *(.rel.gnu.linkonce.t*) } - .rel.data : - { *(.rel.data) *(.rel.gnu.linkonce.d*) } - .rel.rodata : - { *(.rel.rodata) *(.rel.gnu.linkonce.r*) } - .rel.got : { *(.rel.got) } - .rel.ctors : { *(.rel.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rel.init : { *(.rel.init) } - .rel.fini : { *(.rel.fini) } - .rel.bss : { *(.rel.bss) } - .rel.plt : { *(.rel.plt) } - .plt : { *(.plt) } - .text . : - { - _start = .; - *(.text*) - *(.stub) - - /* - * Special FreeBSD sysctl sections. - */ - . = ALIGN (16); - ___start_set_sysctl_set = .; - *(set_sysc*); /* set_sysctl_* but name is truncated by SH-coff */ - ___stop_set_sysctl_set = ABSOLUTE(.); - *(set_doma*); /* set_domain_* but name is truncated by SH-coff */ - *(set_pseu*); /* set_pseudo_* but name is truncated by SH-coff */ - - /* .gnu.warning sections are handled specially by elf32.em. */ - *(.gnu.warning) - *(.gnu.linkonce.t*) - } > ram - .init : - { - KEEP (*(.init)) - } >ram - .fini : - { - KEEP (*(.fini)) - } >ram - _etext = .; - PROVIDE (etext = .); - .rodata . : { *(.rodata*) .rodata.* *(.gnu.linkonce.r*) } > ram - .rodata1 . : { *(.rodata1) } > ram - .tdata : { - __TLS_Data_begin = .; - *(.tdata .tdata.* .gnu.linkonce.td.*) - __TLS_Data_end = .; - } > ram - .tbss : { - __TLS_BSS_begin = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) - __TLS_BSS_end = .; - } > ram - .init . : { KEEP(*(.init)) } > ram =0 - .fini . : { KEEP(*(.fini)) } > ram =0 - .ctors . : { KEEP(*(.ctors)) } > ram =0 - .dtors . : { KEEP(*(.dtors)) } > ram =0 - __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin; - __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin; - __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin; - __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin; - __TLS_Size = __TLS_BSS_end - __TLS_Data_begin; - __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); - /* Adjust the address for the data segment. We want to adjust up to - the same address within the page on the next page up. */ - . = ALIGN(128) + (. & (128 - 1)); - .data . : - { - *(.data*) - *(.gcc_exc*) - ___EH_FRAME_BEGIN__ = .; - *(.eh_fram*) - ___EH_FRAME_END__ = .; - LONG(0); - *(.gcc_except_table*) - *(.gnu.linkonce.d*) - CONSTRUCTORS - } > ram - .data1 . : { *(.data1) } - .rtemsroset : { - /* for pre rtems-libbsd FreeBSD code */ - __start_set_sysctl_set = .; - *(set_sysctl_*); - __stop_set_sysctl_set = .; - *(set_domain_*); - *(set_pseudo_*); - - KEEP (*(SORT(.rtemsroset.*))) - } >ram - .rtemsrwset : { - KEEP (*(SORT(.rtemsrwset.*))) - } >ram - - .got . : { *(.got.plt) *(.got) } - .dynamic . : { *(.dynamic) } - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - .sdata . : { *(.sdata) } - _edata = .; - PROVIDE (edata = .); - __bss_start = .; - .sbss . : { *(.sbss*) *(.scommon) } - .bss . : - { - *(.dynbss) - *(.bss .bss* .gnu.linkonce.b*) - *(COMMON) - } > ram - _end = . ; - PROVIDE (end = .); - - .noinit (NOLOAD) : { - *(SORT_BY_NAME (SORT_BY_ALIGNMENT (.noinit*))) - } > ram - - .rtemsstack (NOLOAD) : { - *(SORT(.rtemsstack.*)) - } > ram - - _WorkAreaBase = . ; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* These must appear regardless of . */ - - /* Addition to let linker know about custom section for GDB pretty-printing support. */ - .debug_gdb_scripts 0 : { *(.debug_gdb_scripts) } -} diff --git a/bsps/sh/shsim/start/start.S b/bsps/sh/shsim/start/start.S deleted file mode 100644 index b5294e3861..0000000000 --- a/bsps/sh/shsim/start/start.S +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include -#include - - BEGIN_CODE - PUBLIC(start) -SYM (start): - ! install the stack pointer - mov.l stack_k,r15 - - ! zero out bss - mov.l edata_k,r0 - mov.l end_k,r1 - mov #0,r2 -0: - mov.l r2,@r0 - add #4,r0 - cmp/ge r0,r1 - bt 0b - - ! copy the vector table from rom to ram - mov.l vects_k,r0 ! vectab - mov #0,r1 ! address of boot vector table - mov #0,r2 ! number of bytes copied - mov.w vects_size,r3 ! size of entries in vectab -1: - mov.l @r1+,r4 - mov.l r4,@r0 - add #4,r0 - add #1,r2 - cmp/hi r3,r2 - bf 1b - - mov.l vects_k,r0 ! update vbr to point to vectab - ldc r0,vbr - - ! call the mainline - mov #0,r4 ! command line - mov.l main_k,r0 - jsr @r0 - - - ! call exit - mov r0,r4 - mov.l exit_k,r0 - jsr @r0 - or r0,r0 - - END_CODE - - .align 2 -stack_k: - .long SYM(_ISR_Stack_area_end) -edata_k: - .long SYM(edata) -end_k: - .long SYM(end) -main_k: - .long SYM(boot_card) -exit_k: - .long SYM(_sys_exit) - -vects_k: - .long SYM(vectab) -vects_size: - .word 255 diff --git a/bsps/sh/shsim/start/sysexit.c b/bsps/sh/shsim/start/sysexit.c deleted file mode 100644 index fcb888d9af..0000000000 --- a/bsps/sh/shsim/start/sysexit.c +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * This file contains the simulator specific exit trap. - */ - -/* - * COPYRIGHT (c) 1989-2014. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include - -int errno; /* assumed to exist by exit_k() */ - -int _sys_exit (int n) -{ - return __trap34 (SYS_exit, n, 0, 0); -} diff --git a/cpukit/score/cpu/sh/context.c b/cpukit/score/cpu/sh/context.c deleted file mode 100644 index 1505f0217e..0000000000 --- a/cpukit/score/cpu/sh/context.c +++ /dev/null @@ -1,233 +0,0 @@ -/** - * @file - * - * @brief SuperH CPU Context - */ - -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include -#include -#include -#include - -/* - * _CPU_Context_save_fp_context - * - * This routine is responsible for saving the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - */ - -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -) -{ -#if SH_HAS_FPU - -asm volatile("\n\ - mov.l @%0,r4 \n\ - add %1,r4\n\ - sts.l fpscr,@-r4\n\ - sts.l fpul,@-r4\n\ - lds %2,fpscr\n\ - fmov dr14,@-r4\n\ - fmov dr12,@-r4\n\ - fmov dr10,@-r4\n\ - fmov dr8,@-r4\n\ - fmov dr6,@-r4\n\ - fmov dr4,@-r4\n\ - fmov dr2,@-r4\n\ - fmov dr0,@-r4\n\ - " -#ifdef SH4_USE_X_REGISTERS - "\ - lds %3,fpscr\n\ - fmov xd14,@-r4\n\ - fmov xd12,@-r4\n\ - fmov xd10,@-r4\n\ - fmov xd8,@-r4\n\ - fmov xd6,@-r4\n\ - fmov xd4,@-r4\n\ - fmov xd2,@-r4\n\ - fmov xd0,@-r4\n\ - " -#endif - "lds %4,fpscr\n\ - " - : - : "r"(fp_context_ptr), "r"(sizeof(Context_Control_fp)), - "r"(SH4_FPSCR_SZ), "r"(SH4_FPSCR_PR | SH4_FPSCR_SZ), "r"(SH4_FPSCR_PR) - : "r4", "r0"); - -#endif - -} - -/* - * _CPU_Context_restore_fp_context - * - * This routine is responsible for restoring the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - */ - -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -) -{ - -#if SH_HAS_FPU - -asm volatile("\n\ - mov.l @%0,r4 \n\ - " -#ifdef SH4_USE_X_REGISTERS - "\n\ - lds %1,fpscr\n\ - fmov @r4+,xd0\n\ - fmov @r4+,xd2\n\ - fmov @r4+,xd4\n\ - fmov @r4+,xd6\n\ - fmov @r4+,xd8\n\ - fmov @r4+,xd10\n\ - fmov @r4+,xd12\n\ - fmov @r4+,xd14\n\ - " -#endif - "\n\ - lds %2,fpscr\n\ - fmov @r4+,dr0\n\ - fmov @r4+,dr2\n\ - fmov @r4+,dr4\n\ - fmov @r4+,dr6\n\ - fmov @r4+,dr8\n\ - fmov @r4+,dr10\n\ - fmov @r4+,dr12\n\ - fmov @r4+,dr14\n\ - lds.l @r4+,fpul\n\ - lds.l @r4+,fpscr\n\ - " : - : "r"(fp_context_ptr), "r"(SH4_FPSCR_PR | SH4_FPSCR_SZ), "r"(SH4_FPSCR_SZ) - : "r4", "r0"); -#endif -} - -/* _CPU_Context_switch - * - * This routine performs a normal non-FP context switch. - */ - -/* within __CPU_Context_switch: - * _CPU_Context_switch - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: It should be safe not to store r4, r5 - * - * NOTE: It is doubtful if r0 is really needed to be stored - * - * NOTE: gbr is added, but should not be necessary, as it is - * only used globally in this port. - */ - -/* - * FIXME: This is an ugly hack, but we wanted to avoid recalculating - * the offset each time Context_Control is changed - */ -void _CPU_Context_switch( - Context_Control *run, /* r4 */ - Context_Control *heir /* r5 */ -) -{ - -asm volatile("\n\ - .global __CPU_Context_switch\n\ -__CPU_Context_switch:\n\ -\n\ - add %0,r4\n\ - \n\ - stc.l sr,@-r4\n\ - stc.l gbr,@-r4\n\ - mov.l r0,@-r4\n\ - mov.l r1,@-r4\n\ - mov.l r2,@-r4\n\ - mov.l r3,@-r4\n\ -\n\ - mov.l r6,@-r4\n\ - mov.l r7,@-r4\n\ - mov.l r8,@-r4\n\ - mov.l r9,@-r4\n\ - mov.l r10,@-r4\n\ - mov.l r11,@-r4\n\ - mov.l r12,@-r4\n\ - mov.l r13,@-r4\n\ - mov.l r14,@-r4\n\ - sts.l pr,@-r4\n\ - sts.l mach,@-r4\n\ - sts.l macl,@-r4\n\ - mov.l r15,@-r4\n\ -\n\ - mov r5, r4" - :: "i" (sizeof(Context_Control)) - ); - - __asm__ volatile("\n\ - .global __CPU_Context_restore\n\ -__CPU_Context_restore:\n\ - mov.l @r4+,r15\n\ - lds.l @r4+,macl\n\ - lds.l @r4+,mach\n\ - lds.l @r4+,pr\n\ - mov.l @r4+,r14\n\ - mov.l @r4+,r13\n\ - mov.l @r4+,r12\n\ - mov.l @r4+,r11\n\ - mov.l @r4+,r10\n\ - mov.l @r4+,r9\n\ - mov.l @r4+,r8\n\ - mov.l @r4+,r7\n\ - mov.l @r4+,r6\n\ -\n\ - mov.l @r4+,r3\n\ - mov.l @r4+,r2\n\ - mov.l @r4+,r1\n\ - mov.l @r4+,r0\n\ - ldc.l @r4+,gbr\n\ - ldc.l @r4+,sr\n\ -\n\ - rts\n\ - nop" ); -} diff --git a/cpukit/score/cpu/sh/cpu.c b/cpukit/score/cpu/sh/cpu.c deleted file mode 100644 index 0cfb3ae2b1..0000000000 --- a/cpukit/score/cpu/sh/cpu.c +++ /dev/null @@ -1,177 +0,0 @@ -/** - * @file - * - * @brief SuperH CPU Support - * - * This file contains information pertaining to the Hitachi SH - * processor. - */ - -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include -#include -#include -#include - -/* referenced in start.S */ -CPU_ISR_raw_handler vectab[256] ; - -#if SH_HAS_FPU -Context_Control_fp _CPU_Null_fp_context; -#endif - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: NONE - */ - -void _CPU_Initialize(void) -{ - register uint32_t level = 0; - - /* - * If there is not an easy way to initialize the FP context - * during Context_Initialize, then it is usually easier to - * save an "uninitialized" FP context here and copy it to - * the task's during Context_Initialize. - */ - - /* FP context initialization support goes here */ -#if SH_HAS_FPU - /* FIXME: When not to use SH4_FPSCR_PR ? */ -#ifdef __SH4__ - _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM | SH4_FPSCR_PR; -#endif -#ifdef __SH3E__ - /* FIXME: Wild guess :) */ - _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM; -#endif -#endif - - /* enable interrupts */ - _CPU_ISR_Set_level( level ) ; -} - -/* - * _CPU_ISR_Get_level - */ - -uint32_t _CPU_ISR_Get_level( void ) -{ - /* - * This routine returns the current interrupt level. - */ - - register uint32_t _mask ; - - sh_get_interrupt_level( _mask ); - - return ( _mask); -} - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - CPU_ISR_raw_handler new_handler, - CPU_ISR_raw_handler *old_handler -) - -{ - /* - * This is where we install the interrupt handler into the "raw" interrupt - * table used by the CPU to dispatch interrupt handlers. - */ - volatile CPU_ISR_raw_handler *vbr ; - -#if SH_PARANOID_ISR - uint32_t level ; - - sh_disable_interrupts( level ); -#endif - - /* get vbr */ - __asm__ ( "stc vbr,%0" : "=r" (vbr) ); - - *old_handler = vbr[vector] ; - vbr[vector] = new_handler ; - -#if SH_PARANOID_ISR - sh_enable_interrupts( level ); -#endif -} - -void _CPU_ISR_install_vector( - uint32_t vector, - CPU_ISR_handler new_handler, - CPU_ISR_handler *old_handler -) -{ -#if defined(__sh1__) || defined(__sh2__) - CPU_ISR_raw_handler ignored ; -#endif - *old_handler = _ISR_Vector_table[ vector ]; - - /* - * If the interrupt vector table is a table of pointer to isr entry - * points, then we need to install the appropriate RTEMS interrupt - * handler for this vector number. - */ -#if defined(__sh1__) || defined(__sh2__) - _CPU_ISR_install_raw_handler(vector, _Hardware_isr_Table[vector], &ignored ); -#endif - - /* - * We put the actual user ISR address in '_ISR_Vector_table'. - * This will be used by __ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler; -} - -void _CPU_Context_Initialize( - Context_Control *_the_context, - void *_stack_base, - uint32_t _size, - uint32_t _isr, - void (*_entry_point)(void), - int _is_fp, - void *_tls_base) -{ - _the_context->r15 = (uint32_t *) ((uint32_t) (_stack_base) + (_size) ); -#if defined(__sh1__) || defined(__sh2__) || defined(__SH2E__) - _the_context->sr = (_isr << 4) & 0x00f0 ; -#else - _the_context->sr = SH4_SR_MD | ((_isr << 4) & 0x00f0); -#endif - _the_context->pr = (uint32_t *) _entry_point ; - - -#if 0 && SH_HAS_FPU - /* Disable FPU if it is non-fp task */ - if(!_is_fp) - _the_context->sr |= SH4_SR_FD; -#endif -} diff --git a/cpukit/score/cpu/sh/include/rtems/asm.h b/cpukit/score/cpu/sh/include/rtems/asm.h deleted file mode 100644 index a2b42647e5..0000000000 --- a/cpukit/score/cpu/sh/include/rtems/asm.h +++ /dev/null @@ -1,147 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * @note The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif - -#include -#include - -/** - * @defgroup RTEMSScoreCPUshASM SuperH (sh) Assembler Support - * - * @ingroup RTEMSScoreCPUsh - * - * @brief SuperH (sh) Assembler Support - * - * @{ - */ - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ -#define r0 REG (r0) -#define r1 REG (r1) -#define r2 REG (r2) -#define r3 REG (r3) -#define r4 REG (r4) -#define r5 REG (r5) -#define r6 REG (r6) -#define r7 REG (r7) -#define r8 REG (r8) -#define r9 REG (r9) -#define r10 REG (r10) -#define r11 REG (r11) -#define r12 REG (r12) -#define r13 REG (r13) -#define r14 REG (r14) -#define r15 REG (r15) -#define vbr REG (vbr) -#define gbr REG (gbr) -#define pr REG (pr) -#define mach REG (mach) -#define macl REG (macl) -#define sr REG (sr) -#define pc REG (pc) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .global SYM (sym) -#define EXTERN(sym) .global SYM (sym) - -#endif diff --git a/cpukit/score/cpu/sh/include/rtems/score/cpu.h b/cpukit/score/cpu/sh/include/rtems/score/cpu.h deleted file mode 100644 index 8c73ae13ba..0000000000 --- a/cpukit/score/cpu/sh/include/rtems/score/cpu.h +++ /dev/null @@ -1,590 +0,0 @@ -/** - * @file - */ - -/* - * This include file contains information pertaining to the Hitachi SH - * processor. - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998-2006. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/* conditional compilation parameters */ - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * SH Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER FALSE - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * We currently support sh1 only, which has no FPU, other SHes have an FPU - * - * The macro name "SH_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#if SH_HAS_FPU -#define CPU_HARDWARE_FP TRUE -#define CPU_SOFTWARE_FP FALSE -#else -#define CPU_SOFTWARE_FP FALSE -#define CPU_HARDWARE_FP FALSE -#endif - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - */ - -#if SH_HAS_FPU -#define CPU_ALL_TASKS_ARE_FP TRUE -#else -#define CPU_ALL_TASKS_ARE_FP FALSE -#endif - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#if SH_HAS_FPU -#define CPU_IDLE_TASK_IS_FP TRUE -#else -#define CPU_IDLE_TASK_IS_FP FALSE -#endif - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - */ - -#if SH_HAS_FPU -#define CPU_USE_DEFERRED_FP_SWITCH FALSE -#else -#define CPU_USE_DEFERRED_FP_SWITCH TRUE -#endif - -#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* FIXME: Is this the right value? */ -#define CPU_CACHE_LINE_BYTES 16 - -#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - */ - -#define CPU_MODES_INTERRUPT_MASK 0x0000000f - -#define CPU_MAXIMUM_PROCESSORS 32 - -/* - * Processor defined structures required for cpukit/score. - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -typedef struct { - uint32_t *r15; /* stack pointer */ - - uint32_t macl; - uint32_t mach; - uint32_t *pr; - - uint32_t *r14; /* frame pointer/call saved */ - - uint32_t r13; /* call saved */ - uint32_t r12; /* call saved */ - uint32_t r11; /* call saved */ - uint32_t r10; /* call saved */ - uint32_t r9; /* call saved */ - uint32_t r8; /* call saved */ - - uint32_t *r7; /* arg in */ - uint32_t *r6; /* arg in */ - -#if 0 - uint32_t *r5; /* arg in */ - uint32_t *r4; /* arg in */ -#endif - - uint32_t *r3; /* scratch */ - uint32_t *r2; /* scratch */ - uint32_t *r1; /* scratch */ - - uint32_t *r0; /* arg return */ - - uint32_t gbr; - uint32_t sr; - -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->r15 - -typedef struct { -#if SH_HAS_FPU -#ifdef SH4_USE_X_REGISTERS - union { - float f[16]; - double d[8]; - } x; -#endif - union { - float f[16]; - double d[8]; - } r; - float fpul; /* fp communication register */ - uint32_t fpscr; /* fp control register */ -#endif /* SH_HAS_FPU */ -} Context_Control_fp; - -typedef struct { -} CPU_Interrupt_frame; - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -#if SH_HAS_FPU -extern Context_Control_fp _CPU_Null_fp_context; -#endif - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - */ - -/* XXX: if needed, put more variables here */ -void CPU_delay( uint32_t microseconds ); - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * We have been able to run the sptests with this value, but have not - * been able to run the tmtest suite. - */ - -#define CPU_STACK_MINIMUM_SIZE 4096 - -#define CPU_SIZEOF_POINTER 4 - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ -#if defined(__SH4__) -/* FIXME: sh3 and SH3E? */ -#define CPU_ALIGNMENT 8 -#else -#define CPU_ALIGNMENT 4 -#endif - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT - -#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES - -/* - * ISR handler macros - */ - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - */ - -#define _CPU_ISR_Disable( _level) \ - sh_disable_interrupts( _level ) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _level) \ - sh_enable_interrupts( _level) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _level) \ - sh_flash_interrupts( _level) - -static inline bool _CPU_ISR_Is_enabled( uint32_t level ) -{ - sh_get_interrupt_level( level ); - return level == 0; -} - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - */ - -#define _CPU_ISR_Set_level( _newlevel) \ - sh_set_interrupt_level(_newlevel) - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - */ - -/* - * FIXME: defined as a function for debugging - should be a macro - */ -void _CPU_Context_Initialize( - Context_Control *_the_context, - void *_stack_base, - uint32_t _size, - uint32_t _isr, - void (*_entry_point)(void), - int _is_fp, - void *_tls_area ); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * SH1, SH2, SH3 have no FPU, but the SH3e and SH4 have. - */ - -#if SH_HAS_FPU -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *(*(_destination)) = _CPU_Null_fp_context;\ - } while(0) -#else -#define _CPU_Context_Initialize_fp( _destination ) \ - { } -#endif - -/* end of Context handler macros */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE - -/* functions */ - -/* - * @brief CPU Initialize - * - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ -void _CPU_Initialize(void); - -typedef void ( *CPU_ISR_raw_handler )( void ); - -extern CPU_ISR_raw_handler _Hardware_isr_Table[]; - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - CPU_ISR_raw_handler new_handler, - CPU_ISR_raw_handler *old_handler -); - -typedef void ( *CPU_ISR_handler )( uint32_t ); - -void _CPU_ISR_install_vector( - uint32_t vector, - CPU_ISR_handler new_handler, - CPU_ISR_handler *old_handler -); - -RTEMS_NO_RETURN void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - */ - -RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context ); - -/* - * @brief This routine saves the floating point context passed to it. - * - * _CPU_Context_save_fp - * - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * @brief This routine restores the floating point context passed to it. - * - * _CPU_Context_restore_fp - * - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -typedef uint32_t CPU_Counter_ticks; - -uint32_t _CPU_Counter_frequency( void ); - -CPU_Counter_ticks _CPU_Counter_read( void ); - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -/** Types related to SH specific ISRs */ -typedef void sh_isr; -typedef void ( *sh_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h deleted file mode 100644 index 5a712c369d..0000000000 --- a/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h +++ /dev/null @@ -1,87 +0,0 @@ -/** - * @file - * - * @brief CPU Port Implementation API - */ - -/* - * Copyright (c) 2013 embedded brains GmbH & Co. KG - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPUIMPL_H -#define _RTEMS_SCORE_CPUIMPL_H - -#include - -/** - * @defgroup RTEMSScoreCPUsh SuperH (sh) - * - * @ingroup RTEMSScoreCPU - * - * @brief SuperH (sh) Architecture Support - * - * @{ - */ - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10 - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - (void) pattern; - - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - (void) pattern; - - while (1) { - /* TODO */ - } -} - -static inline void _CPU_Instruction_illegal( void ) -{ - __asm__ volatile ( ".word 0" ); -} - -static inline void _CPU_Instruction_no_operation( void ) -{ - __asm__ volatile ( "nop" ); -} - -static inline void _CPU_Use_thread_local_storage( - const Context_Control *context -) -{ - (void) context; -} - -static inline void *_CPU_Get_TLS_thread_pointer( - const Context_Control *context -) -{ - (void) context; - return NULL; -} - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/sh/include/rtems/score/sh.h b/cpukit/score/cpu/sh/include/rtems/score/sh.h deleted file mode 100644 index 6ac5ef1382..0000000000 --- a/cpukit/score/cpu/sh/include/rtems/score/sh.h +++ /dev/null @@ -1,277 +0,0 @@ -/** - * @file - * - * @brief Hitachi SH CPU Department Source - * - * This include file contains information pertaining to the Hitachi SH - * processor. - */ - -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE - * - * - * COPYRIGHT (c) 1998-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_SH_H -#define _RTEMS_SCORE_SH_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "SH" family. - * - * It does this by setting variables to indicate which implementation - * dependent features are present in a particular member of the family. - */ - -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#if defined(__SH2E__) || defined(__SH3E__) - -/* FIXME: SH-DSP context not currently supported */ -#define SH_HAS_FPU 0 - -#elif defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) - -/* - * Define this if you want to use XD-registers. - * Then this registers will be saved/restored on context switch. - * ! They will not be saved/restored on interrupts! - */ -#define SH4_USE_X_REGISTERS 0 - -#if defined(__LITTLE_ENDIAN__) -#define SH_HAS_FPU 1 -#else -/* FIXME: Context_Control_fp does not support big endian */ -#warning FPU not supported -#define SH_HAS_FPU 0 -#endif - -#elif defined(__sh1__) || defined(__sh2__) || defined(__sh3__) -#define SH_HAS_FPU 0 -#else -#warning Cannot detect FPU support, assuming no FPU -#define SH_HAS_FPU 0 -#endif - -/* this should not be here */ -#ifndef CPU_MODEL_NAME -#define CPU_MODEL_NAME "SH-Multilib" -#endif - -/* - * If the following macro is set to 0 there will be no software irq stack - */ - -#ifndef SH_HAS_SEPARATE_STACKS -#define SH_HAS_SEPARATE_STACKS 1 -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "Hitachi SH" - -#ifndef ASM - -#if defined(__sh1__) || defined(__sh2__) - -/* - * Mask for disabling interrupts - */ -#define SH_IRQDIS_VALUE 0xf0 - -#define sh_disable_interrupts( _level ) \ - __asm__ volatile ( \ - "stc sr,%0\n\t" \ - "ldc %1,sr\n\t"\ - : "=&r" (_level ) \ - : "r" (SH_IRQDIS_VALUE) ); - -#define sh_enable_interrupts( _level ) \ - __asm__ volatile( "ldc %0,sr\n\t" \ - "nop\n\t" \ - :: "r" (_level) ); - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define sh_flash_interrupts( _level ) \ - __asm__ volatile( \ - "ldc %1,sr\n\t" \ - "nop\n\t" \ - "ldc %0,sr\n\t" \ - "nop\n\t" \ - : : "r" (SH_IRQDIS_VALUE), "r" (_level) ); - -#else - -#define SH_IRQDIS_MASK 0xf0 - -#define sh_disable_interrupts( _level ) \ - __asm__ volatile ( \ - "stc sr,%0\n\t" \ - "mov %0,r5\n\t" \ - "or %1,r5\n\t" \ - "ldc r5,sr\n\t"\ - : "=&r" (_level ) \ - : "r" (SH_IRQDIS_MASK) \ - : "r5" ); - -#define sh_enable_interrupts( _level ) \ - __asm__ volatile( "ldc %0,sr\n\t" \ - "nop\n\t" \ - :: "r" (_level) ); - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define sh_flash_interrupts( _level ) \ - __asm__ volatile( \ - "stc sr,r5\n\t" \ - "ldc %1,sr\n\t" \ - "nop\n\t" \ - "or %0,r5\n\t" \ - "ldc r5,sr\n\t" \ - "nop\n\t" \ - : : "r" (SH_IRQDIS_MASK), "r" (_level) : "r5"); - -#endif - -#define sh_get_interrupt_level( _level ) \ -{ \ - uint32_t _tmpsr ; \ - \ - __asm__ volatile( "stc sr, %0" : "=r" (_tmpsr) ); \ - _level = (_tmpsr & 0xf0) >> 4 ; \ -} - -#define sh_set_interrupt_level( _newlevel ) \ -{ \ - uint32_t _tmpsr; \ - \ - __asm__ volatile ( "stc sr, %0" : "=r" (_tmpsr) ); \ - _tmpsr = ( _tmpsr & ~0xf0 ) | ((_newlevel) << 4) ; \ - __asm__ volatile( "ldc %0,sr" :: "r" (_tmpsr) ); \ -} - -/* - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - */ - -static inline uint32_t sh_swap_u32( - uint32_t value -) -{ - uint32_t swapped; - - __asm__ volatile ( - "swap.b %1,%0; " - "swap.w %0,%0; " - "swap.b %0,%0" - : "=r" (swapped) - : "r" (value) ); - - return( swapped ); -} - -static inline uint16_t sh_swap_u16( - uint16_t value -) -{ - uint16_t swapped ; - - __asm__ volatile ( "swap.b %1,%0" : "=r" (swapped) : "r" (value) ); - - return( swapped ); -} - -#define CPU_swap_u32( value ) sh_swap_u32( value ) -#define CPU_swap_u16( value ) sh_swap_u16( value ) - -extern unsigned int sh_set_irq_priority( - unsigned int irq, - unsigned int prio ); - -#endif /* !ASM */ - -/* - * Bits on SH-4 registers. - * See SH-4 Programming manual for more details. - * - * Added by Alexandra Kossovsky - */ - -#if defined(__SH4__) -#define SH4_SR_MD 0x40000000 /* Priveleged mode */ -#define SH4_SR_RB 0x20000000 /* General register bank specifier */ -#define SH4_SR_BL 0x10000000 /* Exeption/interrupt masking bit */ -#define SH4_SR_FD 0x00008000 /* FPU disable bit */ -#define SH4_SR_M 0x00000200 /* For signed division: - divisor (module) is negative */ -#define SH4_SR_Q 0x00000100 /* For signed division: - dividend (and quotient) is negative */ -#define SH4_SR_IMASK 0x000000f0 /* Interrupt mask level */ -#define SH4_SR_IMASK_S 4 -#define SH4_SR_S 0x00000002 /* Saturation for MAC instruction: - if set, data in MACH/L register - is restricted to 48/32 bits - for MAC.W/L instructions */ -#define SH4_SR_T 0x00000001 /* 1 if last condiyion was true */ -#define SH4_SR_RESERV 0x8fff7d0d /* Reserved bits, read/write as 0 */ - -/* FPSCR -- FPU Status/Control Register */ -#define SH4_FPSCR_FR 0x00200000 /* FPU register bank specifier */ -#define SH4_FPSCR_SZ 0x00100000 /* FMOV 64-bit transfer mode */ -#define SH4_FPSCR_PR 0x00080000 /* Double-percision floating-point - operations flag */ - /* SH4_FPSCR_SZ & SH4_FPSCR_PR != 1 */ -#define SH4_FPSCR_DN 0x00040000 /* Treat denormalized number as zero */ -#define SH4_FPSCR_CAUSE 0x0003f000 /* FPU exeption cause field */ -#define SH4_FPSCR_CAUSE_S 12 -#define SH4_FPSCR_ENABLE 0x00000f80 /* FPU exeption enable field */ -#define SH4_FPSCR_ENABLE_s 7 -#define SH4_FPSCR_FLAG 0x0000007d /* FPU exeption flag field */ -#define SH4_FPSCR_FLAG_S 2 -#define SH4_FPSCR_RM 0x00000001 /* Rounding mode: - 1/0 -- round to zero/nearest */ -#define SH4_FPSCR_RESERV 0xffd00000 /* Reserved bits, read/write as 0 */ - -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/sh/include/rtems/score/sh_io.h b/cpukit/score/cpu/sh/include/rtems/score/sh_io.h deleted file mode 100644 index 8d81965f78..0000000000 --- a/cpukit/score/cpu/sh/include/rtems/score/sh_io.h +++ /dev/null @@ -1,51 +0,0 @@ -/** - * @file - * - * @brief Macros to Access Memory Mapped Devices on the SH7000-Architecture - * - * These are some macros to access memory mapped devices - * on the SH7000-architecture. - */ - -/* - * Inspired from the linux kernel's include/asm/io.h - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1996-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_SH_IO_H -#define _RTEMS_SCORE_SH_IO_H - -#define readb(addr) (*(volatile unsigned char *) (addr)) -#define readw(addr) (*(volatile unsigned short *) (addr)) -#define readl(addr) (*(volatile unsigned int *) (addr)) -#define read8(addr) (*(volatile uint8_t *) (addr)) -#define read16(addr) (*(volatile uint16_t *) (addr)) -#define read32(addr) (*(volatile uint32_t *) (addr)) - -#define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b)) -#define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b)) -#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b)) -#define write8(b,addr) ((*(volatile uint8_t *) (addr)) = (b)) -#define write16(b,addr) ((*(volatile uint16_t *) (addr)) = (b)) -#define write32(b,addr) ((*(volatile uint32_t *) (addr)) = (b)) - -#define inb(addr) readb(addr) -#define outb(b,addr) writeb(b,addr) - -#endif diff --git a/cpukit/score/cpu/sh/sh-exception-frame-print.c b/cpukit/score/cpu/sh/sh-exception-frame-print.c deleted file mode 100644 index d6c49f5569..0000000000 --- a/cpukit/score/cpu/sh/sh-exception-frame-print.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2012 embedded brains GmbH & Co. KG - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ) -{ - /* TODO */ -} diff --git a/spec/build/bsps/sh/gensh1/abi.yml b/spec/build/bsps/sh/gensh1/abi.yml deleted file mode 100644 index 518af2f92e..0000000000 --- a/spec/build/bsps/sh/gensh1/abi.yml +++ /dev/null @@ -1,18 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-string: null -- split: null -- env-append: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: - - -m1 -description: | - ABI flags -enabled-by: true -links: [] -name: ABI_FLAGS -type: build diff --git a/spec/build/bsps/sh/gensh1/bspgensh1.yml b/spec/build/bsps/sh/gensh1/bspgensh1.yml deleted file mode 100644 index f22be46924..0000000000 --- a/spec/build/bsps/sh/gensh1/bspgensh1.yml +++ /dev/null @@ -1,69 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -arch: sh -bsp: gensh1 -build-type: bsp -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -family: gensh1 -includes: [] -install: -- destination: ${BSP_INCLUDEDIR} - source: - - bsps/sh/gensh1/include/bsp.h -- destination: ${BSP_INCLUDEDIR}/bsp - source: - - bsps/sh/gensh1/include/bsp/irq.h -- destination: ${BSP_INCLUDEDIR}/rtems/score - source: - - bsps/sh/gensh1/include/rtems/score/iosh7032.h - - bsps/sh/gensh1/include/rtems/score/ispsh7032.h -- destination: ${BSP_INCLUDEDIR}/sh - source: - - bsps/sh/gensh1/include/sh/sci.h - - bsps/sh/gensh1/include/sh/sh7_pfc.h - - bsps/sh/gensh1/include/sh/sh7_sci.h -- destination: ${BSP_LIBDIR} - source: - - bsps/sh/gensh1/start/linkcmds -links: -- role: build-dependency - uid: ../../obj -- role: build-dependency - uid: ../../objirqdflt -- role: build-dependency - uid: ../../objmem -- role: build-dependency - uid: ../../opto2 -- role: build-dependency - uid: abi -- role: build-dependency - uid: optcpuclk -- role: build-dependency - uid: optlowinit -- role: build-dependency - uid: start -- role: build-dependency - uid: tstgensh1 -- role: build-dependency - uid: ../../bspopts -source: -- bsps/sh/gensh1/btimer/btimer.c -- bsps/sh/gensh1/clock/ckinit.c -- bsps/sh/gensh1/clock/delay.c -- bsps/sh/gensh1/console/sci.c -- bsps/sh/gensh1/console/scitab.c -- bsps/sh/gensh1/start/cpu_asm.c -- bsps/sh/gensh1/start/ispsh7032.c -- bsps/sh/shared/console/console.c -- bsps/sh/shared/start/bsphwinit.c -- bsps/sh/shared/start/bspstart.c -- bsps/shared/cache/nocache.c -- bsps/shared/dev/getentropy/getentropy-cpucounter.c -- bsps/shared/dev/serial/printk-dummy.c -- bsps/shared/start/bspreset-loop.c -- bsps/shared/start/gettargethash-default.c -- bsps/shared/start/sbrk.c -type: build diff --git a/spec/build/bsps/sh/gensh1/optcpuclk.yml b/spec/build/bsps/sh/gensh1/optcpuclk.yml deleted file mode 100644 index 85c2469d6c..0000000000 --- a/spec/build/bsps/sh/gensh1/optcpuclk.yml +++ /dev/null @@ -1,17 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-integer: null -- define: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: 20000000 -description: | - cpu clock rate in HZ -enabled-by: true -format: '{}' -links: [] -name: CPU_CLOCK_RATE_HZ -type: build diff --git a/spec/build/bsps/sh/gensh1/optlowinit.yml b/spec/build/bsps/sh/gensh1/optlowinit.yml deleted file mode 100644 index 71f5874577..0000000000 --- a/spec/build/bsps/sh/gensh1/optlowinit.yml +++ /dev/null @@ -1,16 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-boolean: null -- define-condition: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: false -description: | - If defined, selects whether 'early_hw_init()' is called from 'start.S'; 'bsp_hw_init()' is always called from 'bspstart.c' -enabled-by: true -links: [] -name: START_HW_INIT -type: build diff --git a/spec/build/bsps/sh/gensh1/start.yml b/spec/build/bsps/sh/gensh1/start.yml deleted file mode 100644 index 31c9602991..0000000000 --- a/spec/build/bsps/sh/gensh1/start.yml +++ /dev/null @@ -1,14 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -asflags: [] -build-type: start-file -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -includes: [] -install-path: ${BSP_LIBDIR} -links: [] -source: -- bsps/sh/gensh1/start/start.S -target: start.o -type: build diff --git a/spec/build/bsps/sh/gensh1/tstgensh1.yml b/spec/build/bsps/sh/gensh1/tstgensh1.yml deleted file mode 100644 index 660e5ebfa9..0000000000 --- a/spec/build/bsps/sh/gensh1/tstgensh1.yml +++ /dev/null @@ -1,24 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- set-test-state: - reason: null - state: exclude - tests: - - fileio - - fsdosfsname01 - - iostream - - linpack - - rcxx01 - - record02 - - utf8proc01 - - validation-no-clock-0 -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: [] -description: '' -enabled-by: true -links: -- role: build-dependency - uid: ../../tstnoiconv -type: build diff --git a/spec/build/bsps/sh/gensh2/abi.yml b/spec/build/bsps/sh/gensh2/abi.yml deleted file mode 100644 index 9a9c83e4ff..0000000000 --- a/spec/build/bsps/sh/gensh2/abi.yml +++ /dev/null @@ -1,18 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-string: null -- split: null -- env-append: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: - - -m2 -description: | - ABI flags -enabled-by: true -links: [] -name: ABI_FLAGS -type: build diff --git a/spec/build/bsps/sh/gensh2/bspgensh2.yml b/spec/build/bsps/sh/gensh2/bspgensh2.yml deleted file mode 100644 index 54b96fc1f6..0000000000 --- a/spec/build/bsps/sh/gensh2/bspgensh2.yml +++ /dev/null @@ -1,77 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -arch: sh -bsp: gensh2 -build-type: bsp -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -family: gensh2 -includes: [] -install: -- destination: ${BSP_INCLUDEDIR} - source: - - bsps/sh/gensh2/include/bsp.h -- destination: ${BSP_INCLUDEDIR}/bsp - source: - - bsps/sh/gensh2/include/bsp/irq.h -- destination: ${BSP_INCLUDEDIR}/rtems/score - source: - - bsps/sh/gensh2/include/rtems/score/iosh7045.h - - bsps/sh/gensh2/include/rtems/score/ispsh7045.h -- destination: ${BSP_INCLUDEDIR}/sh - source: - - bsps/sh/gensh2/include/sh/io_types.h - - bsps/sh/gensh2/include/sh/sci.h - - bsps/sh/gensh2/include/sh/sci_termios.h - - bsps/sh/gensh2/include/sh/sh7_pfc.h - - bsps/sh/gensh2/include/sh/sh7_sci.h -- destination: ${BSP_LIBDIR} - source: - - bsps/sh/gensh2/start/linkcmds - - bsps/sh/gensh2/start/linkcmds.ram - - bsps/sh/gensh2/start/linkcmds.rom -links: -- role: build-dependency - uid: ../../obj -- role: build-dependency - uid: ../../objirqdflt -- role: build-dependency - uid: ../../objmem -- role: build-dependency - uid: ../../opto2 -- role: build-dependency - uid: abi -- role: build-dependency - uid: optcpuclk -- role: build-dependency - uid: optevb -- role: build-dependency - uid: optlowinit -- role: build-dependency - uid: start -- role: build-dependency - uid: tstgensh2 -- role: build-dependency - uid: ../../bspopts -source: -- bsps/sh/gensh2/btimer/btimer.c -- bsps/sh/gensh2/clock/ckinit.c -- bsps/sh/gensh2/console/config.c -- bsps/sh/gensh2/console/sci.c -- bsps/sh/gensh2/console/sci_termios.c -- bsps/sh/gensh2/console/scitab.c -- bsps/sh/gensh2/start/cpu_asm.c -- bsps/sh/gensh2/start/hw_init.c -- bsps/sh/gensh2/start/ispsh7045.c -- bsps/sh/shared/console/console.c -- bsps/sh/shared/start/bsphwinit.c -- bsps/sh/shared/start/bspstart.c -- bsps/shared/cache/nocache.c -- bsps/shared/dev/getentropy/getentropy-cpucounter.c -- bsps/shared/dev/serial/printk-dummy.c -- bsps/shared/start/bspreset-loop.c -- bsps/shared/start/gettargethash-default.c -- bsps/shared/start/sbrk.c -type: build diff --git a/spec/build/bsps/sh/gensh2/optcpuclk.yml b/spec/build/bsps/sh/gensh2/optcpuclk.yml deleted file mode 100644 index 85c2469d6c..0000000000 --- a/spec/build/bsps/sh/gensh2/optcpuclk.yml +++ /dev/null @@ -1,17 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-integer: null -- define: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: 20000000 -description: | - cpu clock rate in HZ -enabled-by: true -format: '{}' -links: [] -name: CPU_CLOCK_RATE_HZ -type: build diff --git a/spec/build/bsps/sh/gensh2/optevb.yml b/spec/build/bsps/sh/gensh2/optevb.yml deleted file mode 100644 index de5c08454c..0000000000 --- a/spec/build/bsps/sh/gensh2/optevb.yml +++ /dev/null @@ -1,16 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-boolean: null -- define-condition: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: false -description: | - If defined, compiles code to jump-start from FLASH, without a monitor -enabled-by: true -links: [] -name: STANDALONE_EVB -type: build diff --git a/spec/build/bsps/sh/gensh2/optlowinit.yml b/spec/build/bsps/sh/gensh2/optlowinit.yml deleted file mode 100644 index 71f5874577..0000000000 --- a/spec/build/bsps/sh/gensh2/optlowinit.yml +++ /dev/null @@ -1,16 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-boolean: null -- define-condition: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: false -description: | - If defined, selects whether 'early_hw_init()' is called from 'start.S'; 'bsp_hw_init()' is always called from 'bspstart.c' -enabled-by: true -links: [] -name: START_HW_INIT -type: build diff --git a/spec/build/bsps/sh/gensh2/start.yml b/spec/build/bsps/sh/gensh2/start.yml deleted file mode 100644 index 2fac1e9055..0000000000 --- a/spec/build/bsps/sh/gensh2/start.yml +++ /dev/null @@ -1,14 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -asflags: [] -build-type: start-file -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -includes: [] -install-path: ${BSP_LIBDIR} -links: [] -source: -- bsps/sh/gensh2/start/start.S -target: start.o -type: build diff --git a/spec/build/bsps/sh/gensh2/tstgensh2.yml b/spec/build/bsps/sh/gensh2/tstgensh2.yml deleted file mode 100644 index 8681b1e8f3..0000000000 --- a/spec/build/bsps/sh/gensh2/tstgensh2.yml +++ /dev/null @@ -1,23 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- set-test-state: - reason: null - state: exclude - tests: - - fileio - - iostream - - rcxx01 - - utf8proc01 - - validation-no-clock-0 -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: [] -description: '' -enabled-by: true -links: -- role: build-dependency - uid: ../../tstnoiconv -- role: build-dependency - uid: ../../tstsmallmem -type: build diff --git a/spec/build/bsps/sh/gensh4/abi.yml b/spec/build/bsps/sh/gensh4/abi.yml deleted file mode 100644 index bfa553dc9d..0000000000 --- a/spec/build/bsps/sh/gensh4/abi.yml +++ /dev/null @@ -1,19 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-string: null -- split: null -- env-append: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: - - -m4 - - -ml -description: | - ABI flags -enabled-by: true -links: [] -name: ABI_FLAGS -type: build diff --git a/spec/build/bsps/sh/gensh4/bspgensh4.yml b/spec/build/bsps/sh/gensh4/bspgensh4.yml deleted file mode 100644 index da0dbe294a..0000000000 --- a/spec/build/bsps/sh/gensh4/bspgensh4.yml +++ /dev/null @@ -1,72 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -arch: sh -bsp: gensh4 -build-type: bsp -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -family: gensh4 -includes: [] -install: -- destination: ${BSP_INCLUDEDIR} - source: - - bsps/sh/gensh4/include/bsp.h - - bsps/sh/gensh4/include/sdram.h -- destination: ${BSP_INCLUDEDIR}/bsp - source: - - bsps/sh/gensh4/include/bsp/irq.h -- destination: ${BSP_INCLUDEDIR}/rtems/score - source: - - bsps/sh/gensh4/include/rtems/score/iosh7750.h - - bsps/sh/gensh4/include/rtems/score/ipl.h - - bsps/sh/gensh4/include/rtems/score/ispsh7750.h - - bsps/sh/gensh4/include/rtems/score/sh4_regs.h - - bsps/sh/gensh4/include/rtems/score/sh7750_regs.h -- destination: ${BSP_INCLUDEDIR}/sh - source: - - bsps/sh/gensh4/include/sh/sh4uart.h -- destination: ${BSP_LIBDIR} - source: - - bsps/sh/gensh4/start/linkcmds - - bsps/sh/gensh4/start/linkcmds.rom - - bsps/sh/gensh4/start/linkcmds.rom2ram -links: -- role: build-dependency - uid: ../../obj -- role: build-dependency - uid: ../../objirqdflt -- role: build-dependency - uid: ../../objmem -- role: build-dependency - uid: ../../opto2 -- role: build-dependency - uid: abi -- role: build-dependency - uid: optcpuclk -- role: build-dependency - uid: optcpydata -- role: build-dependency - uid: optlowinit -- role: build-dependency - uid: start -- role: build-dependency - uid: ../../bspopts -source: -- bsps/sh/gensh4/btimer/btimer.c -- bsps/sh/gensh4/clock/ckinit.c -- bsps/sh/gensh4/console/console.c -- bsps/sh/gensh4/console/sh4uart.c -- bsps/sh/gensh4/start/cpu_asm.c -- bsps/sh/gensh4/start/hw_init.c -- bsps/sh/gensh4/start/ispsh7750.c -- bsps/sh/shared/start/bsphwinit.c -- bsps/sh/shared/start/bspstart.c -- bsps/shared/cache/nocache.c -- bsps/shared/dev/getentropy/getentropy-cpucounter.c -- bsps/shared/dev/serial/printk-dummy.c -- bsps/shared/start/bspreset-loop.c -- bsps/shared/start/gettargethash-default.c -- bsps/shared/start/sbrk.c -type: build diff --git a/spec/build/bsps/sh/gensh4/optcpuclk.yml b/spec/build/bsps/sh/gensh4/optcpuclk.yml deleted file mode 100644 index 85c2469d6c..0000000000 --- a/spec/build/bsps/sh/gensh4/optcpuclk.yml +++ /dev/null @@ -1,17 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-integer: null -- define: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: 20000000 -description: | - cpu clock rate in HZ -enabled-by: true -format: '{}' -links: [] -name: CPU_CLOCK_RATE_HZ -type: build diff --git a/spec/build/bsps/sh/gensh4/optcpydata.yml b/spec/build/bsps/sh/gensh4/optcpydata.yml deleted file mode 100644 index 6bcc2113af..0000000000 --- a/spec/build/bsps/sh/gensh4/optcpydata.yml +++ /dev/null @@ -1,16 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-boolean: null -- define-condition: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: false -description: | - Whether to copy data from ROM to RAM in start.S -enabled-by: true -links: [] -name: COPY_DATA_FROM_ROM -type: build diff --git a/spec/build/bsps/sh/gensh4/optlowinit.yml b/spec/build/bsps/sh/gensh4/optlowinit.yml deleted file mode 100644 index 5277350ab3..0000000000 --- a/spec/build/bsps/sh/gensh4/optlowinit.yml +++ /dev/null @@ -1,16 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-boolean: null -- define-condition: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: false -description: | - Whether to call early_hw_init from start.S -enabled-by: true -links: [] -name: START_HW_INIT -type: build diff --git a/spec/build/bsps/sh/gensh4/start.yml b/spec/build/bsps/sh/gensh4/start.yml deleted file mode 100644 index d3b7aa6210..0000000000 --- a/spec/build/bsps/sh/gensh4/start.yml +++ /dev/null @@ -1,14 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -asflags: [] -build-type: start-file -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -includes: [] -install-path: ${BSP_LIBDIR} -links: [] -source: -- bsps/sh/gensh4/start/start.S -target: start.o -type: build diff --git a/spec/build/bsps/sh/shsim/abi.yml b/spec/build/bsps/sh/shsim/abi.yml deleted file mode 100644 index aea8763903..0000000000 --- a/spec/build/bsps/sh/shsim/abi.yml +++ /dev/null @@ -1,29 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-string: null -- split: null -- env-append: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: sh/simsh2e - value: - - -m2e - - -ml -- enabled-by: sh/simsh2 - value: - - -m2 -- enabled-by: sh/simsh1 - value: - - -m1 -- enabled-by: true - value: - - -m4 - - -ml -description: | - ABI flags -enabled-by: true -links: [] -name: ABI_FLAGS -type: build diff --git a/spec/build/bsps/sh/shsim/bspsimsh1.yml b/spec/build/bsps/sh/shsim/bspsimsh1.yml deleted file mode 100644 index fd94cccb19..0000000000 --- a/spec/build/bsps/sh/shsim/bspsimsh1.yml +++ /dev/null @@ -1,21 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -arch: sh -bsp: simsh1 -build-type: bsp -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -family: shsim -includes: [] -install: [] -links: -- role: build-dependency - uid: ../../opto2 -- role: build-dependency - uid: grp -- role: build-dependency - uid: tstsimsh1 -source: [] -type: build diff --git a/spec/build/bsps/sh/shsim/bspsimsh2.yml b/spec/build/bsps/sh/shsim/bspsimsh2.yml deleted file mode 100644 index 31c8a76ab8..0000000000 --- a/spec/build/bsps/sh/shsim/bspsimsh2.yml +++ /dev/null @@ -1,21 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -arch: sh -bsp: simsh2 -build-type: bsp -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -family: shsim -includes: [] -install: [] -links: -- role: build-dependency - uid: ../../opto2 -- role: build-dependency - uid: grp -- role: build-dependency - uid: tstsimsh2 -source: [] -type: build diff --git a/spec/build/bsps/sh/shsim/bspsimsh2e.yml b/spec/build/bsps/sh/shsim/bspsimsh2e.yml deleted file mode 100644 index 5133bd888f..0000000000 --- a/spec/build/bsps/sh/shsim/bspsimsh2e.yml +++ /dev/null @@ -1,21 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -arch: sh -bsp: simsh2e -build-type: bsp -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -family: shsim -includes: [] -install: [] -links: -- role: build-dependency - uid: ../../opto2 -- role: build-dependency - uid: grp -- role: build-dependency - uid: tstsimsh2e -source: [] -type: build diff --git a/spec/build/bsps/sh/shsim/bspsimsh4.yml b/spec/build/bsps/sh/shsim/bspsimsh4.yml deleted file mode 100644 index 6000d2e224..0000000000 --- a/spec/build/bsps/sh/shsim/bspsimsh4.yml +++ /dev/null @@ -1,21 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -arch: sh -bsp: simsh4 -build-type: bsp -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -family: shsim -includes: [] -install: [] -links: -- role: build-dependency - uid: ../../opto2 -- role: build-dependency - uid: grp -- role: build-dependency - uid: tstsimsh4 -source: [] -type: build diff --git a/spec/build/bsps/sh/shsim/grp.yml b/spec/build/bsps/sh/shsim/grp.yml deleted file mode 100644 index c7c72dc22e..0000000000 --- a/spec/build/bsps/sh/shsim/grp.yml +++ /dev/null @@ -1,33 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -build-type: group -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -cxxflags: [] -enabled-by: true -includes: [] -install: [] -ldflags: [] -links: -- role: build-dependency - uid: ../../obj -- role: build-dependency - uid: ../../objirqdflt -- role: build-dependency - uid: abi -- role: build-dependency - uid: obj -- role: build-dependency - uid: ../../objmem -- role: build-dependency - uid: optcpuclk -- role: build-dependency - uid: optlowinit -- role: build-dependency - uid: start -- role: build-dependency - uid: ../../bspopts -type: build -use-after: [] -use-before: [] diff --git a/spec/build/bsps/sh/shsim/obj.yml b/spec/build/bsps/sh/shsim/obj.yml deleted file mode 100644 index b64c40feca..0000000000 --- a/spec/build/bsps/sh/shsim/obj.yml +++ /dev/null @@ -1,39 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -build-type: objects -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -cxxflags: [] -enabled-by: true -includes: [] -install: -- destination: ${BSP_INCLUDEDIR} - source: - - bsps/sh/shsim/include/bsp.h -- destination: ${BSP_INCLUDEDIR}/bsp - source: - - bsps/sh/shsim/include/bsp/irq.h - - bsps/sh/shsim/include/bsp/syscall.h -- destination: ${BSP_LIBDIR} - source: - - bsps/sh/shsim/start/linkcmds -links: [] -source: -- bsps/sh/shared/start/bsphwinit.c -- bsps/sh/shared/start/bspstart.c -- bsps/sh/shsim/console/console-debugio.c -- bsps/sh/shsim/console/console-io.c -- bsps/sh/shsim/console/console-support.S -- bsps/sh/shsim/start/cpu_asm.c -- bsps/sh/shsim/start/ispshgdb.c -- bsps/sh/shsim/start/sysexit.c -- bsps/shared/cache/nocache.c -- bsps/shared/dev/btimer/btimer-cpucounter.c -- bsps/shared/dev/clock/clock-simidle.c -- bsps/shared/dev/getentropy/getentropy-cpucounter.c -- bsps/shared/dev/serial/console-polled.c -- bsps/shared/start/bspreset-loop.c -- bsps/shared/start/gettargethash-default.c -- bsps/shared/start/sbrk.c -type: build diff --git a/spec/build/bsps/sh/shsim/optcpuclk.yml b/spec/build/bsps/sh/shsim/optcpuclk.yml deleted file mode 100644 index 85c2469d6c..0000000000 --- a/spec/build/bsps/sh/shsim/optcpuclk.yml +++ /dev/null @@ -1,17 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-integer: null -- define: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: 20000000 -description: | - cpu clock rate in HZ -enabled-by: true -format: '{}' -links: [] -name: CPU_CLOCK_RATE_HZ -type: build diff --git a/spec/build/bsps/sh/shsim/optlowinit.yml b/spec/build/bsps/sh/shsim/optlowinit.yml deleted file mode 100644 index 71f5874577..0000000000 --- a/spec/build/bsps/sh/shsim/optlowinit.yml +++ /dev/null @@ -1,16 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-boolean: null -- define-condition: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: false -description: | - If defined, selects whether 'early_hw_init()' is called from 'start.S'; 'bsp_hw_init()' is always called from 'bspstart.c' -enabled-by: true -links: [] -name: START_HW_INIT -type: build diff --git a/spec/build/bsps/sh/shsim/start.yml b/spec/build/bsps/sh/shsim/start.yml deleted file mode 100644 index 59d9356f75..0000000000 --- a/spec/build/bsps/sh/shsim/start.yml +++ /dev/null @@ -1,14 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -asflags: [] -build-type: start-file -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -includes: [] -install-path: ${BSP_LIBDIR} -links: [] -source: -- bsps/sh/shsim/start/start.S -target: start.o -type: build diff --git a/spec/build/bsps/sh/shsim/tstsimsh1.yml b/spec/build/bsps/sh/shsim/tstsimsh1.yml deleted file mode 100644 index 612af75c1c..0000000000 --- a/spec/build/bsps/sh/shsim/tstsimsh1.yml +++ /dev/null @@ -1,28 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- set-test-state: - reason: null - state: exclude - tests: - - fileio - - fsdosfsname01 - - iostream - - linpack - - rcxx01 - - record02 - - utf8proc01 - - validation-no-clock-0 -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: [] -description: '' -enabled-by: true -links: -- role: build-dependency - uid: ../../tstnoiconv -- role: build-dependency - uid: ../../tstnointrcrit -- role: build-dependency - uid: ../../tstreqtick -type: build diff --git a/spec/build/bsps/sh/shsim/tstsimsh2.yml b/spec/build/bsps/sh/shsim/tstsimsh2.yml deleted file mode 100644 index 612af75c1c..0000000000 --- a/spec/build/bsps/sh/shsim/tstsimsh2.yml +++ /dev/null @@ -1,28 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- set-test-state: - reason: null - state: exclude - tests: - - fileio - - fsdosfsname01 - - iostream - - linpack - - rcxx01 - - record02 - - utf8proc01 - - validation-no-clock-0 -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: [] -description: '' -enabled-by: true -links: -- role: build-dependency - uid: ../../tstnoiconv -- role: build-dependency - uid: ../../tstnointrcrit -- role: build-dependency - uid: ../../tstreqtick -type: build diff --git a/spec/build/bsps/sh/shsim/tstsimsh2e.yml b/spec/build/bsps/sh/shsim/tstsimsh2e.yml deleted file mode 100644 index 612af75c1c..0000000000 --- a/spec/build/bsps/sh/shsim/tstsimsh2e.yml +++ /dev/null @@ -1,28 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- set-test-state: - reason: null - state: exclude - tests: - - fileio - - fsdosfsname01 - - iostream - - linpack - - rcxx01 - - record02 - - utf8proc01 - - validation-no-clock-0 -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: [] -description: '' -enabled-by: true -links: -- role: build-dependency - uid: ../../tstnoiconv -- role: build-dependency - uid: ../../tstnointrcrit -- role: build-dependency - uid: ../../tstreqtick -type: build diff --git a/spec/build/bsps/sh/shsim/tstsimsh4.yml b/spec/build/bsps/sh/shsim/tstsimsh4.yml deleted file mode 100644 index 612af75c1c..0000000000 --- a/spec/build/bsps/sh/shsim/tstsimsh4.yml +++ /dev/null @@ -1,28 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- set-test-state: - reason: null - state: exclude - tests: - - fileio - - fsdosfsname01 - - iostream - - linpack - - rcxx01 - - record02 - - utf8proc01 - - validation-no-clock-0 -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: [] -description: '' -enabled-by: true -links: -- role: build-dependency - uid: ../../tstnoiconv -- role: build-dependency - uid: ../../tstnointrcrit -- role: build-dependency - uid: ../../tstreqtick -type: build diff --git a/spec/build/cpukit/cpush.yml b/spec/build/cpukit/cpush.yml deleted file mode 100644 index 61e178d442..0000000000 --- a/spec/build/cpukit/cpush.yml +++ /dev/null @@ -1,29 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -build-type: objects -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -cxxflags: [] -enabled-by: -- sh -includes: [] -install: -- destination: ${BSP_INCLUDEDIR}/rtems - source: - - cpukit/score/cpu/sh/include/rtems/asm.h -- destination: ${BSP_INCLUDEDIR}/rtems/score - source: - - cpukit/score/cpu/sh/include/rtems/score/cpu.h - - cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h - - cpukit/score/cpu/sh/include/rtems/score/sh.h - - cpukit/score/cpu/sh/include/rtems/score/sh_io.h -links: [] -source: -- cpukit/score/cpu/no_cpu/cpucounterfrequency.c -- cpukit/score/cpu/no_cpu/cpucounterread.c -- cpukit/score/cpu/no_cpu/cpuidle.c -- cpukit/score/cpu/sh/context.c -- cpukit/score/cpu/sh/cpu.c -- cpukit/score/cpu/sh/sh-exception-frame-print.c -type: build diff --git a/spec/build/cpukit/librtemscpu.yml b/spec/build/cpukit/librtemscpu.yml index c32cd56943..4187456840 100644 --- a/spec/build/cpukit/librtemscpu.yml +++ b/spec/build/cpukit/librtemscpu.yml @@ -502,8 +502,6 @@ links: uid: cpupowerpc - role: build-dependency uid: cpuriscv -- role: build-dependency - uid: cpush - role: build-dependency uid: cpusparc - role: build-dependency