cmake: Improve nuttx_generate_kconfig()

Enhance the nuttx_generate_kconfig() implementation to ensure that
both subdirectories and external directories containing a CMakeLists.txt
or a Kconfig file are properly included during Kconfig generation.

Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>

Documentation/platforms/avr/avrdx/docs/twi.rst

@@ -0,0 +1,109 @@
+===============================
+Two Wire Interface in AVR DA/DB
+===============================
+
+Two Wire Interface is AVR peripheral capable of supporting both I\ :sup:`2`\ C and SMBus.
+
+Usage
+=====
+
+
+Pointer to initialized ``struct i2c_master_s`` can be obtained using
+
+.. code-block:: c
+
+   FAR struct i2c_master_s *i2c;
+   i2c = avrdx_initialize_twi(0);
+
+
+This function will initialize the peripheral based on configuration specified
+via Kconfig. It may be called multiple times, only first call will perform
+the initialization - subsequent calls will only return the pointer.
+
+Deinitialization is currently not supported.
+
+The parameter denotes which peripheral is to be initialized. With current chips,
+permitted values are ``0`` and ``1``.
+It is ignored if the chip has only single TWI interface.
+
+Configuration options
+=====================
+
+Pin selection
+-------------
+
+This option makes it possible to choose which I/O pins will be connected
+to the peripheral.
+
+Mode selection
+--------------
+
+The peripheral supports Standard, Fast and Fast Plus modes.
+
+Quick commands
+--------------
+
+SMBus permits transactions that contain no data. Instead, the R/nW bit
+is interpreted as a single-bit datum by the target device. If this is enabled,
+I\ :sup:`2`\ C messages with zero length are interpreted as quick commands. If not,
+zero-length messages are not permitted and the transmission is rejected
+with ``EINVAL``
+
+Forbid NOSTART
+--------------
+
+NuttX upper half of the I\ :sup:`2`\ C driver permits ``I2C_M_NOSTART``
+flag for a message, indicating that the message is not a standalone entity
+but rather a continuation of previous message. Since not all drivers need
+this and program memory space is not unlimited on the chip, this configuration
+option can be used to remove support for such messages.
+
+Transmission that submits message with this flag will be rejected
+with ``EINVAL`` if this configuration option is set. Enable this only
+if you know internals of I\ :sup:`2`\ C drivers used by your application.
+
+Limitations
+===========
+
+Mode and addressing
+-------------------
+
+Currently, only master mode is supported.
+
+Only 7-bit addressing is supported. The peripheral does not support 10-bit
+addressing directly and the driver software does currently have no support
+for that either. I\ :sup:`2`\ C messages requesting 10-bit address
+are rejected with ``ENOTSUP``.
+
+Message limitations
+-------------------
+
+Maximum message count for single transmission is 127.
+
+The driver does not support ``I2C_M_NOSTOP`` flag for last submitted message.
+As per rules specified in ``include/nuttx/i2c/i2c_master.h``, the I\ :sup:`2`\ C
+driver lower half is supposed to leave the bus occupied if the last
+of the submitted messages has this ``NOSTOP`` flag set. This driver
+is not capable of doing that.
+
+Also not supported is ``I2C_M_NOSTART`` flag for first submitted message.
+First message within the transfer always starts with ``START`` condition.
+
+Messages with zero length (which are only permitted based on configuration
+- see above) may not specify ``I2C_M_NOSTART`` nor ``I2C_M_NOSTOP``.
+(Such a message is interpreted as a quick command and quick commands
+must end with a ``STOP`` condition according to the chip's documentation.)
+
+Inactivity timeout
+------------------
+
+The driver configures timeout for bus inactivity during initialization.
+This timeout is used by the hardware to switch its internal state
+from "bus is busy" or "bus is in unknown state" to "bus is idle."
+This transition otherwise only happens after a ``STOP`` condition is detected
+or when forced by software.
+
+This timeout remains in effect during normal TWI operation as well.
+Such a timeout is defined for SMBus but not for I\ :sup:`2`\ C; nevertheless,
+the driver does not distinguish between the two and the timeout is always
+in place.

Documentation/platforms/avr/avrdx/index.rst

@@ -51,12 +51,13 @@ Peripheral Support
 
 The following list indicates peripherals supported in NuttX:
 
-==========  ================
+==========  =======================
 Peripheral  Notes
-==========  ================
+==========  =======================
 GPIO        In board code
 UART        See below
-==========  ================
+TWI         Master only, more below
+==========  =======================
 
 GPIO
 ----
@@ -101,6 +102,12 @@ This for example means that ``USART1`` peripheral will always
 be accessed through ``/dev/ttyS1`` regardless of what other ``USART``
 peripherals are enabled (if any.)
 
+TWI
+---
+
+Currently, only master is supported. Implementation details and quick
+usage instructions can be found in :doc:`docs/twi` document.
+
 Supported Boards
 ================
 

Documentation/platforms/xtensa/esp32s2/boards/esp32s2-saola-1/index.rst

@@ -423,6 +423,69 @@ using 1 second delay)::
 
     nsh> qe
 
+pm
+-------
+
+This config demonstrate the use of power management.
+You can use the ``pmconfig`` command to check current power state and time spent in other power states.
+Also you can define time will spend in standby and sleep modes::
+
+    $ make menuconfig
+    -> Board Selection
+        -> (15) PM_STANDBY delay (seconds)
+           (0)  PM_STANDBY delay (nanoseconds)
+           (20) PM_SLEEP delay (seconds)
+           (0)  PM_SLEEP delay (nanoseconds)
+
+Timer wakeup is not only way to wake up the chip. Other wakeup modes include:
+
+- EXT1 wakeup mode: Uses RTC GPIO pins to wake up the chip. Enabled with ``CONFIG_PM_EXT1_WAKEUP`` option.
+- ULP coprocessor wakeup mode: Uses ULP RISC-V co-processor to wake up the chip. Enabled with ``CONFIG_PM_ULP_WAKEUP`` option.
+- GPIO wakeup mode: Uses GPIO pins to wakeup the chip. Only wakes up the chip from ``PM_STANDBY`` mode and requires ``CONFIG_PM_GPIO_WAKEUP``.
+- UART wakeup mode: Uses UART to wakeup the chip. Only wakes up the chip from ``PM_STANDBY`` mode and requires ``CONFIG_PM_GPIO_WAKEUP``.
+
+Before switching PM status, you need to query the current PM status to call correct number of relax command to correct modes::
+
+    nsh> pmconfig
+    Last state 0, Next state 0
+
+    /proc/pm/state0:
+    DOMAIN0           WAKE         SLEEP         TOTAL
+    normal          0s 00%        0s 00%        0s 00%
+    idle            0s 00%        0s 00%        0s 00%
+    standby         0s 00%        0s 00%        0s 00%
+    sleep           0s 00%        0s 00%        0s 00%
+
+    /proc/pm/wakelock0:
+    DOMAIN0      STATE     COUNT      TIME
+    system       normal        2        1s
+    system       idle          1        1s
+    system       standby       1        1s
+    system       sleep         1        1s
+
+In this case, needed commands to switch the system into PM idle mode::
+
+    nsh> pmconfig relax normal
+    nsh> pmconfig relax normal
+
+In this case, needed commands to switch the system into PM standby mode::
+
+    nsh> pmconfig relax idle
+    nsh> pmconfig relax normal
+    nsh> pmconfig relax normal
+
+System switch to the PM sleep mode, you need to enter::
+
+    nsh> pmconfig relax standby
+    nsh> pmconfig relax idle
+    nsh> pmconfig relax normal
+    nsh> pmconfig relax normal
+
+Note: When normal mode COUNT is 0, it will switch to the next PM state where COUNT is not 0.
+
+Note: During light sleep, overall current consumption of board should drop from 26ma (without any system load) to 3.5 mA on ESP32-S2 Saola-1.
+During deep sleep, current consumption of board should drop from 26 (without any system load) to 1.24 mA.
+
 pwm
 ------
 

arch/arm/src/kl/CMakeLists.txt

@@ -0,0 +1,72 @@
+# ##############################################################################
+# arch/arm/src/kl/CMakeLists.txt
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more contributor
+# license agreements.  See the NOTICE file distributed with this work for
+# additional information regarding copyright ownership.  The ASF licenses this
+# file to you under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License.  You may obtain a copy of
+# the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations under
+# the License.
+#
+# ##############################################################################
+
+list(
+  APPEND
+  SRCS
+  kl_clockconfig.c
+  kl_gpio.c
+  kl_irq.c
+  kl_lowputc.c
+  kl_serial.c
+  kl_start.c
+  kl_cfmconfig.c)
+
+# Configuration-dependent Kinetis L files
+
+if(NOT CONFIG_ARCH_IDLE_CUSTOM)
+  list(APPEND SRCS kl_idle.c)
+endif()
+
+if(NOT CONFIG_SCHED_TICKLESS)
+  list(APPEND SRCS kl_timerisr.c)
+endif()
+
+if(CONFIG_BUILD_PROTECTED)
+  list(APPEND SRCS kl_userspace.c)
+endif()
+
+if(CONFIG_KL_GPIOIRQ)
+  list(APPEND SRCS kl_gpioirq.c)
+endif()
+
+if(CONFIG_ARCH_IRQPRIO)
+  list(APPEND SRCS kl_irqprio.c)
+endif()
+
+if(CONFIG_KL_SPI0)
+  list(APPEND SRCS kl_spi.c)
+else()
+  if(CONFIG_KL_SPI1)
+    list(APPEND SRCS kl_spi.c)
+  endif()
+endif()
+
+if(CONFIG_PWM)
+  list(APPEND SRCS kl_pwm.c)
+endif()
+
+if(CONFIG_DEBUG_FEATURES)
+  list(APPEND SRCS kl_dumpgpio.c)
+endif()
+
+target_sources(arch PRIVATE ${SRCS})

arch/arm64/src/imx9/Kconfig

@@ -1013,6 +1013,15 @@ config IMX9_ENET_USE_OTP_MAC
 	default n
 	depends on IMX9_ENET
 
+config IMX9_ENET_HPWORK
+	bool "Use high priority work queue for ethernet"
+	depends on IMX9_ENET
+	depends on SCHED_HPWORK
+	default n
+	---help---
+		Use high-priority work-queue for ethernet packet handling.
+		Enable if low-latency ethernet packet handling is required.
+
 config IMX9_ENET1_OTP_MAC_ADDR
 	hex "MAC address offset in OCOTP"
 	default 0x4ec

arch/arm64/src/imx9/imx9_enet.c

@@ -74,15 +74,22 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-/* If processing is not done at the interrupt level, then work queue support
- * is required.
+/* Select work queue for normal operation */
+
+#  if defined(CONFIG_IMX9_ENET_HPWORK)
+#    define ETHWORK HPWORK
+#  else
+#    define ETHWORK LPWORK
+#  endif
+
+/* LPWORK support is always required. Even if HPWORK were used for normal
+ * operation, timeouts are only handled in LPWORK since phy communication
+ * might cause delays due to polling
  */
 
-#if !defined(CONFIG_SCHED_LPWORK)
-#  error LPWORK queue support is required
-#endif
-
-#define ETHWORK LPWORK
+#  if !defined(CONFIG_SCHED_LPWORK)
+#    error LPWORK queue support is required
+#  endif
 
 /* We need at least two TX buffers for reliable operation */
 
@@ -1282,10 +1289,13 @@ static void imx9_txtimeout_expiry(wdparm_t arg)
   priv->ints = 0;
 
   /* Schedule to perform the TX timeout processing on the worker thread,
-   * canceling any pending interrupt work.
+   * canceling any pending interrupt work. Note: this runs always in the
+   * low-priority queue instead of ETHWORK. It is too intrusive for the
+   * high-priority queue, running ifdown / ifup sequence and communicating
+   * with PHY.
    */
 
-  work_queue(ETHWORK, &priv->irqwork, imx9_txtimeout_work, priv, 0);
+  work_queue(LPWORK, &priv->irqwork, imx9_txtimeout_work, priv, 0);
 }
 
 /****************************************************************************

arch/avr/src/avrdx/Kconfig

@@ -8,17 +8,55 @@ comment "AVR DA/DB Configuration Options"
 
 # Hidden configuration options selected by specific chip
 # Available serial ports
-config AVR_HAS_USART_2
+config AVR_HAVE_USART_2
 	bool
 	default n
+	---help---
+		Chip has USART 2 (and also 0 and 1)
 
-config AVR_HAS_USART_4
+config AVR_HAVE_USART_4
 	bool
 	default n
+	---help---
+		Chip has USART 4 (and also 3)
 
-config AVR_HAS_USART_5
+config AVR_HAVE_USART_5
 	bool
 	default n
+	---help---
+		Chip has USART 5
+
+# Available alternate pinouts for serial ports
+# USART0 omitted, all chips have that
+config AVR_HAVE_USART1_ALT1
+	bool
+	default n
+	---help---
+		Chip has alternate pin position for USART 1
+
+config AVR_HAVE_USART2_ALT1
+	bool
+	default n
+	---help---
+		Chip has alternate pin position for USART 2
+
+config AVR_HAVE_USART3_ALT1
+	bool
+	default n
+	---help---
+		Chip has alternate pin position for USART 3
+
+config AVR_HAVE_USART4_ALT1
+	bool
+	default n
+	---help---
+		Chip has alternate pin position for USART 4
+
+config AVR_HAVE_USART5_ALT1
+	bool
+	default n
+	---help---
+		Chip has alternate pin position for USART 5
 
 # Available I/O ports (only those not common for all devices)
 config AVR_HAS_PORTB
@@ -33,6 +71,23 @@ config AVR_HAS_PORTG
 	bool
 	default n
 
+# Available TWI interfaces and their options (not common for all devices)
+config AVR_HAVE_TWI0_ALT1
+	bool
+	default n
+	---help---
+		Chip has alternate pin configuration 1 for TWI0
+
+config AVR_HAVE_TWI1
+	bool
+	default n
+
+config AVR_HAVE_TWI1_ALT1
+	bool
+	default n
+	---help---
+		Chip has alternate pin configuration 1 for TW1
+
 choice
 	prompt "Atmel AVR DA/DB chip selection"
 	default ARCH_CHIP_AVR128DA28
@@ -40,31 +95,47 @@ choice
 config ARCH_CHIP_AVR128DA28
 	bool "AVR128DA28"
 	select AVR_HAS_RAMPZ
-	select AVR_HAS_USART_2
+	select AVR_HAVE_USART_2
 	---help---
 		Atmel AVR128DA28 8-bit AVR.
 
 config ARCH_CHIP_AVR128DA64
 	bool "AVR128DA64"
 	select AVR_HAS_RAMPZ
-	select AVR_HAS_USART_2
-	select AVR_HAS_USART_4
-	select AVR_HAS_USART_5
+	select AVR_HAVE_USART_2
+	select AVR_HAVE_USART1_ALT1
+	select AVR_HAVE_USART2_ALT1
+	select AVR_HAVE_USART_4
+	select AVR_HAVE_USART3_ALT1
+	select AVR_HAVE_USART4_ALT1
+	select AVR_HAVE_USART_5
+	select AVR_HAVE_USART5_ALT1
 	select AVR_HAS_PORTB
 	select AVR_HAS_PORTE
 	select AVR_HAS_PORTG
+	select AVR_HAVE_TWI0_ALT1
+	select AVR_HAVE_TWI1
+	select AVR_HAVE_TWI1_ALT1
 	---help---
 		Atmel AVR128DA64 8-bit AVR.
 
 config ARCH_CHIP_AVR128DB64
 	bool "AVR128DB64"
 	select AVR_HAS_RAMPZ
-	select AVR_HAS_USART_2
-	select AVR_HAS_USART_4
-	select AVR_HAS_USART_5
+	select AVR_HAVE_USART_2
+	select AVR_HAVE_USART1_ALT1
+	select AVR_HAVE_USART2_ALT1
+	select AVR_HAVE_USART_4
+	select AVR_HAVE_USART3_ALT1
+	select AVR_HAVE_USART4_ALT1
+	select AVR_HAVE_USART_5
+	select AVR_HAVE_USART5_ALT1
 	select AVR_HAS_PORTB
 	select AVR_HAS_PORTE
 	select AVR_HAS_PORTG
+	select AVR_HAVE_TWI0_ALT1
+	select AVR_HAVE_TWI1
+	select AVR_HAVE_TWI1_ALT1
 	---help---
 		Atmel AVR128DB64 8-bit AVR.
 
@@ -87,98 +158,366 @@ config AVR_USART0
 	bool "Enable serial driver for USART0"
 	select USART0_SERIALDRIVER
 	select ARCH_HAVE_SERIAL_TERMIOS
-	depends on AVR_HAS_USART_2
+	depends on AVR_HAVE_USART_2
 	depends on SERIAL
 	---help---
 		Enable serial driver on USART0
 
-config AVR_USART0_ALT
-	bool "Activate USART0 alternative pinout"
+choice AVR_USART0_MUX
+	prompt "USART0 pin selection"
 	depends on AVR_USART0
+	default AVR_USART0_DEFAULT
+	---help---
+		Select which I/O pins will be driven by USART0 interface.
+		Refer to I/O Multiplexing and Port Multiplexer sections
+		in chip documentation for specifics.
+
+config AVR_USART0_DEFAULT
+	bool "Default USART0 pinout"
+
+config AVR_USART0_ALT
+	bool "Alternate USART0 pinout"
 	---help---
 		Board is wired to use alternative I/O pins,
 		4-5 instead of 0-1 for TxD/RxD
 
+config AVR_USART0_NONE
+	bool "Not connected"
+
+endchoice
+
 config AVR_USART1
 	bool "Enable serial driver for USART1"
 	select USART1_SERIALDRIVER
 	select ARCH_HAVE_SERIAL_TERMIOS
-	depends on AVR_HAS_USART_2
+	depends on AVR_HAVE_USART_2
 	depends on SERIAL
 	---help---
 		Enable serial driver on USART1
 
-config AVR_USART1_ALT
-	bool "Activate USART1 alternative pinout"
+choice AVR_USART1_MUX
+	prompt "USART1 pin selection"
 	depends on AVR_USART1
+	default AVR_USART1_DEFAULT
+	---help---
+		Select which I/O pins will be driven by USART1 interface.
+		Refer to I/O Multiplexing and Port Multiplexer sections
+		in chip documentation for specifics.
+
+config AVR_USART1_DEFAULT
+	bool "Default USART1 pinout"
+
+config AVR_USART1_ALT
+	depends on AVR_HAVE_USART1_ALT1
+	bool "Alternate USART1 pinout"
 	---help---
 		Board is wired to use alternative I/O pins,
 		4-5 instead of 0-1 for TxD/RxD
 
+config AVR_USART1_NONE
+	bool "Not connected"
+
+endchoice
+
 config AVR_USART2
 	bool "Enable serial driver for USART2"
 	select USART2_SERIALDRIVER
 	select ARCH_HAVE_SERIAL_TERMIOS
-	depends on AVR_HAS_USART_2
+	depends on AVR_HAVE_USART_2
 	depends on SERIAL
 	---help---
 		Enable serial driver on USART2
 
-config AVR_USART2_ALT
-	bool "Activate USART2 alternative pinout"
+choice AVR_USART2_MUX
+	prompt "USART2 pin selection"
 	depends on AVR_USART2
+	default AVR_USART2_DEFAULT
+	---help---
+		Select which I/O pins will be driven by USART2 interface.
+		Refer to I/O Multiplexing and Port Multiplexer sections
+		in chip documentation for specifics.
+
+config AVR_USART2_DEFAULT
+	bool "Default USART2 pinout"
+
+config AVR_USART2_ALT
+	depends on AVR_HAVE_USART2_ALT1
+	bool "Alternate USART2 pinout"
 	---help---
 		Board is wired to use alternative I/O pins,
 		4-5 instead of 0-1 for TxD/RxD
 
+config AVR_USART2_NONE
+	bool "Not connected"
+
+endchoice
+
 config AVR_USART3
 	bool "Enable serial driver for USART3"
 	select USART3_SERIALDRIVER
 	select ARCH_HAVE_SERIAL_TERMIOS
-	depends on AVR_HAS_USART_4
+	depends on AVR_HAVE_USART_4
 	depends on SERIAL
 	---help---
 		Enable serial driver on USART3
 
-config AVR_USART3_ALT
-	bool "Activate USART3 alternative pinout"
+choice AVR_USART3_MUX
+	prompt "USART3 pin selection"
 	depends on AVR_USART3
+	default AVR_USART3_DEFAULT
+	---help---
+		Select which I/O pins will be driven by USART3 interface.
+		Refer to I/O Multiplexing and Port Multiplexer sections
+		in chip documentation for specifics.
+
+config AVR_USART3_DEFAULT
+	bool "Default USART3 pinout"
+
+config AVR_USART3_ALT
+	depends on AVR_HAVE_USART3_ALT1
+	bool "Alternate USART3 pinout"
 	---help---
 		Board is wired to use alternative I/O pins,
 		4-5 instead of 0-1 for TxD/RxD
 
+config AVR_USART3_NONE
+	bool "Not connected"
+
+endchoice
+
 config AVR_USART4
 	bool "Enable serial driver for USART4"
 	select USART4_SERIALDRIVER
 	select ARCH_HAVE_SERIAL_TERMIOS
-	depends on AVR_HAS_USART_4
+	depends on AVR_HAVE_USART_4
 	depends on SERIAL
 	---help---
 		Enable serial driver on USART1
 
-config AVR_USART4_ALT
-	bool "Activate USART4 alternative pinout"
+choice AVR_USART4_MUX
+	prompt "USART4 pin selection"
 	depends on AVR_USART4
+	default AVR_USART4_DEFAULT
+	---help---
+		Select which I/O pins will be driven by USART4 interface.
+		Refer to I/O Multiplexing and Port Multiplexer sections
+		in chip documentation for specifics.
+
+config AVR_USART4_DEFAULT
+	bool "Default USART4 pinout"
+
+config AVR_USART4_ALT
+	depends on AVR_HAVE_USART4_ALT1
+	bool "Alternate USART4 pinout"
 	---help---
 		Board is wired to use alternative I/O pins,
 		4-5 instead of 0-1 for TxD/RxD
 
+config AVR_USART4_NONE
+	bool "Not connected"
+
+endchoice
+
 config AVR_USART5
 	bool "Enable serial driver for USART5"
 	select USART5_SERIALDRIVER
 	select ARCH_HAVE_SERIAL_TERMIOS
-	depends on AVR_HAS_USART_5
+	depends on AVR_HAVE_USART_5
 	depends on SERIAL
 	---help---
 		Enable serial driver on USART5
 
-config AVR_USART5_ALT
-	bool "Activate USART5 alternative pinout"
+choice AVR_USART5_MUX
+	prompt "USART5 pin selection"
 	depends on AVR_USART5
+	default AVR_USART5_DEFAULT
+	---help---
+		Select which I/O pins will be driven by USART5 interface.
+		Refer to I/O Multiplexing and Port Multiplexer sections
+		in chip documentation for specifics.
+
+config AVR_USART5_DEFAULT
+	bool "Default USART5 pinout"
+
+config AVR_USART5_ALT
+	depends on AVR_HAVE_USART5_ALT1
+	bool "Alternate USART5 pinout"
 	---help---
 		Board is wired to use alternative I/O pins,
 		4-5 instead of 0-1 for TxD/RxD
 
+config AVR_USART5_NONE
+	bool "Not connected"
+
+endchoice
+
+config AVR_TWI0
+	bool "Enable TWI (I2C) driver for interface 0"
+	depends on I2C
+	---help---
+		Enable driver for TWI0
+
+choice AVR_TWI0_ALT
+	prompt "TWI0 pin selection"
+	depends on AVR_TWI0
+	default AVR_TWI0_ALT0
+	---help---
+		Select which I/O pins will be driven by TWI0 interface.
+		Refer to I/O Multiplexing and Port Multiplexer sections
+		in chip documentation for specifics.
+
+config AVR_TWI0_ALT0
+	bool "Default TWI0 pinout"
+
+config AVR_TWI0_ALT1
+	bool "Alternate TWI0 pinout 1"
+	depends on AVR_HAVE_TWI0_ALT1
+
+config AVR_TWI0_ALT2
+	bool "Alternate TWI0 pinout 2"
+
+endchoice
+
+choice AVR_TWI0_MODE
+	prompt "TWI0 mode selection"
+	depends on AVR_TWI0
+	default AVR_TWI0_MODE_STD
+	---help---
+		Select TWI0 operating mode.
+
+config AVR_TWI0_MODE_STD
+	bool "Standard mode"
+
+config AVR_TWI0_MODE_FAST
+	bool "Fast mode"
+
+config AVR_TWI0_MODE_FASTPLUS
+	bool "Fast plus mode"
+
+endchoice
+
+choice AVR_TWI0_SDAHOLD
+	prompt "SDA hold time selection"
+	depends on AVR_TWI0
+	default AVR_TWI0_SDAHOLD_OFF
+	---help---
+		Select TWI0 SDA hold time. Refer to Electrical Characteristics
+		in chip documentation for details
+
+config AVR_TWI0_SDAHOLD_OFF
+	bool "Hold time OFF"
+
+config AVR_TWI0_SDAHOLD_50NS
+	bool "50ns (short)"
+
+config AVR_TWI0_SDAHOLD_300NS
+	bool "300ns (meets SMBus 2.0 specs under typical conditions)"
+
+config AVR_TWI0_SDAHOLD_500NS
+	bool "500ns (meets SMBus 2.0 specs across all corners)"
+
+endchoice
+
+config AVR_TWI1
+	bool "Enable TWI (I2C) driver for interface 1"
+	depends on I2C
+	depends on AVR_HAVE_TWI1
+	---help---
+		Enable driver for TWI0
+
+choice AVR_TWI1_ALT
+	prompt "TWI0 pin selection"
+	depends on AVR_TWI1
+	default AVR_TWI1_ALT0
+	---help---
+		Select which I/O pins will be driven by TWI1 interface.
+		Refer to I/O Multiplexing and Port Multiplexer sections
+		in chip documentation for specifics.
+
+config AVR_TWI1_ALT0
+	bool "Default TWI1 pinout"
+
+config AVR_TWI1_ALT1
+	bool "Alternate TWI1 pinout 1"
+	depends on AVR_HAVE_TWI1_ALT1
+
+config AVR_TWI1_ALT2
+	bool "Alternate TWI1 pinout 2"
+
+endchoice
+
+choice AVR_TWI1_MODE
+	prompt "TWI1 mode selection"
+	depends on AVR_TWI1
+	default AVR_TWI1_MODE_STD
+	---help---
+		Select TWI1 operating mode.
+
+config AVR_TWI1_MODE_STD
+	bool "Standard mode"
+
+config AVR_TWI1_MODE_FAST
+	bool "Fast mode"
+
+config AVR_TWI1_MODE_FASTPLUS
+	bool "Fast plus mode"
+
+endchoice
+
+choice AVR_TWI1_SDAHOLD
+	prompt "SDA hold time selection"
+	depends on AVR_TWI1
+	default AVR_TWI1_SDAHOLD_OFF
+	---help---
+		Select TWI1 SDA hold time. Refer to Electrical Characteristics
+		in chip documentation for details.
+
+config AVR_TWI1_SDAHOLD_OFF
+	bool "Hold time OFF"
+
+config AVR_TWI1_SDAHOLD_50NS
+	bool "50ns (short)"
+
+config AVR_TWI1_SDAHOLD_300NS
+	bool "300ns (meets SMBus 2.0 specs under typical conditions)"
+
+config AVR_TWI1_SDAHOLD_500NS
+	bool "500ns (meets SMBus 2.0 specs across all corners)"
+
+endchoice
+
+if AVR_TWI0 || AVR_TWI1
+
+config AVR_TWI_QCEN
+	bool "Quick command enabled"
+	default false
+	---help---
+		Enable Quick Command mode. In this mode, messages with
+		zero-length data are interpreted as SMBus quick commands
+		which use R/non-W bit as a single bit of data transmitted
+		(written) to the target device.
+
+		If not enabled, attempt to transmit message with zero-length
+		is an error rejected with EINVAL.
+
+config AVR_TWI_FORBID_NOSTART
+	bool "Forbid I2C NOSTART to save flash space"
+	default false
+	---help---
+		NuttX I2C message can be submitted with a flag that indicates
+		that the caller does want that message processed without
+		issuing start condition on the BUS (presumably with previous
+		message set to not issue STOP nor REPEATED START condition.)
+
+		Since not many drivers require this, it is possible to exclude
+		support for this flag from the build. Any I2C device driver
+		that attempt to submit such message will receive EINVAL.
+
+		If you know that your system's drivers do not use I2C_M_NOSTART,
+		you can enable this option to save around 120 bytes of flash space.
+
+endif
+
 endmenu # AVR DA/DB Peripheral Selections
 
 choice

arch/avr/src/avrdx/Make.defs

@@ -54,6 +54,7 @@ CHIP_ASRCS = avrdx_exceptions.S
 CHIP_CSRCS = avrdx_lowconsole.c avrdx_lowinit.c avrdx_init.c
 CHIP_CSRCS += avrdx_serial.c avrdx_serial_early.c
 CHIP_CSRCS += avrdx_peripherals.c
+CHIP_CSRCS += avrdx_twi.c
 
 # Configuration-dependent files
 

arch/avr/src/avrdx/avrdx_lowconsole.c

@@ -65,7 +65,7 @@
 #ifdef CONFIG_MCU_SERIAL
 static const IOBJ uint32_t avrdx_usart_baud[] =
 {
-#  ifdef CONFIG_AVR_HAS_USART_2
+#  ifdef CONFIG_AVR_HAVE_USART_2
 
 #    if defined(CONFIG_USART0_SERIALDRIVER)
   CONFIG_USART0_BAUD,
@@ -85,9 +85,9 @@ static const IOBJ uint32_t avrdx_usart_baud[] =
   0
 #    endif
 
-  #  endif /* ifdef CONFIG_AVR_HAS_USART_2 */
+  #  endif /* ifdef CONFIG_AVR_HAVE_USART_2 */
 
-#  ifdef CONFIG_AVR_HAS_USART_4
+#  ifdef CONFIG_AVR_HAVE_USART_4
 #    if defined(CONFIG_USART3_SERIALDRIVER)
   , CONFIG_USART3_BAUD
 #    else
@@ -98,15 +98,15 @@ static const IOBJ uint32_t avrdx_usart_baud[] =
 #    else
   , 0
 #    endif
-#  endif /* ifdef CONFIG_AVR_HAS_USART_4 */
+#  endif /* ifdef CONFIG_AVR_HAVE_USART_4 */
 
-#  ifdef CONFIG_AVR_HAS_USART_5
+#  ifdef CONFIG_AVR_HAVE_USART_5
 #    if defined(CONFIG_USART5_SERIALDRIVER)
   , CONFIG_USART5_BAUD
 #    else
   , 0
 #    endif
-#  endif /* ifdef CONFIG_AVR_HAS_USART_5 */
+#  endif /* ifdef CONFIG_AVR_HAVE_USART_5 */
 };
 
 /* Peripheral settings for USARTn.CTRLC. Combined from multiple Kconfig
@@ -115,7 +115,7 @@ static const IOBJ uint32_t avrdx_usart_baud[] =
 
 static const IOBJ uint8_t avrdx_usart_ctrlc[] =
 {
-#  ifdef CONFIG_AVR_HAS_USART_2
+#  ifdef CONFIG_AVR_HAVE_USART_2
 
   /* USART0 */
 
@@ -219,11 +219,11 @@ static const IOBJ uint8_t avrdx_usart_ctrlc[] =
   0
 #    endif /* if defined(CONFIG_USART2_SERIALDRIVER) */
 
-#  endif /* ifdef CONFIG_AVR_HAS_USART_2 */
+#  endif /* ifdef CONFIG_AVR_HAVE_USART_2 */
 
   /* Definitions for chips that have USART4 */
 
-#  ifdef CONFIG_AVR_HAS_USART_4
+#  ifdef CONFIG_AVR_HAVE_USART_4
 
   /* USART3 */
 
@@ -293,11 +293,11 @@ static const IOBJ uint8_t avrdx_usart_ctrlc[] =
   , 0
 #    endif /* if defined(CONFIG_USART4_SERIALDRIVER) */
 
-#  endif /* ifdef CONFIG_AVR_HAS_USART_4 */
+#  endif /* ifdef CONFIG_AVR_HAVE_USART_4 */
 
   /* Definitions for chips that have USART5 */
 
-#  ifdef CONFIG_AVR_HAS_USART_5
+#  ifdef CONFIG_AVR_HAVE_USART_5
 
   /* USART5 */
 
@@ -333,7 +333,7 @@ static const IOBJ uint8_t avrdx_usart_ctrlc[] =
   , 0
 #    endif /* if defined(CONFIG_USART5_SERIALDRIVER) */
 
-#  endif /* ifdef CONFIG_AVR_HAS_USART_5 */
+#  endif /* ifdef CONFIG_AVR_HAVE_USART_5 */
 };
 
 #endif /* ifdef CONFIG_MCU_SERIAL */
@@ -406,6 +406,7 @@ void avrdx_usart_reset(struct avrdx_uart_priv_s *priv)
 
 void avrdx_usart_configure(struct avrdx_uart_priv_s *priv)
 {
+  volatile uint8_t *portmux_reg;
   irqstate_t irqstate;
   uint32_t baud_temp; /* Being calculated, needs 32 bits */
   uint32_t temp32;
@@ -471,7 +472,33 @@ void avrdx_usart_configure(struct avrdx_uart_priv_s *priv)
 
   usart->CTRLC = avrdx_usart_ctrlc[priv->usart_n];
 
-  /* 3. configure TXD pin as output */
+  /* 3. configure port multiplexer and set TXD pin as output */
+
+#  ifdef PORTMUX_USARTROUTEB
+  if (priv->usart_n < 4)
+#  endif
+    {
+      portmux_reg = &(PORTMUX.USARTROUTEA);
+    }
+#  ifdef PORTMUX_USARTROUTEB
+  else
+    {
+      portmux_reg = &(PORTMUX.USARTROUTEB);
+    }
+#  endif
+
+  /* In theory, only the kernel should manipulate this register
+   * and the value written is static (chosen by configuration.)
+   * That means there should be no need to reset it. Still doing it,
+   * runaway application may do accidental writes.
+   */
+
+  *(portmux_reg) = \
+    (\
+      *(portmux_reg) & \
+      ~(avrdx_usart_portmux_masks[priv->usart_n]) \
+    ) | \
+    avrdx_usart_portmux_bits[priv->usart_n];
 
   AVRDX_USART_PORT(priv->usart_n).DIRSET = \
     avrdx_usart_tx_pins[priv->usart_n];

arch/avr/src/avrdx/avrdx_peripherals.c

@@ -78,16 +78,16 @@ static const IOBJ uint8_t avrdx_main_pdiv[] = \
 
 const IOBJ uint8_t avrdx_usart_ports[] =
 {
-#  ifdef CONFIG_AVR_HAS_USART_2
+#  ifdef CONFIG_AVR_HAVE_USART_2
   AVRDX_GPIO_PORTA_IDX,   /* A, C, F */
   AVRDX_GPIO_PORTC_IDX,
   AVRDX_GPIO_PORTF_IDX
 #  endif
-#  ifdef CONFIG_AVR_HAS_USART_4
+#  ifdef CONFIG_AVR_HAVE_USART_4
   , AVRDX_GPIO_PORTB_IDX  /* B, E */
   , AVRDX_GPIO_PORTE_IDX
 #  endif
-#  ifdef CONFIG_AVR_HAS_USART_5
+#  ifdef CONFIG_AVR_HAVE_USART_5
   , AVRDX_GPIO_PORTG_IDX  /* port G */
 #  endif
 };
@@ -100,7 +100,7 @@ const IOBJ uint8_t avrdx_usart_ports[] =
 
 const IOBJ uint8_t avrdx_usart_tx_pins[] =
 {
-#  ifdef CONFIG_AVR_HAS_USART_2
+#  ifdef CONFIG_AVR_HAVE_USART_2
 #    if !defined(CONFIG_AVR_USART0_ALT)
   PIN0_bm ,
 #    else
@@ -118,7 +118,7 @@ const IOBJ uint8_t avrdx_usart_tx_pins[] =
 #    endif
 #  endif
 
-#  ifdef CONFIG_AVR_HAS_USART_4
+#  ifdef CONFIG_AVR_HAVE_USART_4
 #    if !defined(CONFIG_AVR_USART3_ALT)
   , PIN0_bm
 #    else
@@ -131,7 +131,7 @@ const IOBJ uint8_t avrdx_usart_tx_pins[] =
 #    endif
 #  endif
 
-#  ifdef CONFIG_AVR_HAS_USART_5
+#  ifdef CONFIG_AVR_HAVE_USART_5
 #    if !defined(CONFIG_AVR_USART5_ALT)
   , PIN0_bm
 #    else
@@ -175,6 +175,127 @@ const IOBJ uint8_t avrdx_gpio_irq_vectors[] =
 #endif
 };
 
+/* This array holds bits to be set in PORTMUX.USARTROUTEx registers
+ * depending on if the alternate pin position was configured.
+ * (Index is port index.)
+ */
+
+const IOBJ uint8_t avrdx_usart_portmux_bits[] =
+{
+#  ifdef CONFIG_AVR_HAVE_USART_2
+
+#    ifdef CONFIG_AVR_USART0
+#      if defined(CONFIG_AVR_USART0_DEFAULT)
+  PORTMUX_USART0_DEFAULT_GC,
+#      elif defined(CONFIG_AVR_USART0_ALT)
+  PORTMUX_USART0_ALT1_GC,
+#      elif defined(CONFIG_AVR_USART0_NONE)
+  PORTMUX_USART0_NONE_GC,
+#      else
+#        error Kconfig error, no option is set
+#      endif
+#    else /* AVR_USART0 not active, value will not be used */
+  PORTMUX_USART0_DEFAULT_GC,
+#    endif
+
+#    ifdef CONFIG_AVR_USART1
+#      if defined(CONFIG_AVR_USART1_DEFAULT)
+  PORTMUX_USART1_DEFAULT_GC,
+#      elif defined(CONFIG_AVR_USART1_ALT)
+  PORTMUX_USART1_ALT1_GC,
+#      elif defined(CONFIG_AVR_USART1_NONE)
+  PORTMUX_USART1_NONE_GC,
+#      else
+#        error Kconfig error, no option is set
+#      endif
+#    else /* AVR_USART1 not active, value will not be used */
+  PORTMUX_USART1_DEFAULT_GC,
+#    endif
+
+#    ifdef CONFIG_AVR_USART2
+#      if defined(CONFIG_AVR_USART2_DEFAULT)
+  PORTMUX_USART2_DEFAULT_GC
+#      elif defined(CONFIG_AVR_USART2_ALT)
+  PORTMUX_USART2_ALT1_GC
+#      elif defined(CONFIG_AVR_USART2_NONE)
+  PORTMUX_USART2_NONE_GC
+#      else
+#        error Kconfig error, no option is set
+#      endif
+#    else /* AVR_USART2 not active, value will not be used */
+  PORTMUX_USART2_DEFAULT_GC
+#    endif
+
+#  endif /* ifdef CONFIG_AVR_HAVE_USART_2 */
+
+#  ifdef CONFIG_AVR_HAVE_USART_4
+
+#    ifdef CONFIG_AVR_USART3
+#      if defined(CONFIG_AVR_USART3_DEFAULT)
+  , PORTMUX_USART3_DEFAULT_GC
+#      elif defined(CONFIG_AVR_USART3_ALT)
+  , PORTMUX_USART3_ALT1_GC
+#      elif defined(CONFIG_AVR_USART3_NONE)
+  , PORTMUX_USART3_NONE_GC
+#      else
+#        error Kconfig error, no option is set
+#      endif
+#    else /* AVR_USART3 not active, value will not be used */
+  , PORTMUX_USART3_DEFAULT_GC
+#    endif
+
+#    ifdef CONFIG_AVR_USART4
+#      if defined(CONFIG_AVR_USART4_DEFAULT)
+  , PORTMUX_USART4_DEFAULT_GC
+#      elif defined(CONFIG_AVR_USART4_ALT)
+  , PORTMUX_USART4_ALT1_GC
+#      elif defined(CONFIG_AVR_USART4_NONE)
+  , PORTMUX_USART4_NONE_GC
+#      else
+#        error Kconfig error, no option is set
+#      endif
+#    else /* AVR_USART4 not active, value will not be used */
+  , PORTMUX_USART4_DEFAULT_GC
+#    endif
+
+#  endif /* ifdef CONFIG_AVR_HAVE_USART_4 */
+
+#  ifdef CONFIG_AVR_HAVE_USART_5
+
+#    ifdef CONFIG_AVR_USART5
+#      if defined(CONFIG_AVR_USART5_DEFAULT)
+  , PORTMUX_USART5_DEFAULT_GC
+#      elif defined(CONFIG_AVR_USART5_ALT)
+  , PORTMUX_USART5_ALT1_GC
+#      elif defined(CONFIG_AVR_USART5_NONE)
+  , PORTMUX_USART5_NONE_GC
+#      else
+#        error Kconfig error, no option is set
+#      endif
+#    else /* AVR_USART5 not active, value will not be used */
+  , PORTMUX_USART5_DEFAULT_GC
+#    endif
+
+#  endif /* ifdef CONFIG_AVR_HAVE_USART_5 */
+};
+
+/* This array holds masks for bits affecting specific USART
+ * peripheral in PORTMUX.USARTROUTEx registers. (Index is port index.)
+ */
+
+const IOBJ uint8_t avrdx_usart_portmux_masks[] =
+{
+#  ifdef CONFIG_AVR_HAVE_USART_2
+  PORTMUX_USART0_GM, PORTMUX_USART1_GM, PORTMUX_USART2_GM
+#  endif
+#  ifdef CONFIG_AVR_HAVE_USART_4
+  , PORTMUX_USART3_GM, PORTMUX_USART4_GM
+#  endif
+#  ifdef CONFIG_AVR_HAVE_USART_5
+  , PORTMUX_USART5_GM
+#  endif
+};
+
 /****************************************************************************
  * Private Functions
  ****************************************************************************/

arch/avr/src/avrdx/avrdx_serial.c

@@ -156,13 +156,13 @@ static bool avrdx_usart_txempty(struct uart_dev_s *dev);
 
 static const IOBJ uint8_t avrdx_usart_rx_interrupts[] =
 {
-#  ifdef CONFIG_AVR_HAS_USART_2
+#  ifdef CONFIG_AVR_HAVE_USART_2
   AVRDX_IRQ_USART0_RXC, AVRDX_IRQ_USART1_RXC, AVRDX_IRQ_USART2_RXC
 #  endif
-#  ifdef CONFIG_AVR_HAS_USART_4
+#  ifdef CONFIG_AVR_HAVE_USART_4
   , AVRDX_IRQ_USART3_RXC, AVRDX_IRQ_USART4_RXC
 #  endif
-#  ifdef CONFIG_AVR_HAS_USART_5
+#  ifdef CONFIG_AVR_HAVE_USART_5
   , AVRDX_IRQ_USART5_RXC
 #  endif
 };
@@ -171,13 +171,13 @@ static const IOBJ uint8_t avrdx_usart_rx_interrupts[] =
 
 static const IOBJ uint8_t avrdx_usart_dre_interrupts[] =
 {
-#  ifdef CONFIG_AVR_HAS_USART_2
+#  ifdef CONFIG_AVR_HAVE_USART_2
   AVRDX_IRQ_USART0_DRE, AVRDX_IRQ_USART1_DRE, AVRDX_IRQ_USART2_DRE
 #  endif
-#  ifdef CONFIG_AVR_HAS_USART_4
+#  ifdef CONFIG_AVR_HAVE_USART_4
   , AVRDX_IRQ_USART3_DRE, AVRDX_IRQ_USART4_DRE
 #  endif
-#  ifdef CONFIG_AVR_HAS_USART_5
+#  ifdef CONFIG_AVR_HAVE_USART_5
   , AVRDX_IRQ_USART5_DRE
 #  endif
 };
@@ -221,11 +221,11 @@ static const struct uart_ops_s g_usart_ops =
  */
 
 #  ifdef CONFIG_MCU_SERIAL
-#    if defined(CONFIG_AVR_HAS_USART_5)
+#    if defined(CONFIG_AVR_HAVE_USART_5)
 static uart_dev_t *g_usart_ports[6];
-#    elif defined(CONFIG_AVR_HAS_USART_4)
+#    elif defined(CONFIG_AVR_HAVE_USART_4)
 static uart_dev_t *g_usart_ports[5];
-#    elif defined(CONFIG_AVR_HAS_USART_2)
+#    elif defined(CONFIG_AVR_HAVE_USART_2)
 static uart_dev_t *g_usart_ports[3];
 #    endif
 #  endif

arch/avr/src/avrdx/avrdx_serial.h

@@ -89,6 +89,8 @@ extern "C"
 
 EXTERN const IOBJ uint8_t avrdx_usart_ports[];
 EXTERN const IOBJ uint8_t avrdx_usart_tx_pins[];
+EXTERN const IOBJ uint8_t avrdx_usart_portmux_bits[];
+EXTERN const IOBJ uint8_t avrdx_usart_portmux_masks[];
 
 #endif
 

arch/avr/src/avrdx/avrdx_twi.h

@@ -0,0 +1,94 @@
+/****************************************************************************
+ * arch/avr/src/avrdx/avrdx_twi.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_AVR_SRC_AVRDX_AVRDX_TWI_H
+#define __ARCH_AVR_SRC_AVRDX_AVRDX_TWI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "avrdx_iodefs.h"
+#include <nuttx/i2c/i2c_master.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Base address of TWIn peripheral. TWI index corresponds to the location
+ * of its I/O registers in memory. Ignores its parameter if the chip
+ * only has one TWI.
+ */
+
+#ifdef CONFIG_AVR_HAVE_TWI1
+#  define AVRDX_TWI(n) (*(avr_twi_t *) (0x0900 + n * 0x20))
+#else
+#  define AVRDX_TWI(n) (*(avr_twi_t *) (0x0900 + 0 * 0x20))
+#endif
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: avrdx_initialize_twi
+ *
+ * Description:
+ *   Initializer for TWI device. Allocates data structures and configures
+ *   the peripheral. May be called multiple times by multiple drivers using
+ *   the bus.
+ *
+ * Input Parameters:
+ *   Peripheral number, ignored if the chip only has single TWI
+ *
+ * Returned Value:
+ *   Initialized structure cast to i2c_master_s
+ *
+ ****************************************************************************/
+
+FAR struct i2c_master_s *avrdx_initialize_twi(uint8_t twi_n);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_AVR_SRC_AVRDX_AVRDX_TWI_H */

arch/avr/src/avrdx/iodefs/avr128da28.h

@@ -37,6 +37,27 @@
 #  error "Do not include this file directly, use avrdx_iodefs.h instead"
 #endif
 
+/* PORTMUX.USARTROUTEA */
+
+#define PORTMUX_USART0_DEFAULT_GC (0)
+#define PORTMUX_USART0_ALT1_GC (PORTMUX_USART0_0_bm )
+#define PORTMUX_USART0_NONE_GC (PORTMUX_USART0_1_bm | PORTMUX_USART0_0_bm)
+#define PORTMUX_USART0_GM (PORTMUX_USART0_1_bm | PORTMUX_USART0_0_bm)
+
+#define PORTMUX_USART1_DEFAULT_GC (0)
+#define PORTMUX_USART1_NONE_GC (PORTMUX_USART1_1_bm | PORTMUX_USART1_0_bm)
+#define PORTMUX_USART1_GM (PORTMUX_USART1_1_bm | PORTMUX_USART1_0_bm)
+
+#define PORTMUX_USART2_DEFAULT_GC (0)
+#define PORTMUX_USART2_NONE_GC (PORTMUX_USART2_1_bm | PORTMUX_USART2_0_bm)
+#define PORTMUX_USART2_GM (PORTMUX_USART2_1_bm | PORTMUX_USART2_0_bm)
+
+/* PORTMUX.TWIROUTEA */
+
+#define PORTMUX_TWI0_DEFAULT_GC (0)
+#define PORTMUX_TWI0_ALT2_GC = (PORTMUX_TWI0_1_bm)
+#define PORTMUX_TWI0_GM (PORTMUX_TWI0_1_bm | PORTMUX_TWI0_0_bm)
+
 /* PORT.PINCONFIG */
 
 #define PORT_ISC_GM ( PORT_ISC_0_bm | PORT_ISC_1_bm | PORT_ISC_2_bm )
@@ -90,6 +111,35 @@
 #define USART_CHSIZE_7BIT_GC (USART_CHSIZE_1_bm)
 #define USART_CHSIZE_8BIT_GC (USART_CHSIZE_1_bm | USART_CHSIZE_0_bm)
 
+/* TWI.MCTRLA */
+
+#define TWI_FMPEN_ON_GC (TWI_FMPEN_bm)
+
+#define TWI_SDAHOLD_OFF_GC (0)
+#define TWI_SDAHOLD_50NS_GC (TWI_SDAHOLD_0_bm)
+#define TWI_SDAHOLD_300NS_GC (TWI_SDAHOLD_1_bm)
+#define TWI_SDAHOLD_500NS_GC (TWI_SDAHOLD_1_bm | TWI_SDAHOLD_0_bm)
+
+#define TWI_TIMEOUT_200US_GC (TWI_TIMEOUT_1_bm | TWI_TIMEOUT_0_bm)
+
+/* TWI.MCTRLB */
+
+#define TWI_MCMD_NOACT_GC (0)
+#define TWI_MCMD_REPSTART_GC (TWI_MCMD_0_bm)
+#define TWI_MCMD_RECVTRANS_GC (TWI_MCMD_1_bm)
+#define TWI_MCMD_STOP_GC (TWI_MCMD_0_bm | TWI_MCMD_1_bm)
+
+#define TWI_ACKACT_ACK_GC (0)
+#define TWI_ACKACT_NACK_GC (TWI_ACKACT_bm)
+
+/* TWI.MSTATUS */
+
+#define TWI_BUSSTATE_UNKNOWN_GC (0)
+#define TWI_BUSSTATE_IDLE_GC (TWI_BUSSTATE_0_bm)
+#define TWI_BUSSTATE_OWNER_GC (TWI_BUSSTATE_1_bm)
+#define TWI_BUSSTATE_BUSY_GC (TWI_BUSSTATE_1_bm | TWI_BUSSTATE_0_bm)
+#define TWI_BUSSTATE_GM (TWI_BUSSTATE_1_bm | TWI_BUSSTATE_0_bm)
+
 /****************************************************************************
  * Public Types
  ****************************************************************************/
@@ -115,6 +165,26 @@ typedef struct avr_usart_struct
   register8_t reserved_1[1];
 } avr_usart_t;
 
+typedef struct avr_twi_struct
+{
+  register8_t CTRLA;     /* Control A */
+  register8_t DUALCTRL;  /* Dual Control */
+  register8_t DBGCTRL;   /* Debug Control Register */
+  register8_t MCTRLA;    /* Host Control A */
+  register8_t MCTRLB;    /* Host Control B */
+  register8_t MSTATUS;   /* Host Status */
+  register8_t MBAUD;     /* Host Baud Rate Control */
+  register8_t MADDR;     /* Host Address */
+  register8_t MDATA;     /* Host Data */
+  register8_t SCTRLA;    /* Client Control A */
+  register8_t SCTRLB;    /* Client Control B */
+  register8_t SSTATUS;   /* Client Status */
+  register8_t SADDR;     /* Client Address */
+  register8_t SDATA;     /* Client Data */
+  register8_t SADDRMASK; /* Client Address Mask */
+  register8_t reserved_1[1];
+} avr_twi_t;
+
 /****************************************************************************
  * Public Data
  ****************************************************************************/

arch/avr/src/avrdx/iodefs/avr128da64.h

@@ -37,6 +37,52 @@
 #  error "Do not include this file directly, use avrdx_iodefs.h instead"
 #endif
 
+/* PORTMUX.USARTROUTEA */
+
+#define PORTMUX_USART0_DEFAULT_GC (0)
+#define PORTMUX_USART0_ALT1_GC (PORTMUX_USART0_0_bm )
+#define PORTMUX_USART0_NONE_GC (PORTMUX_USART0_1_bm | PORTMUX_USART0_0_bm)
+#define PORTMUX_USART0_GM (PORTMUX_USART0_1_bm | PORTMUX_USART0_0_bm)
+
+#define PORTMUX_USART1_DEFAULT_GC (0)
+#define PORTMUX_USART1_ALT1_GC (PORTMUX_USART1_0_bm)
+#define PORTMUX_USART1_NONE_GC (PORTMUX_USART1_1_bm | PORTMUX_USART1_0_bm)
+#define PORTMUX_USART1_GM (PORTMUX_USART1_1_bm | PORTMUX_USART1_0_bm)
+
+#define PORTMUX_USART2_DEFAULT_GC (0)
+#define PORTMUX_USART2_ALT1_gc (PORTMUX_USART2_0_bm)
+#define PORTMUX_USART2_NONE_GC (PORTMUX_USART2_1_bm | PORTMUX_USART2_0_bm)
+#define PORTMUX_USART2_GM (PORTMUX_USART2_1_bm | PORTMUX_USART2_0_bm)
+
+#define PORTMUX_USART3_DEFAULT_GC (0)
+#define PORTMUX_USART3_ALT1_GC (PORTMUX_USART3_0_bm)
+#define PORTMUX_USART3_NONE_GC (PORTMUX_USART3_1_bm | PORTMUX_USART3_0_bm)
+#define PORTMUX_USART3_GM (PORTMUX_USART3_1_bm | PORTMUX_USART3_0_bm)
+
+/* PORTMUX.USARTROUTEB */
+
+#define PORTMUX_USART4_DEFAULT_GC (0)
+#define PORTMUX_USART4_ALT1_GC (PORTMUX_USART4_0_bm)
+#define PORTMUX_USART4_NONE_GC (PORTMUX_USART4_1_bm | PORTMUX_USART4_0_bm)
+#define PORTMUX_USART4_GM (PORTMUX_USART4_1_bm | PORTMUX_USART4_0_bm)
+
+#define PORTMUX_USART5_DEFAULT_GC (0)
+#define PORTMUX_USART5_ALT1_GC (PORTMUX_USART5_0_bm)
+#define PORTMUX_USART5_NONE_GC (PORTMUX_USART5_1_bm | PORTMUX_USART5_0_bm)
+#define PORTMUX_USART5_GM (PORTMUX_USART5_1_bm | PORTMUX_USART5_0_bm)
+
+/* PORTMUX.TWIROUTEA */
+
+#define PORTMUX_TWI0_DEFAULT_GC (0)
+#define PORTMUX_TWI0_ALT1_GC = (PORTMUX_TWI0_0_bm)
+#define PORTMUX_TWI0_ALT2_GC = (PORTMUX_TWI0_1_bm)
+#define PORTMUX_TWI0_GM (PORTMUX_TWI0_1_bm | PORTMUX_TWI0_0_bm)
+
+#define PORTMUX_TWI1_DEFAULT_GC (0)
+#define PORTMUX_TWI1_ALT1_GC = (PORTMUX_TWI1_0_bm)
+#define PORTMUX_TWI1_ALT2_GC = (PORTMUX_TWI1_1_bm)
+#define PORTMUX_TWI1_GM (PORTMUX_TWI1_1_bm | PORTMUX_TWI1_0_bm)
+
 /* PORT.PINCONFIG */
 
 #define PORT_ISC_GM ( PORT_ISC_0_bm | PORT_ISC_1_bm | PORT_ISC_2_bm )
@@ -90,6 +136,35 @@
 #define USART_CHSIZE_7BIT_GC (USART_CHSIZE_1_bm)
 #define USART_CHSIZE_8BIT_GC (USART_CHSIZE_1_bm | USART_CHSIZE_0_bm)
 
+/* TWI.MCTRLA */
+
+#define TWI_FMPEN_ON_GC (TWI_FMPEN_bm)
+
+#define TWI_SDAHOLD_OFF_GC (0)
+#define TWI_SDAHOLD_50NS_GC (TWI_SDAHOLD_0_bm)
+#define TWI_SDAHOLD_300NS_GC (TWI_SDAHOLD_1_bm)
+#define TWI_SDAHOLD_500NS_GC (TWI_SDAHOLD_1_bm | TWI_SDAHOLD_0_bm)
+
+#define TWI_TIMEOUT_200US_GC (TWI_TIMEOUT_1_bm | TWI_TIMEOUT_0_bm)
+
+/* TWI.MCTRLB */
+
+#define TWI_MCMD_NOACT_GC (0)
+#define TWI_MCMD_REPSTART_GC (TWI_MCMD_0_bm)
+#define TWI_MCMD_RECVTRANS_GC (TWI_MCMD_1_bm)
+#define TWI_MCMD_STOP_GC (TWI_MCMD_0_bm | TWI_MCMD_1_bm)
+
+#define TWI_ACKACT_ACK_GC (0)
+#define TWI_ACKACT_NACK_GC (TWI_ACKACT_bm)
+
+/* TWI.MSTATUS */
+
+#define TWI_BUSSTATE_UNKNOWN_GC (0)
+#define TWI_BUSSTATE_IDLE_GC (TWI_BUSSTATE_0_bm)
+#define TWI_BUSSTATE_OWNER_GC (TWI_BUSSTATE_1_bm)
+#define TWI_BUSSTATE_BUSY_GC (TWI_BUSSTATE_1_bm | TWI_BUSSTATE_0_bm)
+#define TWI_BUSSTATE_GM (TWI_BUSSTATE_1_bm | TWI_BUSSTATE_0_bm)
+
 /****************************************************************************
  * Public Types
  ****************************************************************************/
@@ -115,6 +190,26 @@ typedef struct avr_usart_struct
   register8_t reserved_1[1];
 } avr_usart_t;
 
+typedef struct avr_twi_struct
+{
+  register8_t CTRLA;     /* Control A */
+  register8_t DUALCTRL;  /* Dual Control */
+  register8_t DBGCTRL;   /* Debug Control Register */
+  register8_t MCTRLA;    /* Host Control A */
+  register8_t MCTRLB;    /* Host Control B */
+  register8_t MSTATUS;   /* Host Status */
+  register8_t MBAUD;     /* Host Baud Rate Control */
+  register8_t MADDR;     /* Host Address */
+  register8_t MDATA;     /* Host Data */
+  register8_t SCTRLA;    /* Client Control A */
+  register8_t SCTRLB;    /* Client Control B */
+  register8_t SSTATUS;   /* Client Status */
+  register8_t SADDR;     /* Client Address */
+  register8_t SDATA;     /* Client Data */
+  register8_t SADDRMASK; /* Client Address Mask */
+  register8_t reserved_1[1];
+} avr_twi_t;
+
 /****************************************************************************
  * Public Data
  ****************************************************************************/

arch/avr/src/avrdx/iodefs/avr128db64.h

@@ -37,6 +37,52 @@
 #  error "Do not include this file directly, use avrdx_iodefs.h instead"
 #endif
 
+/* PORTMUX.USARTROUTEA */
+
+#define PORTMUX_USART0_DEFAULT_GC (0)
+#define PORTMUX_USART0_ALT1_GC (PORTMUX_USART0_0_bm )
+#define PORTMUX_USART0_NONE_GC (PORTMUX_USART0_1_bm | PORTMUX_USART0_0_bm)
+#define PORTMUX_USART0_GM (PORTMUX_USART0_1_bm | PORTMUX_USART0_0_bm)
+
+#define PORTMUX_USART1_DEFAULT_GC (0)
+#define PORTMUX_USART1_ALT1_GC (PORTMUX_USART1_0_bm)
+#define PORTMUX_USART1_NONE_GC (PORTMUX_USART1_1_bm | PORTMUX_USART1_0_bm)
+#define PORTMUX_USART1_GM (PORTMUX_USART1_1_bm | PORTMUX_USART1_0_bm)
+
+#define PORTMUX_USART2_DEFAULT_GC (0)
+#define PORTMUX_USART2_ALT1_gc (PORTMUX_USART2_0_bm)
+#define PORTMUX_USART2_NONE_GC (PORTMUX_USART2_1_bm | PORTMUX_USART2_0_bm)
+#define PORTMUX_USART2_GM (PORTMUX_USART2_1_bm | PORTMUX_USART2_0_bm)
+
+#define PORTMUX_USART3_DEFAULT_GC (0)
+#define PORTMUX_USART3_ALT1_GC (PORTMUX_USART3_0_bm)
+#define PORTMUX_USART3_NONE_GC (PORTMUX_USART3_1_bm | PORTMUX_USART3_0_bm)
+#define PORTMUX_USART3_GM (PORTMUX_USART3_1_bm | PORTMUX_USART3_0_bm)
+
+/* PORTMUX.USARTROUTEB */
+
+#define PORTMUX_USART4_DEFAULT_GC (0)
+#define PORTMUX_USART4_ALT1_GC (PORTMUX_USART4_0_bm)
+#define PORTMUX_USART4_NONE_GC (PORTMUX_USART4_1_bm | PORTMUX_USART4_0_bm)
+#define PORTMUX_USART4_GM (PORTMUX_USART4_1_bm | PORTMUX_USART4_0_bm)
+
+#define PORTMUX_USART5_DEFAULT_GC (0)
+#define PORTMUX_USART5_ALT1_GC (PORTMUX_USART5_0_bm)
+#define PORTMUX_USART5_NONE_GC (PORTMUX_USART5_1_bm | PORTMUX_USART5_0_bm)
+#define PORTMUX_USART5_GM (PORTMUX_USART5_1_bm | PORTMUX_USART5_0_bm)
+
+/* PORTMUX.TWIROUTEA */
+
+#define PORTMUX_TWI0_DEFAULT_GC (0)
+#define PORTMUX_TWI0_ALT1_GC = (PORTMUX_TWI0_0_bm)
+#define PORTMUX_TWI0_ALT2_GC = (PORTMUX_TWI0_1_bm)
+#define PORTMUX_TWI0_GM (PORTMUX_TWI0_1_bm | PORTMUX_TWI0_0_bm)
+
+#define PORTMUX_TWI1_DEFAULT_GC (0)
+#define PORTMUX_TWI1_ALT1_GC = (PORTMUX_TWI1_0_bm)
+#define PORTMUX_TWI1_ALT2_GC = (PORTMUX_TWI1_1_bm)
+#define PORTMUX_TWI1_GM (PORTMUX_TWI1_1_bm | PORTMUX_TWI1_0_bm)
+
 /* PORT.PINCONFIG */
 
 #define PORT_ISC_GM ( PORT_ISC_0_bm | PORT_ISC_1_bm | PORT_ISC_2_bm )
@@ -90,6 +136,35 @@
 #define USART_CHSIZE_7BIT_GC (USART_CHSIZE_1_bm)
 #define USART_CHSIZE_8BIT_GC (USART_CHSIZE_1_bm | USART_CHSIZE_0_bm)
 
+/* TWI.MCTRLA */
+
+#define TWI_FMPEN_ON_GC (TWI_FMPEN_bm)
+
+#define TWI_SDAHOLD_OFF_GC (0)
+#define TWI_SDAHOLD_50NS_GC (TWI_SDAHOLD_0_bm)
+#define TWI_SDAHOLD_300NS_GC (TWI_SDAHOLD_1_bm)
+#define TWI_SDAHOLD_500NS_GC (TWI_SDAHOLD_1_bm | TWI_SDAHOLD_0_bm)
+
+#define TWI_TIMEOUT_200US_GC (TWI_TIMEOUT_1_bm | TWI_TIMEOUT_0_bm)
+
+/* TWI.MCTRLB */
+
+#define TWI_MCMD_NOACT_GC (0)
+#define TWI_MCMD_REPSTART_GC (TWI_MCMD_0_bm)
+#define TWI_MCMD_RECVTRANS_GC (TWI_MCMD_1_bm)
+#define TWI_MCMD_STOP_GC (TWI_MCMD_0_bm | TWI_MCMD_1_bm)
+
+#define TWI_ACKACT_ACK_GC (0)
+#define TWI_ACKACT_NACK_GC (TWI_ACKACT_bm)
+
+/* TWI.MSTATUS */
+
+#define TWI_BUSSTATE_UNKNOWN_GC (0)
+#define TWI_BUSSTATE_IDLE_GC (TWI_BUSSTATE_0_bm)
+#define TWI_BUSSTATE_OWNER_GC (TWI_BUSSTATE_1_bm)
+#define TWI_BUSSTATE_BUSY_GC (TWI_BUSSTATE_1_bm | TWI_BUSSTATE_0_bm)
+#define TWI_BUSSTATE_GM (TWI_BUSSTATE_1_bm | TWI_BUSSTATE_0_bm)
+
 /****************************************************************************
  * Public Types
  ****************************************************************************/
@@ -115,6 +190,26 @@ typedef struct avr_usart_struct
   register8_t reserved_1[1];
 } avr_usart_t;
 
+typedef struct avr_twi_struct
+{
+  register8_t CTRLA;     /* Control A */
+  register8_t DUALCTRL;  /* Dual Control */
+  register8_t DBGCTRL;   /* Debug Control Register */
+  register8_t MCTRLA;    /* Host Control A */
+  register8_t MCTRLB;    /* Host Control B */
+  register8_t MSTATUS;   /* Host Status */
+  register8_t MBAUD;     /* Host Baud Rate Control */
+  register8_t MADDR;     /* Host Address */
+  register8_t MDATA;     /* Host Data */
+  register8_t SCTRLA;    /* Client Control A */
+  register8_t SCTRLB;    /* Client Control B */
+  register8_t SSTATUS;   /* Client Status */
+  register8_t SADDR;     /* Client Address */
+  register8_t SDATA;     /* Client Data */
+  register8_t SADDRMASK; /* Client Address Mask */
+  register8_t reserved_1[1];
+} avr_twi_t;
+
 /****************************************************************************
  * Public Data
  ****************************************************************************/

arch/risc-v/src/mpfs/mpfs_ddr.c

@@ -3449,6 +3449,7 @@ static int mpfs_training_verify(void)
   if ((LIBERO_SETTING_TRAINING_SKIP_SETTING & ADDCMD_BIT) != ADDCMD_BIT)
     {
       unsigned low_ca_dly_count = 0;
+      unsigned decrease_count = 0;
       uint8_t ca_status[8] =
         {
           ((addcmd_status0) & 0xff),
@@ -3467,21 +3468,28 @@ static int mpfs_training_verify(void)
        * Expected result is increasing numbers, starting at index n and
        * wrapping around. For example:
        *   [0x35, 0x3b, 0x4, 0x14, 0x1b, 0x21, 0x28, 0x2f].
-       *
-       * Also they need to be separated by at least 5
        */
 
       for (i = 0; i < 8; i++)
         {
-          if (ca_status[i] < last + 5)
+          if (ca_status[i] < 5)
             {
               low_ca_dly_count++;
             }
 
+          if (ca_status[i] <= last)
+            {
+              decrease_count++;
+            }
+
           last = ca_status[i];
         }
 
-      if (low_ca_dly_count > 1)
+      /* Check against thresholds. Allow one low and one extra
+       * backwards jump, in addition to the wrap-around point
+       */
+
+      if (low_ca_dly_count > 1 || decrease_count > 2)
         {
           /* Retrain via reset */
 
@@ -3508,19 +3516,34 @@ static int mpfs_training_verify(void)
           t_status |= 0x01;
         }
 
-      /* Check that DQ/DQS calculated window is above 5 taps
-       * and centered with margin
-       */
-
       off_taps = getreg32(MPFS_CFG_DDR_SGMII_PHY_DQDQS_STATUS1);
       width_taps = getreg32(MPFS_CFG_DDR_SGMII_PHY_DQDQS_STATUS2);
 
-      if (width_taps < DQ_DQS_NUM_TAPS ||
-          width_taps + off_taps <= 16 + DQ_DQS_NUM_TAPS / 2)
+      /* Check that DQ/DQS calculated window is above 5 taps */
+
+      if (width_taps < DQ_DQS_NUM_TAPS) /* eye is long enough */
         {
           t_status |= 0x01;
         }
 
+      /* Check that DQ/DQS calculated window is centered; starts
+       * at > 2 taps left and ends at > 2 taps right from
+       * the center
+       */
+
+      if (width_taps + off_taps <= 16 + DQ_DQS_NUM_TAPS / 2 ||
+          off_taps >= 16 - DQ_DQS_NUM_TAPS / 2)
+        {
+          t_status |= 0x01;
+        }
+
+      /* Check that the calculated window ends within the 32-taps */
+
+      if (off_taps + width_taps > 32)
+        {
+           t_status |= 0x01;
+        }
+
       /* Extra checks */
 
       /* Check the GT_TXDLY result for the selected clock */

arch/tricore/src/common/tricore_systimer.c

@@ -49,6 +49,8 @@
  * 40 CPU cycles (100ns at 400Mhz) ~ 10 timer cycles (for 100 Mhz timer).
  */
 
+#define IFX_CFG_CPU_CLOCK_FREQUENCY 100000000
+
 #define TRICORE_SYSTIMER_MIN_DELAY \
   (40ull * SCU_FREQUENCY / IFX_CFG_CPU_CLOCK_FREQUENCY)
 
@@ -65,6 +67,7 @@ struct tricore_systimer_lowerhalf_s
 {
   struct oneshot_lowerhalf_s lower;
   volatile void             *tbase;
+  spinlock_t                lock;
 };
 
 /****************************************************************************

arch/x86_64/src/intel64/intel64_cpu.c

@@ -366,14 +366,7 @@ bool x86_64_cpu_ready_get(uint8_t cpu)
 
 uint8_t x86_64_cpu_count_get(void)
 {
-  irqstate_t flags;
-  uint8_t count;
-
-  flags = spin_lock_irqsave(&g_ap_boot);
-  count = g_cpu_count;
-  spin_unlock_irqrestore(&g_ap_boot, flags);
-
-  return count;
+  return g_cpu_count;
 }
 
 /****************************************************************************
@@ -425,10 +418,4 @@ void x86_64_cpu_priv_set(uint8_t cpu)
 
   write_msr(MSR_FMASK, X86_64_RFLAGS_IF | X86_64_RFLAGS_DF);
 #endif
-
-#ifdef CONFIG_SMP
-  /* Attach TLB shootdown handler */
-
-  irq_attach(SMP_IPI_TLBSHOOTDOWN_IRQ, x86_64_tlb_handler, NULL);
-#endif
 }

arch/x86_64/src/intel64/intel64_cpustart.c

@@ -154,6 +154,7 @@ void x86_64_ap_boot(void)
 
   tcb = current_task(cpu);
   UNUSED(tcb);
+  up_update_task(tcb);
 
 #ifdef CONFIG_SCHED_THREAD_LOCAL
   /* Make sure that FS_BASE is not null */
@@ -212,8 +213,6 @@ void x86_64_ap_boot(void)
   x86_64_hwdebug_init();
 #endif
 
-  up_update_task(tcb);
-
   /* Then transfer control to the IDLE task */
 
   nx_idle_trampoline();

arch/x86_64/src/intel64/intel64_irq.c

@@ -544,6 +544,12 @@ void up_irqinitialize(void)
   irq_attach(ISR13, x86_64_fault_panic_isr, NULL);
   irq_attach(ISR14, x86_64_fault_panic_isr, NULL);
   irq_attach(ISR16, x86_64_fault_kill_isr, NULL);
+
+#ifdef CONFIG_SMP
+  /* Attach TLB shootdown handler */
+
+  irq_attach(SMP_IPI_TLBSHOOTDOWN_IRQ, x86_64_tlb_handler, NULL);
+#endif
 }
 
 /****************************************************************************

arch/xtensa/src/common/espressif/Kconfig

@@ -398,6 +398,478 @@ config ESPRESSIF_USE_ULP_RISCV_CORE
 
 endmenu # LP Core (Low-power core) Coprocessor Configuration
 
+menu "PM Configuration"
+
+if PM && !ARCH_CHIP_ESP32
+
+config PM_EXT1_WAKEUP
+	bool "PM EXT1 Wakeup"
+	default n
+	---help---
+		Enable EXT1 wakeup functionality.
+		This allows the system to wake up from PM_STANDBY or PM_SLEEP
+		when a GPIO pin configured as an EXT1 wakeup source is triggered.
+
+menu "PM EXT1 Wakeup Sources"
+	depends on PM_EXT1_WAKEUP
+
+config PM_EXT1_WAKEUP_RTC_GPIO0
+	bool "RTC_GPIO0"
+	default n
+	---help---
+		Enable RTC GPIO0 as an EXT1 wakeup source.
+
+config PM_EXT1_WAKEUP_RTC_GPIO1
+	bool "RTC_GPIO1"
+	default n
+	---help---
+		Enable RTC GPIO1 as an EXT1 wakeup source.
+
+config PM_EXT1_WAKEUP_RTC_GPIO2
+	bool "RTC_GPIO2"
+	default n
+	---help---
+		Enable RTC GPIO2 as an EXT1 wakeup source.
+
+config PM_EXT1_WAKEUP_RTC_GPIO3
+	bool "RTC_GPIO3"
+	default n
+	---help---
+		Enable RTC GPIO3 as an EXT1 wakeup source.
+
+config PM_EXT1_WAKEUP_RTC_GPIO4
+	bool "RTC_GPIO4"
+	default n
+	---help---
+		Enable RTC GPIO4 as an EXT1 wakeup source.
+
+config PM_EXT1_WAKEUP_RTC_GPIO5
+	bool "RTC_GPIO5"
+	default n
+	---help---
+		Enable RTC GPIO5 as an EXT1 wakeup source.
+
+config PM_EXT1_WAKEUP_RTC_GPIO6
+	bool "RTC_GPIO6"
+	default n
+	---help---
+		Enable RTC GPIO6 as an EXT1 wakeup source.
+
+config PM_EXT1_WAKEUP_RTC_GPIO7
+	bool "RTC_GPIO7"
+	default n
+	---help---
+		Enable RTC GPIO7 as an EXT1 wakeup source.
+
+config PM_EXT1_WAKEUP_RTC_GPIO8
+	bool "RTC_GPIO8"
+	default n
+	---help---
+		Enable RTC GPIO8 as an EXT1 wakeup source.
+
+config PM_EXT1_WAKEUP_RTC_GPIO9
+	bool "RTC_GPIO9"
+	default n
+	---help---
+		Enable RTC GPIO9 as an EXT1 wakeup source.
+
+config PM_EXT1_WAKEUP_RTC_GPIO10
+	bool "RTC_GPIO10"
+	default n
+	---help---
+		Enable RTC GPIO10 as an EXT1 wakeup source.
+
+config PM_EXT1_WAKEUP_RTC_GPIO11
+	bool "RTC_GPIO11"
+	default n
+	---help---
+		Enable RTC GPIO11 as an EXT1 wakeup source.
+
+config PM_EXT1_WAKEUP_RTC_GPIO12
+	bool "RTC_GPIO12"
+	default n
+	---help---
+		Enable RTC GPIO12 as an EXT1 wakeup source.
+
+config PM_EXT1_WAKEUP_RTC_GPIO13
+	bool "RTC_GPIO13"
+	default n
+	---help---
+		Enable RTC GPIO13 as an EXT1 wakeup source.
+
+config PM_EXT1_WAKEUP_RTC_GPIO14
+	bool "RTC_GPIO14"
+	default n
+	---help---
+		Enable RTC GPIO14 as an EXT1 wakeup source.
+
+config PM_EXT1_WAKEUP_RTC_GPIO15
+	bool "RTC_GPIO15"
+	default n
+	---help---
+		Enable RTC GPIO15 as an EXT1 wakeup source.
+
+config PM_EXT1_WAKEUP_RTC_GPIO16
+	bool "RTC_GPIO16"
+	default n
+	---help---
+		Enable RTC GPIO16 as an EXT1 wakeup source.
+
+config PM_EXT1_WAKEUP_RTC_GPIO17
+	bool "RTC_GPIO17"
+	default n
+	---help---
+		Enable RTC GPIO17 as an EXT1 wakeup source.
+
+config PM_EXT1_WAKEUP_RTC_GPIO18
+	bool "RTC_GPIO18"
+	default n
+	---help---
+		Enable RTC GPIO18 as an EXT1 wakeup source.
+
+config PM_EXT1_WAKEUP_RTC_GPIO19
+	bool "RTC_GPIO19"
+	default n
+	---help---
+		Enable RTC GPIO19 as an EXT1 wakeup source.
+
+config PM_EXT1_WAKEUP_RTC_GPIO20
+	bool "RTC_GPIO20"
+	default n
+	---help---
+		Enable RTC GPIO20 as an EXT1 wakeup source.
+
+choice PM_EXT1_WAKEUP_TRIGGER_MODE
+	prompt "PM EXT1 Wakeup Trigger Mode"
+	default PM_EXT1_WAKEUP_TRIGGER_ANY_LOW
+
+config PM_EXT1_WAKEUP_TRIGGER_ANY_LOW
+	bool "Wake the chip when any of the selected GPIOs go low"
+
+config PM_EXT1_WAKEUP_TRIGGER_ANY_HIGH
+	bool "Wake the chip when any of the selected GPIOs go high"
+
+endchoice # PM_EXT1_WAKEUP_TRIGGER_MODE
+
+endmenu # PM_EXT1_WAKEUP_SOURCES
+
+config PM_EXT0_WAKEUP
+	bool "PM EXT0 Wakeup"
+	default n
+	---help---
+		Enable EXT0 wakeup functionality.
+		This allows the system to wake up from PM_STANDBY or PM_SLEEP
+		when a GPIO pin configured as an EXT0 wakeup source is triggered.
+
+menu "PM EXT0 Wakeup Sources"
+	depends on PM_EXT0_WAKEUP
+
+config PM_EXT0_WAKEUP_GPIO
+	int "EXT0 Wakeup GPIO"
+	depends on PM_EXT0_WAKEUP
+	default 0
+	range 0 20
+	---help---
+		GPIO to wake the device up from PM_STANDBY or PM_SLEEP using as EXT0 wakeup GPIO
+
+choice PM_EXT0_WAKEUP_TRIGGER_MODE
+	prompt "PM EXT0 Wakeup Trigger Mode"
+	default PM_EXT0_WAKEUP_TRIGGER_LOW
+
+config PM_EXT0_WAKEUP_TRIGGER_LOW
+	bool "Wake the chip when the selected GPIO go low"
+
+config PM_EXT0_WAKEUP_TRIGGER_HIGH
+	bool "Wake the chip when the selected GPIO go high"
+
+endchoice # PM_EXT0_WAKEUP_TRIGGER_MODE
+
+endmenu # PM_EXT0_WAKEUP_SOURCES
+
+config PM_ULP_WAKEUP
+	bool "PM ULP Wakeup"
+	default n
+	---help---
+		Enable ULP coprocessor wakeup functionality.
+		This allows the system to wake up from PM_STANDBY or PM_SLEEP
+		when ULP app triggers HP core to wakeup with "ulp_lp_core_wakeup_main_processor"
+		call on ULP app.
+
+config PM_GPIO_WAKEUP
+	bool "PM GPIO Wakeup"
+	default n
+	---help---
+		Enable GPIO wakeup functionality.
+		This allows the system to wake up from PM_STANDBY
+		when a GPIO pin configured as wakeup source is triggered.
+
+menu "PM GPIO Wakeup Sources"
+	depends on PM_GPIO_WAKEUP
+
+config PM_GPIO_WAKEUP_GPIO1
+	bool "GPIO1"
+	default n
+	---help---
+		Enable GPIO1 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO2
+	bool "GPIO2"
+	default n
+	---help---
+		Enable GPIO2 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO3
+	bool "GPIO3"
+	default n
+	---help---
+		Enable GPIO3 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO4
+	bool "GPIO4"
+	default n
+	---help---
+		Enable GPIO4 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO5
+	bool "GPIO5"
+	default n
+	---help---
+		Enable GPIO5 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO6
+	bool "GPIO6"
+	default n
+	---help---
+		Enable GPIO6 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO7
+	bool "GPIO7"
+	default n
+	---help---
+		Enable GPIO7 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO8
+	bool "GPIO8"
+	default n
+	---help---
+		Enable GPIO8 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO9
+	bool "GPIO9"
+	default n
+	---help---
+		Enable GPIO9 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO10
+	bool "GPIO10"
+	default n
+	---help---
+		Enable GPIO10 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO11
+	bool "GPIO11"
+	default n
+	---help---
+		Enable GPIO11 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO12
+	bool "GPIO12"
+	default n
+	---help---
+		Enable GPIO12 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO13
+	bool "GPIO13"
+	default n
+	---help---
+		Enable GPIO13 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO14
+	bool "GPIO14"
+	default n
+	---help---
+		Enable GPIO14 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO15
+	bool "GPIO15"
+	default n
+	---help---
+		Enable GPIO15 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO16
+	bool "GPIO16"
+	default n
+	---help---
+		Enable GPIO16 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO17
+	bool "GPIO17"
+	default n
+	---help---
+		Enable GPIO17 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO18
+	bool "GPIO18"
+	default n
+	---help---
+		Enable GPIO18 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO19
+	bool "GPIO19"
+	default n
+	---help---
+		Enable GPIO19 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO20
+	bool "GPIO20"
+	default n
+	---help---
+		Enable GPIO20 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO21
+	bool "GPIO21"
+	default n
+	---help---
+		Enable GPIO21 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO22
+	bool "GPIO22"
+	depends on !ARCH_CHIP_ESP32C3_GENERIC
+	default n
+	---help---
+		Enable GPIO22 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO23
+	bool "GPIO23"
+	depends on !ARCH_CHIP_ESP32C3_GENERIC
+	default n
+	---help---
+		Enable GPIO23 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO24
+	bool "GPIO24"
+	depends on !ARCH_CHIP_ESP32C3_GENERIC
+	default n
+	---help---
+		Enable GPIO24 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO25
+	bool "GPIO25"
+	depends on !ARCH_CHIP_ESP32C3_GENERIC
+	default n
+	---help---
+		Enable GPIO25 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO26
+	bool "GPIO26"
+	depends on !ARCH_CHIP_ESP32C3_GENERIC
+	default n
+	---help---
+		Enable GPIO26 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO27
+	bool "GPIO27"
+	depends on !ARCH_CHIP_ESP32C3_GENERIC
+	default n
+	---help---
+		Enable GPIO27 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO28
+	bool "GPIO28"
+	depends on ARCH_CHIP_ESP32C6
+	default n
+	---help---
+		Enable GPIO28 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO29
+	bool "GPIO29"
+	depends on ARCH_CHIP_ESP32C6
+	default n
+	---help---
+		Enable GPIO29 as an GPIO wakeup source.
+
+config PM_GPIO_WAKEUP_GPIO30
+	bool "GPIO30"
+	depends on ARCH_CHIP_ESP32C6
+	default n
+	---help---
+		Enable GPIO30 as an GPIO wakeup source.
+
+choice PM_GPIO_WAKEUP_TRIGGER_MODE
+	prompt "PM GPIO Wakeup Trigger Mode"
+	default PM_GPIO_WAKEUP_TRIGGER_ANY_LOW
+
+config PM_GPIO_WAKEUP_TRIGGER_ANY_LOW
+	bool "Wake the chip when any of the selected GPIOs go low"
+
+config PM_GPIO_WAKEUP_TRIGGER_ANY_HIGH
+	bool "Wake the chip when any of the selected GPIOs go high"
+
+endchoice # PM_GPIO_WAKEUP_TRIGGER_MODE
+
+endmenu # PM_GPIO_WAKEUP_SOURCES
+
+config PM_UART_WAKEUP
+	bool "PM UART Wakeup"
+	depends on ESP32S3_UART0 || ESP32S3_UART1
+	default n
+	---help---
+		Enable UART wakeup functionality.
+		This allows the system to wake up from PM_STANDBY
+		when a UART configured as an UART wakeup source is triggered.
+
+menu "PM UART Wakeup Sources"
+	depends on PM_UART_WAKEUP
+
+choice PM_UART_WAKEUP_UART_NUM
+	prompt "PM UART Wakeup UART Number"
+	default PM_UART_WAKEUP_UART0 if ESP32S3_UART0
+	default PM_UART_WAKEUP_UART1 if ESP32S3_UART1
+
+config PM_UART_WAKEUP_UART0
+	depends on ESP32S3_UART0
+	bool "Wake the chip up when UART0 gets a data"
+
+config PM_UART_WAKEUP_UART1
+	depends on ESP32S3_UART1
+	bool "Wake the chip up when UART1 gets a data"
+
+endchoice # PM_UART_WAKEUP_UART_NUM
+
+config PM_UART_WAKEUP_ACTIVE_EDGE_THRESHOLD
+	int "Number of RXD edge changes to to trigger wake-up"
+	default 3
+
+endmenu # PM UART Wakeup Sources
+
+config PM_ALARM_SEC
+	int "PM_STANDBY delay (seconds)"
+	default 15
+	---help---
+		Number of seconds to wait in PM_STANDBY mode.
+
+config PM_ALARM_NSEC
+	int "PM_STANDBY delay (nanoseconds)"
+	default 0
+	---help---
+		Number of additional nanoseconds to wait in PM_STANDBY mode.
+
+config PM_SLEEP_WAKEUP_SEC
+	int "PM_SLEEP delay (seconds)"
+	default 20
+	---help---
+		Number of seconds to wait in PM_SLEEP.
+
+config PM_SLEEP_WAKEUP_NSEC
+	int "PM_SLEEP delay (nanoseconds)"
+	default 0
+	---help---
+		Number of additional nanoseconds to wait in PM_SLEEP.
+
+endif # PM && !ARCH_CHIP_ESP32
+
+endmenu # PM Configuration
+
 menu "Pulse Counter (PCNT) Configuration"
 	depends on ESP_PCNT
 

arch/xtensa/src/common/espressif/Make.defs

@@ -117,6 +117,16 @@ ifeq ($(CONFIG_ESPRESSIF_ADC),y)
 CHIP_CSRCS += esp_adc.c
 endif
 
+ifneq ($(CONFIG_ARCH_CHIP_ESP32),y)
+ifeq ($(CONFIG_PM),y)
+ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y)
+CHIP_CSRCS += esp_pm_initialize.c
+endif
+CHIP_CSRCS += esp_pm.c
+LDFLAGS += -u esp_timer_init_include_func
+endif
+endif
+
 CHIP_CSRCS += esp_efuse.c
 
 LDFLAGS += -u esp_system_include_startup_funcs

arch/xtensa/src/common/espressif/esp_pm.c

@@ -0,0 +1,659 @@
+/****************************************************************************
+ * arch/xtensa/src/common/espressif/esp_pm.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/power/pm.h>
+
+#include <debug.h>
+
+#include "esp_pm.h"
+#ifdef CONFIG_SCHED_TICKLESS
+#  include "esp_tickless.h"
+#endif
+#include "esp_sleep.h"
+#include "soc/rtc.h"
+#include "esp_sleep_internal.h"
+#include "esp_pmu.h"
+#ifdef CONFIG_PM_EXT1_WAKEUP
+#  include "driver/rtc_io.h"
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP
+#  include "driver/gpio.h"
+#  include "hal/gpio_types.h"
+#  if defined(CONFIG_ARCH_CHIP_ESP32S3)
+#    include "esp32s3_gpio.h"
+#  elif defined(CONFIG_ARCH_CHIP_ESP32S2)
+#    include "esp32s2_gpio.h"
+#endif
+#endif
+#ifdef CONFIG_PM_UART_WAKEUP
+#  include "driver/uart_wakeup.h"
+#  include "hal/uart_types.h"
+#  include "hal/uart_hal.h"
+#  include "hal/uart_ll.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if defined(CONFIG_ARCH_CHIP_ESP32S3)
+#define esp_configgpio            esp32s3_configgpio
+#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
+#define esp_configgpio            esp32s2_configgpio
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Wakeup reasons string. */
+
+const char *g_wakeup_reasons[] =
+{
+  "undefined",
+  "",
+  "EXT0",
+  "EXT1",
+  "Timer",
+  "TOUCHPAD",
+  "ULP",
+  "GPIO",
+  "UART",
+  "",
+  "COCPU",
+  "COCPU TRAP",
+  "",
+  "",
+  ""
+};
+
+static _Atomic uint32_t pm_wakelock = 0;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_PM_EXT0_WAKEUP
+/****************************************************************************
+ * Name: esp_pm_ext0_wakeup_prepare
+ *
+ * Description:
+ *   Configure ext0 gpios to use as wakeup source.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void IRAM_ATTR esp_pm_ext0_wakeup_prepare(void)
+{
+  int pin = CONFIG_PM_EXT0_WAKEUP_GPIO;
+#  ifdef CONFIG_PM_EXT0_WAKEUP_TRIGGER_LOW
+  int level_mode = 0;
+#  else
+  int level_mode = 1;
+#  endif /* CONFIG_PM_EXT0_WAKEUP */
+  esp_sleep_enable_ext0_wakeup(pin, level_mode);
+}
+#endif /* CONFIG_PM_EXT0_WAKEUP */
+
+#ifdef CONFIG_PM_EXT1_WAKEUP
+/****************************************************************************
+ * Name: esp_pm_get_ext1_io_mask
+ *
+ * Description:
+ *   Get ext1 IO mask value from configured wakeup pins.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   A 64-bit unsigned integer where each bit corresponds to an RTC GPIO pin
+ *   that has been configured as an ext1 wakeup source.
+ *
+ ****************************************************************************/
+
+static uint64_t IRAM_ATTR esp_pm_get_ext1_io_mask(void)
+{
+  uint64_t io_mask = 0;
+#ifdef CONFIG_PM_EXT1_WAKEUP_RTC_GPIO0
+  io_mask |= BIT(0);
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP_RTC_GPIO1
+  io_mask |= BIT(1);
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP_RTC_GPIO2
+  io_mask |= BIT(2);
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP_RTC_GPIO3
+  io_mask |= BIT(3);
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP_RTC_GPIO4
+  io_mask |= BIT(4);
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP_RTC_GPIO5
+  io_mask |= BIT(5);
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP_RTC_GPIO6
+  io_mask |= BIT(6);
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP_RTC_GPIO7
+  io_mask |= BIT(7);
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP_RTC_GPIO8
+  io_mask |= BIT(8);
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP_RTC_GPIO9
+  io_mask |= BIT(9);
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP_RTC_GPIO10
+  io_mask |= BIT(10);
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP_RTC_GPIO11
+  io_mask |= BIT(11);
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP_RTC_GPIO12
+  io_mask |= BIT(12);
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP_RTC_GPIO13
+  io_mask |= BIT(13);
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP_RTC_GPIO14
+  io_mask |= BIT(14);
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP_RTC_GPIO15
+  io_mask |= BIT(15);
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP_RTC_GPIO16
+  io_mask |= BIT(16);
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP_RTC_GPIO17
+  io_mask |= BIT(17);
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP_RTC_GPIO18
+  io_mask |= BIT(18);
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP_RTC_GPIO19
+  io_mask |= BIT(19);
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP_RTC_GPIO20
+  io_mask |= BIT(20);
+#endif
+
+  return io_mask;
+}
+
+/****************************************************************************
+ * Name: esp_pm_ext1_wakeup_prepare
+ *
+ * Description:
+ *   Configure ext1 gpios to use as wakeup source.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void IRAM_ATTR esp_pm_ext1_wakeup_prepare(void)
+{
+  int pin_mask;
+  uint64_t io_mask;
+#  ifdef CONFIG_PM_EXT1_WAKEUP_TRIGGER_ANY_LOW
+  esp_sleep_ext1_wakeup_mode_t level_mode = ESP_EXT1_WAKEUP_ANY_LOW;
+#  else
+  esp_sleep_ext1_wakeup_mode_t level_mode = ESP_EXT1_WAKEUP_ANY_HIGH;
+#  endif /* CONFIG_PM_EXT1_WAKEUP */
+  io_mask = esp_pm_get_ext1_io_mask();
+  for (int i = 0; i < CONFIG_SOC_GPIO_PIN_COUNT; i++)
+    {
+      pin_mask = BIT(i);
+      if ((io_mask & pin_mask) != 0)
+        {
+          esp_sleep_enable_ext1_wakeup_io(pin_mask, level_mode);
+        }
+    }
+
+  esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
+}
+#endif /* CONFIG_PM_EXT1_WAKEUP */
+
+#ifdef CONFIG_PM_GPIO_WAKEUP
+/****************************************************************************
+ * Name: esp_pm_get_gpio_mask
+ *
+ * Description:
+ *   Get GPIO mask value from configured wakeup pins.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   A 64-bit unsigned integer where each bit corresponds to an GPIO pin
+ *   that has been configured as an GPIO wakeup source.
+ *
+ ****************************************************************************/
+
+static uint64_t IRAM_ATTR esp_pm_get_gpio_mask(void)
+{
+  uint64_t io_mask = 0;
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO0
+  io_mask |= BIT(0);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO1
+  io_mask |= BIT(1);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO2
+  io_mask |= BIT(2);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO3
+  io_mask |= BIT(3);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO4
+  io_mask |= BIT(4);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO5
+  io_mask |= BIT(5);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO6
+  io_mask |= BIT(6);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO7
+  io_mask |= BIT(7);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO8
+  io_mask |= BIT(8);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO9
+  io_mask |= BIT(9);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO10
+  io_mask |= BIT(10);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO11
+  io_mask |= BIT(11);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO12
+  io_mask |= BIT(12);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO13
+  io_mask |= BIT(13);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO14
+  io_mask |= BIT(14);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO15
+  io_mask |= BIT(15);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO16
+  io_mask |= BIT(16);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO17
+  io_mask |= BIT(17);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO18
+  io_mask |= BIT(18);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO19
+  io_mask |= BIT(19);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO20
+  io_mask |= BIT(20);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO21
+  io_mask |= BIT(21);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO22
+  io_mask |= BIT(22);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO23
+  io_mask |= BIT(23);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO24
+  io_mask |= BIT(24);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO25
+  io_mask |= BIT(25);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO26
+  io_mask |= BIT(26);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO27
+  io_mask |= BIT(27);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO28
+  io_mask |= BIT(28);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO29
+  io_mask |= BIT(29);
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO30
+  io_mask |= BIT(30);
+#endif
+
+  return io_mask;
+}
+
+/****************************************************************************
+ * Name: esp_pm_gpio_wakeup_prepare
+ *
+ * Description:
+ *   Configure gpios to use as gpio wakeup source.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void IRAM_ATTR esp_pm_gpio_wakeup_prepare(void)
+{
+  uint64_t mask_value = esp_pm_get_gpio_mask();
+  int pin_mask = 0;
+#  ifdef CONFIG_PM_GPIO_WAKEUP_TRIGGER_ANY_LOW
+  gpio_int_type_t level_mode = GPIO_INTR_LOW_LEVEL;
+#  else
+  gpio_int_type_t level_mode = GPIO_INTR_HIGH_LEVEL;
+#  endif /* CONFIG_PM_EXT1_WAKEUP */
+
+  for (int i = 0; i < CONFIG_SOC_GPIO_PIN_COUNT; i++)
+    {
+      pin_mask = BIT(i);
+      if ((mask_value & pin_mask) != 0)
+        {
+          esp_configgpio(i, INPUT);
+          gpio_wakeup_enable(i, level_mode);
+        }
+    }
+
+  esp_sleep_enable_gpio_wakeup();
+}
+#endif /* CONFIG_PM_GPIO_WAKEUP */
+
+#ifdef CONFIG_PM_UART_WAKEUP
+/****************************************************************************
+ * Name: esp_pm_uart_wakeup_prepare
+ *
+ * Description:
+ *   Configure UART wake-up mode
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void IRAM_ATTR esp_pm_uart_wakeup_prepare(void)
+{
+#  if defined(CONFIG_PM_UART_WAKEUP_UART0)
+  int uart_num = 0;
+#  elif defined(CONFIG_PM_UART_WAKEUP_UART1)
+  int uart_num = 1;
+#  endif
+  uart_wakeup_cfg_t wake_up_cfg =
+    {
+      .wakeup_mode = UART_WK_MODE_ACTIVE_THRESH,
+      .rx_edge_threshold = CONFIG_PM_UART_WAKEUP_ACTIVE_EDGE_THRESHOLD
+    };
+
+  uart_wakeup_setup(uart_num, &wake_up_cfg);
+  esp_sleep_enable_uart_wakeup(uart_num);
+}
+#endif /* CONFIG_PM_UART_WAKEUP */
+
+/****************************************************************************
+ * Name: esp_pm_sleep_enable_timer_wakeup
+ *
+ * Description:
+ *   Configure wakeup interval
+ *
+ * Input Parameters:
+ *   time_in_us - Sleep duration in microseconds.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void esp_pm_sleep_enable_timer_wakeup(uint64_t time_in_us)
+{
+  esp_sleep_enable_timer_wakeup(time_in_us);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp_pm_light_sleep_start
+ *
+ * Description:
+ *   Enter light sleep mode
+ *
+ * Input Parameters:
+ *   sleep_time - Reference of uint64_t value to return actual sleep duration
+ *                in microseconds. Use NULL if not needed.
+ *
+ * Returned Value:
+ *   OK on success or a negated errno value if fails.
+ *
+ ****************************************************************************/
+
+int esp_pm_light_sleep_start(uint64_t *sleep_time)
+{
+  int ret = OK;
+  int sleep_start = rtc_time_get();
+  int sleep_return = 0;
+
+  ret = esp_light_sleep_start();
+  if (sleep_time != NULL)
+    {
+      sleep_return = rtc_time_get();
+      *sleep_time = sleep_return - sleep_start;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name:  esp_pm_deep_sleep_start
+ *
+ * Description:
+ *   Enter deep sleep mode
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void esp_pm_deep_sleep_start(void)
+{
+  esp_deep_sleep_start();
+
+  /* Because RTC is in a slower clock domain than the CPU, it
+   * can take several CPU cycles for the sleep mode to start.
+   */
+
+  while (1);
+}
+
+/****************************************************************************
+ * Name: esp_pmstandby
+ *
+ * Description:
+ *   Enter pm standby (light sleep) mode.
+ *
+ * Input Parameters:
+ *   time_in_us - The maximum time to sleep in microseconds.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void esp_pmstandby(uint64_t time_in_us)
+{
+  uint64_t rtc_diff_us;
+  esp_sleep_wakeup_cause_t cause;
+#ifdef CONFIG_PM_GPIO_WAKEUP
+  int64_t gpio_mask;
+#endif
+#ifdef CONFIG_PM_EXT0_WAKEUP
+  esp_pm_ext0_wakeup_prepare();
+#endif
+#ifdef CONFIG_PM_EXT1_WAKEUP
+  int64_t ext1_mask;
+  esp_pm_ext1_wakeup_prepare();
+#endif
+#ifdef CONFIG_PM_GPIO_WAKEUP
+  esp_pm_gpio_wakeup_prepare();
+#endif
+#ifdef CONFIG_PM_ULP_WAKEUP
+  esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
+  esp_sleep_enable_ulp_wakeup();
+#endif
+#ifdef CONFIG_PM_UART_WAKEUP
+  esp_pm_uart_wakeup_prepare();
+#endif /* CONFIG_PM_UART_WAKEUP */
+
+  esp_pm_sleep_enable_timer_wakeup(time_in_us);
+
+  esp_pm_light_sleep_start(&rtc_diff_us);
+
+#ifdef CONFIG_SCHED_TICKLESS
+  up_step_idletime((uint32_t)time_in_us);
+#endif
+
+  cause = esp_sleep_get_wakeup_cause();
+  pwrinfo("Returned from light-sleep with: %s, slept for %" PRIu32 " ms\n",
+          g_wakeup_reasons[cause],
+          (uint32_t)(rtc_diff_us) / 1000);
+
+#ifdef CONFIG_PM_EXT1_WAKEUP
+  if (cause == ESP_SLEEP_WAKEUP_EXT1)
+    {
+      ext1_mask = esp_sleep_get_ext1_wakeup_status();
+      pwrinfo("EXT1 wakeup mask: %" PRIu64 "\n", ext1_mask);
+    }
+#endif
+}
+
+/****************************************************************************
+ * Name: esp_pmsleep
+ *
+ * Description:
+ *   Enter pm sleep (deep sleep) mode.
+ *
+ * Input Parameters:
+ *   time_in_us - The maximum time to sleep in microseconds.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void esp_pmsleep(uint64_t time_in_us)
+{
+#ifdef CONFIG_PM_EXT1_WAKEUP
+  esp_pm_ext1_wakeup_prepare();
+#endif
+#ifdef CONFIG_PM_ULP_WAKEUP
+  esp_sleep_enable_ulp_wakeup();
+#endif
+  esp_pm_sleep_enable_timer_wakeup(time_in_us);
+  esp_pm_deep_sleep_start();
+}
+
+/****************************************************************************
+ * Name: esp_pm_lockacquire
+ *
+ * Description:
+ *   Take a power management lock
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void IRAM_ATTR esp_pm_lockacquire(void)
+{
+  ++pm_wakelock;
+}
+
+/****************************************************************************
+ * Name: esp_pm_lockrelease
+ *
+ * Description:
+ *   Release the lock taken using esp_pm_lockacquire.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void IRAM_ATTR esp_pm_lockrelease(void)
+{
+  --pm_wakelock;
+}
+
+/****************************************************************************
+ * Name: esp_pm_lockstatus
+ *
+ * Description:
+ *   Return power management lock status.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Current pm_wakelock count
+ *
+ ****************************************************************************/
+
+uint32_t IRAM_ATTR esp_pm_lockstatus(void)
+{
+  return pm_wakelock;
+}

arch/xtensa/src/common/espressif/esp_pm.h

@@ -0,0 +1,173 @@
+/****************************************************************************
+ * arch/xtensa/src/common/espressif/esp_pm.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_V_SRC_COMMON_ESPRESSIF_ESP_PM_H
+#define __ARCH_XTENSA_V_SRC_COMMON_ESPRESSIF_ESP_PM_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#ifdef CONFIG_PM
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp_pm_light_sleep_start
+ *
+ * Description:
+ *   Enter light sleep mode
+ *
+ * Input Parameters:
+ *   sleep_time - Reference of uint64_t value to return actual sleep duration
+ *                in microseconds. Use NULL if not needed.
+ *
+ * Returned Value:
+ *   OK on success or a negated errno value if fails.
+ *
+ ****************************************************************************/
+
+int esp_pm_light_sleep_start(uint64_t *sleep_time);
+
+/****************************************************************************
+ * Name:  esp_pm_deep_sleep_start
+ *
+ * Description:
+ *   Enter deep sleep mode
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void esp_pm_deep_sleep_start(void);
+
+/****************************************************************************
+ * Name: esp_pm_pmstandby
+ *
+ * Description:
+ *   Enter pm standby (light sleep) mode.
+ *
+ * Input Parameters:
+ *   time_in_us - The maximum time to sleep in microseconds.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void esp_pmstandby(uint64_t time_in_us);
+
+/****************************************************************************
+ * Name: esp_pmsleep
+ *
+ * Description:
+ *   Enter pm sleep (deep sleep) mode.
+ *
+ * Input Parameters:
+ *   time_in_us - The maximum time to sleep in microseconds.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void esp_pmsleep(uint64_t time_in_us);
+
+/****************************************************************************
+ * Name: esp_pm_lockacquire
+ *
+ * Description:
+ *   Take a power management lock
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void esp_pm_lockacquire(void);
+
+/****************************************************************************
+ * Name: esp_pm_lockrelease
+ *
+ * Description:
+ *   Release the lock taken using esp_pm_lockacquire.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void esp_pm_lockrelease(void);
+
+/****************************************************************************
+ * Name: esp_pm_lockstatus
+ *
+ * Description:
+ *   Return power management lock status.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Current pm_wakelock count
+ *
+ ****************************************************************************/
+
+uint32_t esp_pm_lockstatus(void);
+
+#endif /* CONFIG_PM */
+
+#ifdef __cplusplus
+}
+#endif
+#undef EXTERN
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_XTENSA_V_SRC_COMMON_ESPRESSIF_ESP_PM_H */

arch/xtensa/src/common/espressif/esp_pm_initialize.c

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/xtensa/src/esp32s3/esp32s3_pminitialize.c
+ * arch/xtensa/src/common/espressif/esp_pm_initialize.c
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with

arch/xtensa/src/esp32s2/Make.defs

@@ -133,7 +133,7 @@ endif
 
 ESP_HAL_3RDPARTY_REPO   = esp-hal-3rdparty
 ifndef ESP_HAL_3RDPARTY_VERSION
-	ESP_HAL_3RDPARTY_VERSION = 4eed03a15b2678a81dfd1ed0f3bde042b1fdd4c4
+	ESP_HAL_3RDPARTY_VERSION = 6b4f19b48c5ba0e847511b5b21584e797ec795dc
 endif
 
 ifndef ESP_HAL_3RDPARTY_URL

arch/xtensa/src/esp32s2/esp32s2_idle.c

@@ -23,11 +23,16 @@
  ****************************************************************************/
 
 #include <nuttx/config.h>
+#include <debug.h>
 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
 #include <nuttx/power/pm.h>
+#include <nuttx/spinlock.h>
 
 #include "xtensa.h"
+#ifdef CONFIG_PM
+#include "espressif/esp_pm.h"
+#endif
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -81,10 +86,22 @@ static spinlock_t g_esp32s2_idle_lock = SP_UNLOCKED;
 #ifdef CONFIG_PM
 static void up_idlepm(void)
 {
+  irqstate_t flags;
   static enum pm_state_e oldstate = PM_NORMAL;
   enum pm_state_e newstate;
-  irqstate_t flags;
   int ret;
+  int count;
+
+  count = pm_staycount(PM_IDLE_DOMAIN, PM_NORMAL);
+  if (oldstate != PM_NORMAL && count == 0)
+    {
+      pm_stay(PM_IDLE_DOMAIN, PM_NORMAL);
+
+      /* Keep working in normal stage */
+
+      pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL);
+      newstate = PM_NORMAL;
+    }
 
   /* Decide, which power saving level can be obtained */
 
@@ -132,8 +149,8 @@ static void up_idlepm(void)
           {
             /* Enter Force-sleep mode */
 
-            esp32s2_pmstandby(CONFIG_PM_ALARM_SEC * 1000000 +
-                                  CONFIG_PM_ALARM_NSEC / 1000);
+            esp_pmstandby(CONFIG_PM_ALARM_SEC * 1000000 +
+                          CONFIG_PM_ALARM_NSEC / 1000);
           }
           break;
 
@@ -141,10 +158,9 @@ static void up_idlepm(void)
           {
             /* Enter Deep-sleep mode */
 
-            esp32s2_pmsleep(CONFIG_PM_SLEEP_WAKEUP_SEC * 1000000 +
-                                CONFIG_PM_SLEEP_WAKEUP_NSEC / 1000);
+            esp_pmsleep(CONFIG_PM_SLEEP_WAKEUP_SEC * 1000000 +
+                        CONFIG_PM_SLEEP_WAKEUP_NSEC / 1000);
           }
-          break;
 
         default:
           break;
@@ -152,13 +168,6 @@ static void up_idlepm(void)
     }
   else
     {
-      if (oldstate == PM_NORMAL)
-        {
-          /* Relax normal operation */
-
-          pm_relax(PM_IDLE_DOMAIN, PM_NORMAL);
-        }
-
 #ifdef CONFIG_WATCHDOG
       /* Announce the power management state change to feed watchdog */
 

arch/xtensa/src/esp32s2/hal.mk

@@ -50,11 +50,13 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)include$(DELIM)$(CHIP_SERIES)
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include$(DELIM)$(CHIP_SERIES)$(DELIM)rom
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include$(DELIM)private
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)public_compat
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)include
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)private_include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)include
@@ -65,6 +67,7 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level$(DELIM)linked_list
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)include
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)newlib
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)newlib$(DELIM)priv_include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)register
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)deprecated_include
@@ -142,8 +145,10 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbed
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)src$(DELIM)rtc_io.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)adc_share_hw_ctrl.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_ctrl_os.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_utils.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)cpu.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_clk.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_memory_utils.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)hw_random.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mac_addr.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)periph_ctrl.c
@@ -153,20 +158,29 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk_init.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_init.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_sleep.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_time.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)systimer.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_event.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_gpio.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_modem.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_init.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_common.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_regi2c_$(CHIP_SERIES).c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_wdt.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)esp_err.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)esp_system.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)startup.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)startup_funcs.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)system_time.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)clk.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)system_internal.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_impl_common.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_impl_systimer.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_init.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)system_time.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)adc_hal_common.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)adc_oneshot_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c
@@ -188,8 +202,11 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2s_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)sha_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)touch_sens_hal.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)systimer_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)newlib$(DELIM)src$(DELIM)port$(DELIM)esp_time_impl.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)dport_access_common.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)adc_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)dedic_gpio_periph.c

arch/xtensa/src/esp32s3/Make.defs

@@ -181,13 +181,6 @@ ifeq ($(CONFIG_ESP32S3_AES_ACCELERATOR),y)
 CHIP_CSRCS += esp32s3_aes.c
 endif
 
-ifeq ($(CONFIG_PM),y)
-ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y)
-CHIP_CSRCS += esp32s3_pminitialize.c
-endif
-CHIP_CSRCS += esp32s3_pm.c
-endif
-
 ifeq ($(CONFIG_ESP32S3_OPENETH),y)
 CHIP_CSRCS += esp_openeth.c
 endif
@@ -209,7 +202,7 @@ endif
 
 ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
 ifndef ESP_HAL_3RDPARTY_VERSION
-	ESP_HAL_3RDPARTY_VERSION = 4eed03a15b2678a81dfd1ed0f3bde042b1fdd4c4
+	ESP_HAL_3RDPARTY_VERSION = 6b4f19b48c5ba0e847511b5b21584e797ec795dc
 endif
 
 ifndef ESP_HAL_3RDPARTY_URL

arch/xtensa/src/esp32s3/esp32s3_idle.c

@@ -32,7 +32,7 @@
 #include <nuttx/spinlock.h>
 
 #include "xtensa.h"
-#include "esp32s3_pm.h"
+#include "espressif/esp_pm.h"
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -149,8 +149,8 @@ static void up_idlepm(void)
           {
             /* Enter Force-sleep mode */
 
-            esp32s3_pmstandby(CONFIG_PM_ALARM_SEC * 1000000 +
-                              CONFIG_PM_ALARM_NSEC / 1000);
+            esp_pmstandby(CONFIG_PM_ALARM_SEC * 1000000 +
+                          CONFIG_PM_ALARM_NSEC / 1000);
           }
           break;
 
@@ -158,8 +158,8 @@ static void up_idlepm(void)
           {
             /* Enter Deep-sleep mode */
 
-            esp32s3_pmsleep(CONFIG_PM_SLEEP_WAKEUP_SEC * 1000000 +
-                            CONFIG_PM_SLEEP_WAKEUP_NSEC / 1000);
+            esp_pmsleep(CONFIG_PM_SLEEP_WAKEUP_SEC * 1000000 +
+                        CONFIG_PM_SLEEP_WAKEUP_NSEC / 1000);
           }
 
         default:

arch/xtensa/src/esp32s3/esp32s3_pm.h

@@ -1,302 +0,0 @@
-/****************************************************************************
- * arch/xtensa/src/esp32s3/esp32s3_pm.h
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements.  See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership.  The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License.  You may obtain a copy of the License at
- *
- *   http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PM_H
-#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PM_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#ifndef __ASSEMBLY__
-
-#undef EXTERN
-#if defined(__cplusplus)
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-#ifdef CONFIG_PM
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/* Callback function type for peripherals to
- * know light sleep wakeup overhead.
- */
-
-typedef void (*inform_out_sleep_overhead_cb_t)(uint32_t);
-
-/* Callback function type for peripherals to skip light sleep. */
-
-typedef bool (*skip_light_sleep_cb_t)(void);
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Name:  esp32s3_sleep_enable_timer_wakeup
- *
- * Description:
- *   Configure wake-up interval
- *
- * Input Parameters:
- *   time_in_us - Configure wake-up time interval
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-void esp32s3_sleep_enable_timer_wakeup(uint64_t time_in_us);
-
-/****************************************************************************
- * Name:  esp32s3_light_sleep_start
- *
- * Description:
- *   Enter light sleep mode
- *
- * Input Parameters:
- *   sleep_time - Actual sleep time
- *
- * Returned Value:
- *   0 is returned on success or a negated errno value is returned
- *
- ****************************************************************************/
-
-int esp32s3_light_sleep_start(uint64_t *sleep_time);
-
-/****************************************************************************
- * Name: esp32s3_pmstandby
- *
- * Description:
- *   Enter force sleep time interval.
- *
- * Input Parameters:
- *   time_in_us - Force sleep time interval
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-void esp32s3_pmstandby(uint64_t time_in_us);
-
-/****************************************************************************
- * Name:  esp32s3_deep_sleep_start
- *
- * Description:
- *   Enter deep sleep mode
- *
- * Input Parameters:
- *   None
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-void esp32s3_deep_sleep_start(void);
-
-/****************************************************************************
- * Name: esp32s3_pmsleep
- *
- * Description:
- *   Enter deep sleep.
- *
- * Input Parameters:
- *   time_in_us - Deep sleep time interval
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-void esp32s3_pmsleep(uint64_t time_in_us);
-
-/****************************************************************************
- * Name: esp32s3_pm_lockacquire
- *
- * Description:
- *   Take a power management lock
- *
- * Input Parameters:
- *   None
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-void esp32s3_pm_lockacquire(void);
-
-/****************************************************************************
- * Name: esp32s3_pm_lockrelease
- *
- * Description:
- *   Release the lock taken using esp32s3_pm_lockacquire.
- *
- * Input Parameters:
- *   None
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-void esp32s3_pm_lockrelease(void);
-
-/****************************************************************************
- * Name: esp32s3_pm_lockstatus
- *
- * Description:
- *   Return power management lock status.
- *
- * Input Parameters:
- *   None
- *
- * Returned Value:
- *   Current pm_wakelock count
- *
- ****************************************************************************/
-
-uint32_t esp32s3_pm_lockstatus(void);
-
-/****************************************************************************
- * Name:  esp32s3_sleep_enable_wifi_wakeup
- *
- * Description:
- *   Configure Wi-Fi wake-up source
- *
- * Input Parameters:
- *   None
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-void esp32s3_sleep_enable_wifi_wakeup(void);
-
-/****************************************************************************
- * Name:  esp32s3_should_skip_light_sleep
- *
- * Description:
- *   Indicates if light sleep should be skipped.
- *
- * Input Parameters:
- *   None
- *
- * Returned Value:
- *   True is returned on success. Otherwise false.
- *
- ****************************************************************************/
-
-bool esp32s3_should_skip_light_sleep(void);
-
-/****************************************************************************
- * Name:  esp32s3_pm_register_inform_out_sleep_overhead_callback
- *
- * Description:
- *   Register informing peripherals of light sleep wakeup overhead time
- *   callback function.
- *
- * Input Parameters:
- *   cb - Callback function
- *
- * Returned Value:
- *   Zero (OK) is returned on success. Otherwise -1 (ERROR).
- *
- ****************************************************************************/
-
-int esp32s3_pm_register_inform_out_sleep_overhead_callback(
-                            inform_out_sleep_overhead_cb_t cb);
-
-/****************************************************************************
- * Name:  esp32s3_pm_unregister_inform_out_sleep_overhead_callback
- *
- * Description:
- *   Unregister informing peripherals of light sleep wakeup overhead time
- *   callback function.
- *
- * Input Parameters:
- *   cb - Callback function
- *
- * Returned Value:
- *   Zero (OK) is returned on success. Otherwise -1 (ERROR).
- *
- ****************************************************************************/
-
-int esp32s3_pm_unregister_inform_out_sleep_overhead_callback(
-                              inform_out_sleep_overhead_cb_t cb);
-
-/****************************************************************************
- * Name:  esp32s3_pm_register_skip_sleep_callback
- *
- * Description:
- *   Unregister callback function of skipping light sleep.
- *
- * Input Parameters:
- *   cb - Callback function
- *
- * Returned Value:
- *   Zero (OK) is returned on success. Otherwise -1 (ERROR).
- *
- ****************************************************************************/
-
-int esp32s3_pm_register_skip_sleep_callback(skip_light_sleep_cb_t cb);
-
-/****************************************************************************
- * Name:  esp32s3_pm_unregister_skip_sleep_callback
- *
- * Description:
- *   Register callback function of skipping light sleep.
- *
- * Input Parameters:
- *   cb - Callback function
- *
- * Returned Value:
- *   Zero (OK) is returned on success. Otherwise -1 (ERROR).
- *
- ****************************************************************************/
-
-int esp32s3_pm_unregister_skip_sleep_callback(skip_light_sleep_cb_t cb);
-
-#endif /* CONFIG_PM */
-
-#ifdef __cplusplus
-}
-#endif
-#undef EXTERN
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PM_H */

arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c

@@ -53,7 +53,7 @@
 #include "periph_ctrl.h"
 
 #ifdef CONFIG_PM
-#  include "esp32s3_pm.h"
+#  include "espressif/esp_pm.h"
 #endif
 
 #ifdef CONFIG_ESPRESSIF_BLE

arch/xtensa/src/esp32s3/hal.mk

@@ -33,6 +33,8 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_coex$(DELIM)include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_event$(DELIM)include
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)include
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)private_include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)esp_private
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)soc
@@ -47,6 +49,7 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)$(CHIP_SERIES)$(DELIM)include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)include$(DELIM)$(CHIP_SERIES)
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include
@@ -59,6 +62,7 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)platform_port$(DELIM)include
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)heap$(DELIM)include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level
@@ -76,6 +80,7 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)include
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_uart$(DELIM)include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)mbedtls
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_common
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_common$(DELIM)include
@@ -116,11 +121,18 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)src$(DELIM)esp_err_to_name.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)adc_share_hw_ctrl.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_ctrl_os.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_utils.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)cpu.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_clk.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_memory_utils.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)hw_random.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mac_addr.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)periph_ctrl.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_console.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_event.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_gpio.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_modem.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)lowpower$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)sleep_cpu.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)sar_periph_ctrl.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)cpu_region_protect.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_clk_tree.c
@@ -152,10 +164,14 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)system_time.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)clk.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)system_internal.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_impl_common.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_impl_systimer.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_init.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)adc_hal_common.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)adc_oneshot_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)efuse_hal.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_cntl_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)brownout_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)efuse_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gpio_hal.c
@@ -168,7 +184,9 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2s_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)sha_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mcpwm_hal.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)systimer_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)touch_sens_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)cache_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mpu_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mmu_hal.c
@@ -189,6 +207,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)os$(DELIM)log_write.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)os$(DELIM)util.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)sha$(DELIM)core$(DELIM)esp_sha256.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)newlib$(DELIM)src$(DELIM)port$(DELIM)esp_time_impl.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)dport_access_common.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)dedic_gpio_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gdma_periph.c
@@ -230,7 +249,9 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_riscv$(DELIM)ulp_riscv_lock.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_riscv$(DELIM)ulp_riscv_i2c.c
 
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)src$(DELIM)gpio.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)src$(DELIM)rtc_io.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_uart$(DELIM)src$(DELIM)uart_wakeup.c
 
 CHIP_ASRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_cache_writeback_esp32s3.S
 

boards/arm/kl/freedom-kl25z/CMakeLists.txt

@@ -0,0 +1,23 @@
+# ##############################################################################
+# boards/arm/kl/freedom-kl25z/CMakeLists.txt
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more contributor
+# license agreements.  See the NOTICE file distributed with this work for
+# additional information regarding copyright ownership.  The ASF licenses this
+# file to you under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License.  You may obtain a copy of
+# the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations under
+# the License.
+#
+# ##############################################################################
+
+add_subdirectory(src)

boards/arm/kl/freedom-kl25z/src/CMakeLists.txt

@@ -0,0 +1,68 @@
+# ##############################################################################
+# boards/arm/kl/freedom-kl25z/src/CMakeLists.txt
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more contributor
+# license agreements.  See the NOTICE file distributed with this work for
+# additional information regarding copyright ownership.  The ASF licenses this
+# file to you under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License.  You may obtain a copy of
+# the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations under
+# the License.
+#
+# ##############################################################################
+
+set(SRCS kl_boardinitialize.c)
+
+if(CONFIG_BOARDCTL)
+  list(APPEND SRCS kl_appinit.c)
+endif()
+
+if(CONFIG_KL_TSI)
+  list(APPEND SRCS kl_tsi.c)
+endif()
+
+if(CONFIG_KL_SPI0)
+  list(APPEND SRCS kl_spi.c)
+else()
+  if(CONFIG_KL_SPI1)
+    list(APPEND SRCS kl_spi.c)
+  endif()
+endif()
+
+if(CONFIG_ARCH_LEDS)
+  list(APPEND SRCS kl_led.c)
+endif()
+
+if(CONFIG_KL_USBOTG)
+  list(APPEND SRCS kl_usb.c)
+endif()
+
+if(CONFIG_PWM)
+  list(APPEND SRCS kl_pwm.c)
+endif()
+
+if(CONFIG_SENSORS_QENCODER)
+  list(APPEND SRCS kl_qencoder.c)
+endif()
+
+if(CONFIG_WATCHDOG)
+  list(APPEND SRCS kl_watchdog.c)
+endif()
+
+if(CONFIG_SENSORS_ADXL345)
+  list(APPEND SRCS kl_adxl345.c)
+endif()
+
+target_sources(board PRIVATE ${SRCS})
+
+set_property(GLOBAL PROPERTY LD_SCRIPT
+                             "${NUTTX_BOARD_DIR}/scripts/freedom-kl25z.ld")

boards/arm/kl/freedom-kl26z/CMakeLists.txt

@@ -0,0 +1,23 @@
+# ##############################################################################
+# boards/arm/kl/freedom-kl26z/CMakeLists.txt
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more contributor
+# license agreements.  See the NOTICE file distributed with this work for
+# additional information regarding copyright ownership.  The ASF licenses this
+# file to you under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License.  You may obtain a copy of
+# the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations under
+# the License.
+#
+# ##############################################################################
+
+add_subdirectory(src)

boards/arm/kl/freedom-kl26z/src/CMakeLists.txt

@@ -0,0 +1,52 @@
+# ##############################################################################
+# boards/arm/kl/freedom-kl26z/src/CMakeLists.txt
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more contributor
+# license agreements.  See the NOTICE file distributed with this work for
+# additional information regarding copyright ownership.  The ASF licenses this
+# file to you under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License.  You may obtain a copy of
+# the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations under
+# the License.
+#
+# ##############################################################################
+
+set(SRCS kl_boardinitialize.c)
+
+if(CONFIG_BOARDCTL)
+  list(APPEND SRCS kl_appinit.c)
+endif()
+
+if(CONFIG_KL_TSI)
+  list(APPEND SRCS kl_tsi.c)
+endif()
+
+if(CONFIG_KL_SPI0)
+  list(APPEND SRCS kl_spi.c)
+else()
+  if(CONFIG_KL_SPI1)
+    list(APPEND SRCS kl_spi.c)
+  endif()
+endif()
+
+if(CONFIG_ARCH_LEDS)
+  list(APPEND SRCS kl_led.c)
+endif()
+
+if(CONFIG_PWM)
+  list(APPEND SRCS kl_pwm.c)
+endif()
+
+target_sources(board PRIVATE ${SRCS})
+
+set_property(GLOBAL PROPERTY LD_SCRIPT
+                             "${NUTTX_BOARD_DIR}/scripts/freedom-kl26z.ld")

boards/arm/kl/teensy-lc/CMakeLists.txt

@@ -0,0 +1,23 @@
+# ##############################################################################
+# boards/arm/kl/teensy-lc/CMakeLists.txt
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more contributor
+# license agreements.  See the NOTICE file distributed with this work for
+# additional information regarding copyright ownership.  The ASF licenses this
+# file to you under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License.  You may obtain a copy of
+# the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations under
+# the License.
+#
+# ##############################################################################
+
+add_subdirectory(src)

boards/arm/kl/teensy-lc/src/CMakeLists.txt

@@ -0,0 +1,48 @@
+# ##############################################################################
+# boards/arm/kl/teensy-lc/src/CMakeLists.txt
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more contributor
+# license agreements.  See the NOTICE file distributed with this work for
+# additional information regarding copyright ownership.  The ASF licenses this
+# file to you under the Apache License, Version 2.0 (the "License"); you may not
+# use this file except in compliance with the License.  You may obtain a copy of
+# the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations under
+# the License.
+#
+# ##############################################################################
+
+set(SRCS kl_boardinitialize.c)
+
+if(CONFIG_BOARDCTL)
+  list(APPEND SRCS kl_appinit.c)
+endif()
+
+if(CONFIG_KL_SPI0)
+  list(APPEND SRCS kl_spi.c)
+else()
+  if(CONFIG_KL_SPI1)
+    list(APPEND SRCS kl_spi.c)
+  endif()
+endif()
+
+if(CONFIG_ARCH_LEDS)
+  list(APPEND SRCS kl_led.c)
+endif()
+
+if(CONFIG_PWM)
+  list(APPEND SRCS kl_pwm.c)
+endif()
+
+target_sources(board PRIVATE ${SRCS})
+
+set_property(GLOBAL PROPERTY LD_SCRIPT
+                             "${NUTTX_BOARD_DIR}/scripts/teensy-lc.ld")

boards/xtensa/esp32s2/common/scripts/esp32s2_sections.ld

@@ -180,6 +180,7 @@ SECTIONS
     *libarch.a:*rtc_init.*(.text .text.* .literal .literal.*)
     *libarch.a:*rtc_sleep.*(.text .text.* .literal .literal.*)
     *libarch.a:*rtc_time.*(.text .text.* .literal .literal.*)
+    *libarch.a:*sleep_modes.*(.text .text.* .literal .literal.*)
     *libarch.a:*regi2c_ctrl.*(.text .text.* .literal .literal.*)
     *libarch.a:*uart_hal_iram.*(.text .text.* .literal .literal.*)
     *libarch.a:*wdt_hal_iram.*(.text .text.* .literal .literal.*)
@@ -354,6 +355,7 @@ SECTIONS
     *libarch.a:*rtc_clk_init.*(.rodata .rodata.*)
     *libarch.a:*rtc_sleep.*(.rodata .rodata.*)
     *libarch.a:*rtc_time.*(.rodata .rodata.*)
+    *libarch.a:*sleep_modes.*(.rodata .rodata.*)
     *libarch.a:*regi2c_ctrl.*(.rodata .rodata.*)
     *libarch.a:*uart_hal_iram.*(.rodata .rodata.*)
     *libarch.a:*wdt_hal_iram.*(.rodata .rodata.*)
@@ -606,6 +608,7 @@ SECTIONS
   {
     . = ALIGN(4);
     *(.rtc.literal .rtc.text)
+    *(.rtc.literal* .rtc.text*)
   } >rtc_iram_seg AT>ROM
 
   .rtc.dummy (NOLOAD) :
@@ -622,11 +625,13 @@ SECTIONS
   .rtc.bss (NOLOAD) :
   {
     *(.rtc.bss)
+    *(.rtc.bss*)
   } >rtc_slow_seg
 
   .rtc.data :
   {
     . = ALIGN(4);
+    _rtc_data_start = ABSOLUTE(.);
     *(.rtc.data)
     *(.rtc.data.*)
     *(.rtc.rodata)
@@ -638,6 +643,17 @@ SECTIONS
     _srtcheap = ABSOLUTE(.);
   } >rtc_slow_seg AT>ROM
 
+  .rtc.force_slow :
+  {
+    . = ALIGN(4);
+    *(.rtc.force_slow .rtc.force_slow.*)
+    . = ALIGN(4);
+    _rtc_force_slow_end = ABSOLUTE(.);
+  } >rtc_slow_seg AT>ROM
+
+  /* Get size of rtc slow data */
+  _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start);
+
   /* This section holds RTC data that should have fixed addresses.
    * The data are not initialized at power-up and are retained during deep sleep.
    */

boards/xtensa/esp32s2/esp32s2-saola-1/configs/pm/defconfig

@@ -0,0 +1,45 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_ARCH_LEDS is not set
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+CONFIG_ARCH="xtensa"
+CONFIG_ARCH_BOARD="esp32s2-saola-1"
+CONFIG_ARCH_BOARD_COMMON=y
+CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y
+CONFIG_ARCH_CHIP="esp32s2"
+CONFIG_ARCH_CHIP_ESP32S2=y
+CONFIG_ARCH_CHIP_ESP32S2WROVER=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH_XTENSA=y
+CONFIG_BOARD_LOOPSPERMSEC=16717
+CONFIG_BUILTIN=y
+CONFIG_ESP32S2_UART0=y
+CONFIG_FS_PROCFS=y
+CONFIG_FS_PROCFS_REGISTER=y
+CONFIG_IDLETHREAD_STACKSIZE=3072
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INIT_STACKSIZE=3072
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LINE_MAX=64
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
+CONFIG_PM=y
+CONFIG_PM_GOVERNOR_EXPLICIT_RELAX=-1
+CONFIG_PM_GOVERNOR_GREEDY=y
+CONFIG_PM_PROCFS=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=114688
+CONFIG_RAM_START=0x20000000
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_SYSLOG_BUFFER=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_UART0_SERIAL_CONSOLE=y

boards/xtensa/esp32s3/common/Kconfig

@@ -78,195 +78,6 @@ config ESP32S3_SPIFLASH_LITTLEFS
 
 endchoice # ESP32S3_SPIFLASH_FS
 
-if PM
-
-config PM_EXT1_WAKEUP
-	bool "PM EXT1 Wakeup"
-	default n
-	---help---
-		Enable EXT1 wakeup functionality.
-		This allows the system to wake up from PM_STANDBY or PM_SLEEP
-		when a GPIO pin configured as an EXT1 wakeup source is triggered.
-
-if PM_EXT1_WAKEUP
-
-menu "PM EXT1 Wakeup Sources"
-
-config PM_EXT1_WAKEUP_RTC_GPIO0
-	bool "RTC_GPIO0"
-	default n
-	---help---
-		Enable RTC GPIO0 as an EXT1 wakeup source.
-
-config PM_EXT1_WAKEUP_RTC_GPIO1
-	bool "RTC_GPIO1"
-	default n
-	---help---
-		Enable RTC GPIO1 as an EXT1 wakeup source.
-
-config PM_EXT1_WAKEUP_RTC_GPIO2
-	bool "RTC_GPIO2"
-	default n
-	---help---
-		Enable RTC GPIO2 as an EXT1 wakeup source.
-
-config PM_EXT1_WAKEUP_RTC_GPIO3
-	bool "RTC_GPIO3"
-	default n
-	---help---
-		Enable RTC GPIO3 as an EXT1 wakeup source.
-
-config PM_EXT1_WAKEUP_RTC_GPIO4
-	bool "RTC_GPIO4"
-	default n
-	---help---
-		Enable RTC GPIO4 as an EXT1 wakeup source.
-
-config PM_EXT1_WAKEUP_RTC_GPIO5
-	bool "RTC_GPIO5"
-	default n
-	---help---
-		Enable RTC GPIO5 as an EXT1 wakeup source.
-
-config PM_EXT1_WAKEUP_RTC_GPIO6
-	bool "RTC_GPIO6"
-	default n
-	---help---
-		Enable RTC GPIO6 as an EXT1 wakeup source.
-
-config PM_EXT1_WAKEUP_RTC_GPIO7
-	bool "RTC_GPIO7"
-	default n
-	---help---
-		Enable RTC GPIO7 as an EXT1 wakeup source.
-
-config PM_EXT1_WAKEUP_RTC_GPIO8
-	bool "RTC_GPIO8"
-	default n
-	---help---
-		Enable RTC GPIO8 as an EXT1 wakeup source.
-
-config PM_EXT1_WAKEUP_RTC_GPIO9
-	bool "RTC_GPIO9"
-	default n
-	---help---
-		Enable RTC GPIO9 as an EXT1 wakeup source.
-
-config PM_EXT1_WAKEUP_RTC_GPIO10
-	bool "RTC_GPIO10"
-	default n
-	---help---
-		Enable RTC GPIO10 as an EXT1 wakeup source.
-
-config PM_EXT1_WAKEUP_RTC_GPIO11
-	bool "RTC_GPIO11"
-	default n
-	---help---
-		Enable RTC GPIO11 as an EXT1 wakeup source.
-
-config PM_EXT1_WAKEUP_RTC_GPIO12
-	bool "RTC_GPIO12"
-	default n
-	---help---
-		Enable RTC GPIO12 as an EXT1 wakeup source.
-
-config PM_EXT1_WAKEUP_RTC_GPIO13
-	bool "RTC_GPIO13"
-	default n
-	---help---
-		Enable RTC GPIO13 as an EXT1 wakeup source.
-
-config PM_EXT1_WAKEUP_RTC_GPIO14
-	bool "RTC_GPIO14"
-	default n
-	---help---
-		Enable RTC GPIO14 as an EXT1 wakeup source.
-
-config PM_EXT1_WAKEUP_RTC_GPIO15
-	bool "RTC_GPIO15"
-	default n
-	---help---
-		Enable RTC GPIO15 as an EXT1 wakeup source.
-
-config PM_EXT1_WAKEUP_RTC_GPIO16
-	bool "RTC_GPIO16"
-	default n
-	---help---
-		Enable RTC GPIO16 as an EXT1 wakeup source.
-
-config PM_EXT1_WAKEUP_RTC_GPIO17
-	bool "RTC_GPIO17"
-	default n
-	---help---
-		Enable RTC GPIO17 as an EXT1 wakeup source.
-
-config PM_EXT1_WAKEUP_RTC_GPIO18
-	bool "RTC_GPIO18"
-	default n
-	---help---
-		Enable RTC GPIO18 as an EXT1 wakeup source.
-
-config PM_EXT1_WAKEUP_RTC_GPIO19
-	bool "RTC_GPIO19"
-	default n
-	---help---
-		Enable RTC GPIO19 as an EXT1 wakeup source.
-
-config PM_EXT1_WAKEUP_RTC_GPIO20
-	bool "RTC_GPIO20"
-	default n
-	---help---
-		Enable RTC GPIO20 as an EXT1 wakeup source.
-
-endmenu # PM_EXT1_WAKEUP_SOURCES
-
-
-config PM_EXT1_WAKEUP_TRIGGER_MODE
-	int "PM EXT1 Wakeup Trigger Mode"
-	range 0 1
-	default 0
-	---help---
-		Select EXT1 wakeup mode:
-		0 = Wakeup when any selected GPIO is LOW
-		1 = Wakeup when any selected GPIO is HIGH
-
-endif # PM_EXT1_WAKEUP
-
-config PM_ULP_WAKEUP
-	bool "PM ULP Wakeup"
-	default n
-	---help---
-		Enable ULP RISC-V coprocessor wakeup functionality.
-		This allows the system to wake up from PM_STANDBY or PM_SLEEP
-		when ULP app triggers HP core to wakeup with "ulp_riscv_wakeup_main_processor"
-		call on ULP app.
-
-config PM_ALARM_SEC
-	int "PM_STANDBY delay (seconds)"
-	default 15
-	---help---
-		Number of seconds to wait in PM_STANDBY before going to PM_STANDBY mode.
-
-config PM_ALARM_NSEC
-	int "PM_STANDBY delay (nanoseconds)"
-	default 0
-	---help---
-		Number of additional nanoseconds to wait in PM_STANDBY before going to PM_STANDBY mode.
-
-config PM_SLEEP_WAKEUP_SEC
-	int "PM_SLEEP delay (seconds)"
-	default 20
-	---help---
-		Number of seconds to wait in PM_SLEEP.
-
-config PM_SLEEP_WAKEUP_NSEC
-	int "PM_SLEEP delay (nanoseconds)"
-	default 0
-	---help---
-		Number of additional nanoseconds to wait in PM_SLEEP.
-
-endif # PM
-
 config ESP32S3_BOARD_I2C
 	bool
 	default y if ESP32S3_I2C0 || ESP32S3_I2C1

boards/xtensa/esp32s3/common/scripts/esp32s3_sections.ld

@@ -291,6 +291,7 @@ SECTIONS
     *libarch.a:*log_write.*(.literal.esp_log_writev .text.esp_log_writev)
     *libarch.a:*cpu_region_protect.*(.text .text.* .literal .literal.*)
     *libarch.a:*mspi_timing_tuning.*(.text .text.* .literal .literal.*)
+    *libarch.a:*mspi_timing_config.*(.text .text.* .literal .literal.*)
     *libarch.a:*esp_rom_cache_esp32s2_esp32s3.*(.literal .text .literal.* .text.*)
     *libarch.a:*flash_qio_mode.*(.text .text.* .literal .literal.*)
     *libarch.a:*spi_flash_wrap.*(.text .text.* .literal .literal.*)
@@ -500,6 +501,7 @@ SECTIONS
     *libarch.a:*log_noos.*(.rodata .rodata.*)
     *libarch.a:*cpu_region_protect.*(.rodata .rodata.*)
     *libarch.a:*mspi_timing_tuning.*(.rodata .rodata.*)
+    *libarch.a:*mspi_timing_config.*(.rodata .rodata.*)
 #ifdef CONFIG_ESP32S3_SPIRAM_MODE_QUAD
     *libarch.a:esp32s3_psram_quad.*(.rodata .rodata.*)
 #endif
@@ -763,7 +765,10 @@ SECTIONS
   .rtc.text :
   {
     . = ALIGN(4);
+    _rtc_fast_start = ABSOLUTE(.);
+    _rtc_text_start = ABSOLUTE(.);
     *(.rtc.literal .rtc.text)
+    _rtc_text_end = ABSOLUTE(.);
   } >rtc_iram_seg AT>ROM
 
   .rtc.dummy (NOLOAD) :
@@ -782,6 +787,21 @@ SECTIONS
     *(.rtc.bss)
   } >rtc_slow_seg
 
+
+  /* This section located in RTC FAST Memory area.
+   * It holds data marked with RTC_FAST_ATTR attribute.
+   * See the file "esp_attr.h" for more information.
+   */
+  .rtc.force_fast :
+  {
+    . = ALIGN(4);
+    _rtc_force_fast_start = ABSOLUTE(.);
+    *(.rtc.force_fast .rtc.force_fast.*)
+    . = ALIGN(4);
+    _rtc_force_fast_end = ABSOLUTE(.);
+  } >rtc_slow_seg AT>ROM
+
+
   .rtc.data :
   {
     *(.rtc.data)

cmake/nuttx_kconfig.cmake

@@ -122,59 +122,77 @@ function(nuttx_generate_kconfig)
     REQUIRED
     ARGN
     ${ARGN})
+
+  # Exit early if: - The current directory does NOT contain a CMakeLists.txt
+  # (not an app dir), OR - The output Kconfig already exists in the apps binary
+  # directory
   if(NOT EXISTS "${CMAKE_CURRENT_LIST_DIR}/CMakeLists.txt"
      OR EXISTS "${NUTTX_APPS_BINDIR}/Kconfig")
     return()
   endif()
 
+  # Determine output Kconfig file path
   set(KCONFIG_OUTPUT_FILE)
   if(MENUDESC)
     string(REPLACE "/" "_" KCONFIG_PREFIX ${CMAKE_CURRENT_LIST_DIR})
     if(WIN32)
+      # On Windows, also replace drive letter separators like "C:".
       string(REPLACE ":" "_" KCONFIG_PREFIX ${KCONFIG_PREFIX})
     endif()
+
+    # Output Kconfig file path: <apps_bindir>/<prefix>_Kconfig
     string(APPEND KCONFIG_OUTPUT_FILE ${NUTTX_APPS_BINDIR} "/"
            ${KCONFIG_PREFIX} "_Kconfig")
+
+    # Start a menu block
     file(WRITE ${KCONFIG_OUTPUT_FILE} "menu \"${MENUDESC}\"\n")
   else()
+    # Without MENUDESC, generate the root Kconfig file.
     set(KCONFIG_OUTPUT_FILE ${NUTTX_APPS_BINDIR}/Kconfig)
   endif()
 
-  file(
-    GLOB SUB_CMAKESCRIPTS
-    LIST_DIRECTORIES false
-    ${CMAKE_CURRENT_LIST_DIR} ${CMAKE_CURRENT_LIST_DIR}/*/CMakeLists.txt)
+  # Collect valid directories that contain Kconfig or CMakeLists
+  set(DIR_LIST)
+  foreach(external_dir ${EXTERNAL_DIRECTORIES})
+    get_filename_component(external_reldir "${external_dir}" REALPATH)
+    if(IS_DIRECTORY ${external_reldir})
+      list(APPEND DIR_LIST "${external_reldir}")
+    endif()
+  endforeach()
 
-  if(NOT MENUDESC)
-    set(EXTERNAL_CMAKESCRIPTS)
-    foreach(external_dir ${EXTERNAL_DIRECTORIES})
-      if(EXISTS ${external_dir}/CMakeLists.txt)
-        list(APPEND EXTERNAL_CMAKESCRIPTS "${external_dir}/CMakeLists.txt")
+  # Get all entries directly under the current app directory
+  file(GLOB FIRST_LEVEL_DIRS "${CMAKE_CURRENT_SOURCE_DIR}/*")
+
+  # Add directories that contain either CMakeLists.txt or Kconfig
+  foreach(dir IN LISTS FIRST_LEVEL_DIRS)
+    if(IS_DIRECTORY "${dir}")
+      if(EXISTS "${dir}/CMakeLists.txt" OR EXISTS "${dir}/Kconfig")
+        list(APPEND DIR_LIST "${dir}")
       endif()
-    endforeach()
-  endif()
+    endif()
+  endforeach()
 
-  # we need to recursively generate the Kconfig menus of multi-level
-  # directories.
-  #
-  # when generating a Kconfig file for the current directory, it should include
-  # and invoke all the Kconfig files gathered from its subdirectories.
-  foreach(SUB_CMAKESCRIPT ${SUB_CMAKESCRIPTS} ${EXTERNAL_CMAKESCRIPTS})
-    string(REPLACE "CMakeLists.txt" "Kconfig" SUB_KCONFIG ${SUB_CMAKESCRIPT})
+  # Generate "source" entries for each discovered Kconfig
+  foreach(dir ${DIR_LIST})
+    set(SUB_KCONFIG "${dir}/Kconfig")
     string(REPLACE "/" "_" MENUCONFIG ${SUB_KCONFIG})
     if(WIN32)
       string(REPLACE ":" "_" MENUCONFIG ${MENUCONFIG})
     endif()
-    # check whether the subdirectory will include a generated Kconfig file.
+
+    # Source Kconfig from the corresponding apps binary directory if present
     if(EXISTS ${NUTTX_APPS_BINDIR}/${MENUCONFIG})
       file(APPEND ${KCONFIG_OUTPUT_FILE}
            "source \"${NUTTX_APPS_BINDIR}/${MENUCONFIG}\"\n")
     endif()
+
+    # Source Kconfig from the directory if present
     if(EXISTS ${SUB_KCONFIG})
       file(APPEND ${KCONFIG_OUTPUT_FILE} "source \"${SUB_KCONFIG}\"\n")
     endif()
   endforeach()
 
+  # Close the menu block if MENUDESC was used
   if(MENUDESC)
     file(APPEND ${KCONFIG_OUTPUT_FILE} "endmenu # ${MENUDESC}\n")
   endif()

drivers/pci/pci_qemu_edu.c

@@ -305,7 +305,7 @@ static void pci_qemu_edu_test_dma(FAR struct pci_qemu_edu_priv_s *priv)
 
   pciinfo("Test block checksum 0x%08" PRIx32 "\n", tx_checksum);
   pci_qemu_edu_write_reg64(priv, PCI_QEMU_EDU_REG_DMA_SOURCE,
-                           (uint64_t)test_block);
+                           (uint64_t)(uintptr_t)test_block);
   pci_qemu_edu_write_reg64(priv, PCI_QEMU_EDU_REG_DMA_DEST, dev_addr);
   pci_qemu_edu_write_reg64(priv, PCI_QEMU_EDU_REG_DMA_COUNT,
                            (uint64_t)block_size);
@@ -316,7 +316,7 @@ static void pci_qemu_edu_test_dma(FAR struct pci_qemu_edu_priv_s *priv)
   pciinfo("DMA transfer to device complete.\n");
 
   pci_qemu_edu_write_reg64(priv, PCI_QEMU_EDU_REG_DMA_DEST,
-                           (uint64_t)test_block);
+                           (uint64_t)(uintptr_t)test_block);
   pci_qemu_edu_write_reg64(priv, PCI_QEMU_EDU_REG_DMA_SOURCE, dev_addr);
   pci_qemu_edu_write_reg64(priv, PCI_QEMU_EDU_REG_DMA_COUNT,
                            (uint64_t)block_size);