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arch/avr/src/avrdx: add support for TWI (I2C and SMBus) peripheral
This patch adds support for Two-Wire interface in AVR Dx chips. Only master mode is supported in this version. The driver was tested using TC74Ax thermal sensor and simple application that read the temperature from it. (Driver for the sensor is not in-tree.) Signed-off-by: Kerogit <kr.git@kerogit.eu>
This commit is contained in:
Kerogit
Xiang Xiao
109
Documentation/platforms/avr/avrdx/docs/twi.rst
Normal file
109
Documentation/platforms/avr/avrdx/docs/twi.rst
Normal file
@@ -0,0 +1,109 @@
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===============================
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Two Wire Interface in AVR DA/DB
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===============================
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Two Wire Interface is AVR peripheral capable of supporting both I\ :sup:`2`\ C and SMBus.
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Usage
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=====
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Pointer to initialized ``struct i2c_master_s`` can be obtained using
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.. code-block:: c
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FAR struct i2c_master_s *i2c;
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i2c = avrdx_initialize_twi(0);
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This function will initialize the peripheral based on configuration specified
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via Kconfig. It may be called multiple times, only first call will perform
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the initialization - subsequent calls will only return the pointer.
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Deinitialization is currently not supported.
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The parameter denotes which peripheral is to be initialized. With current chips,
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permitted values are ``0`` and ``1``.
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It is ignored if the chip has only single TWI interface.
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Configuration options
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=====================
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Pin selection
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-------------
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This option makes it possible to choose which I/O pins will be connected
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to the peripheral.
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Mode selection
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--------------
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The peripheral supports Standard, Fast and Fast Plus modes.
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Quick commands
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--------------
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SMBus permits transactions that contain no data. Instead, the R/nW bit
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is interpreted as a single-bit datum by the target device. If this is enabled,
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I\ :sup:`2`\ C messages with zero length are interpreted as quick commands. If not,
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zero-length messages are not permitted and the transmission is rejected
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with ``EINVAL``
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Forbid NOSTART
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--------------
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NuttX upper half of the I\ :sup:`2`\ C driver permits ``I2C_M_NOSTART``
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flag for a message, indicating that the message is not a standalone entity
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but rather a continuation of previous message. Since not all drivers need
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this and program memory space is not unlimited on the chip, this configuration
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option can be used to remove support for such messages.
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Transmission that submits message with this flag will be rejected
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with ``EINVAL`` if this configuration option is set. Enable this only
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if you know internals of I\ :sup:`2`\ C drivers used by your application.
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Limitations
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===========
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Mode and addressing
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-------------------
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Currently, only master mode is supported.
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Only 7-bit addressing is supported. The peripheral does not support 10-bit
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addressing directly and the driver software does currently have no support
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for that either. I\ :sup:`2`\ C messages requesting 10-bit address
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are rejected with ``ENOTSUP``.
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Message limitations
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-------------------
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Maximum message count for single transmission is 127.
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The driver does not support ``I2C_M_NOSTOP`` flag for last submitted message.
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As per rules specified in ``include/nuttx/i2c/i2c_master.h``, the I\ :sup:`2`\ C
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driver lower half is supposed to leave the bus occupied if the last
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of the submitted messages has this ``NOSTOP`` flag set. This driver
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is not capable of doing that.
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Also not supported is ``I2C_M_NOSTART`` flag for first submitted message.
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First message within the transfer always starts with ``START`` condition.
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Messages with zero length (which are only permitted based on configuration
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- see above) may not specify ``I2C_M_NOSTART`` nor ``I2C_M_NOSTOP``.
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(Such a message is interpreted as a quick command and quick commands
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must end with a ``STOP`` condition according to the chip's documentation.)
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Inactivity timeout
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------------------
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The driver configures timeout for bus inactivity during initialization.
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This timeout is used by the hardware to switch its internal state
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from "bus is busy" or "bus is in unknown state" to "bus is idle."
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This transition otherwise only happens after a ``STOP`` condition is detected
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or when forced by software.
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This timeout remains in effect during normal TWI operation as well.
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Such a timeout is defined for SMBus but not for I\ :sup:`2`\ C; nevertheless,
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the driver does not distinguish between the two and the timeout is always
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in place.
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@@ -51,12 +51,13 @@ Peripheral Support
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The following list indicates peripherals supported in NuttX:
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========== ================
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========== =======================
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Peripheral Notes
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========== ================
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========== =======================
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GPIO In board code
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UART See below
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========== ================
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TWI Master only, more below
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========== =======================
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GPIO
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----
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@@ -101,6 +102,12 @@ This for example means that ``USART1`` peripheral will always
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be accessed through ``/dev/ttyS1`` regardless of what other ``USART``
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peripherals are enabled (if any.)
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TWI
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---
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Currently, only master is supported. Implementation details and quick
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usage instructions can be found in :doc:`docs/twi` document.
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Supported Boards
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================
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@@ -71,6 +71,23 @@ config AVR_HAS_PORTG
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bool
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default n
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# Available TWI interfaces and their options (not common for all devices)
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config AVR_HAVE_TWI0_ALT1
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bool
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default n
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---help---
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Chip has alternate pin configuration 1 for TWI0
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config AVR_HAVE_TWI1
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bool
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default n
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config AVR_HAVE_TWI1_ALT1
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bool
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default n
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---help---
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Chip has alternate pin configuration 1 for TW1
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choice
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prompt "Atmel AVR DA/DB chip selection"
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default ARCH_CHIP_AVR128DA28
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@@ -96,6 +113,9 @@ config ARCH_CHIP_AVR128DA64
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select AVR_HAS_PORTB
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select AVR_HAS_PORTE
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select AVR_HAS_PORTG
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select AVR_HAVE_TWI0_ALT1
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select AVR_HAVE_TWI1
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select AVR_HAVE_TWI1_ALT1
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---help---
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Atmel AVR128DA64 8-bit AVR.
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@@ -113,6 +133,9 @@ config ARCH_CHIP_AVR128DB64
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select AVR_HAS_PORTB
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select AVR_HAS_PORTE
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select AVR_HAS_PORTG
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select AVR_HAVE_TWI0_ALT1
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select AVR_HAVE_TWI1
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select AVR_HAVE_TWI1_ALT1
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---help---
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Atmel AVR128DB64 8-bit AVR.
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@@ -328,6 +351,173 @@ config AVR_USART5_NONE
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endchoice
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config AVR_TWI0
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bool "Enable TWI (I2C) driver for interface 0"
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depends on I2C
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---help---
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Enable driver for TWI0
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choice AVR_TWI0_ALT
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prompt "TWI0 pin selection"
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depends on AVR_TWI0
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default AVR_TWI0_ALT0
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---help---
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Select which I/O pins will be driven by TWI0 interface.
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Refer to I/O Multiplexing and Port Multiplexer sections
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in chip documentation for specifics.
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config AVR_TWI0_ALT0
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bool "Default TWI0 pinout"
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config AVR_TWI0_ALT1
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bool "Alternate TWI0 pinout 1"
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depends on AVR_HAVE_TWI0_ALT1
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config AVR_TWI0_ALT2
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bool "Alternate TWI0 pinout 2"
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endchoice
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choice AVR_TWI0_MODE
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prompt "TWI0 mode selection"
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depends on AVR_TWI0
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default AVR_TWI0_MODE_STD
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---help---
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Select TWI0 operating mode.
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config AVR_TWI0_MODE_STD
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bool "Standard mode"
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config AVR_TWI0_MODE_FAST
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bool "Fast mode"
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config AVR_TWI0_MODE_FASTPLUS
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bool "Fast plus mode"
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endchoice
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choice AVR_TWI0_SDAHOLD
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prompt "SDA hold time selection"
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depends on AVR_TWI0
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default AVR_TWI0_SDAHOLD_OFF
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---help---
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Select TWI0 SDA hold time. Refer to Electrical Characteristics
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in chip documentation for details
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config AVR_TWI0_SDAHOLD_OFF
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bool "Hold time OFF"
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config AVR_TWI0_SDAHOLD_50NS
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bool "50ns (short)"
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config AVR_TWI0_SDAHOLD_300NS
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bool "300ns (meets SMBus 2.0 specs under typical conditions)"
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config AVR_TWI0_SDAHOLD_500NS
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bool "500ns (meets SMBus 2.0 specs across all corners)"
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endchoice
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config AVR_TWI1
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bool "Enable TWI (I2C) driver for interface 1"
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depends on I2C
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depends on AVR_HAVE_TWI1
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---help---
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Enable driver for TWI0
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choice AVR_TWI1_ALT
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prompt "TWI0 pin selection"
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depends on AVR_TWI1
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default AVR_TWI1_ALT0
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---help---
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Select which I/O pins will be driven by TWI1 interface.
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Refer to I/O Multiplexing and Port Multiplexer sections
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in chip documentation for specifics.
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config AVR_TWI1_ALT0
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bool "Default TWI1 pinout"
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config AVR_TWI1_ALT1
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bool "Alternate TWI1 pinout 1"
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depends on AVR_HAVE_TWI1_ALT1
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config AVR_TWI1_ALT2
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bool "Alternate TWI1 pinout 2"
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endchoice
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choice AVR_TWI1_MODE
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prompt "TWI1 mode selection"
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depends on AVR_TWI1
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default AVR_TWI1_MODE_STD
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---help---
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Select TWI1 operating mode.
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config AVR_TWI1_MODE_STD
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bool "Standard mode"
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config AVR_TWI1_MODE_FAST
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bool "Fast mode"
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config AVR_TWI1_MODE_FASTPLUS
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bool "Fast plus mode"
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endchoice
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choice AVR_TWI1_SDAHOLD
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prompt "SDA hold time selection"
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depends on AVR_TWI1
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default AVR_TWI1_SDAHOLD_OFF
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---help---
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Select TWI1 SDA hold time. Refer to Electrical Characteristics
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in chip documentation for details.
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config AVR_TWI1_SDAHOLD_OFF
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bool "Hold time OFF"
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config AVR_TWI1_SDAHOLD_50NS
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bool "50ns (short)"
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config AVR_TWI1_SDAHOLD_300NS
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bool "300ns (meets SMBus 2.0 specs under typical conditions)"
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config AVR_TWI1_SDAHOLD_500NS
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bool "500ns (meets SMBus 2.0 specs across all corners)"
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endchoice
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if AVR_TWI0 || AVR_TWI1
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config AVR_TWI_QCEN
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bool "Quick command enabled"
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default false
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---help---
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Enable Quick Command mode. In this mode, messages with
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zero-length data are interpreted as SMBus quick commands
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which use R/non-W bit as a single bit of data transmitted
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(written) to the target device.
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If not enabled, attempt to transmit message with zero-length
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is an error rejected with EINVAL.
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config AVR_TWI_FORBID_NOSTART
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bool "Forbid I2C NOSTART to save flash space"
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default false
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---help---
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NuttX I2C message can be submitted with a flag that indicates
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that the caller does want that message processed without
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issuing start condition on the BUS (presumably with previous
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message set to not issue STOP nor REPEATED START condition.)
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Since not many drivers require this, it is possible to exclude
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support for this flag from the build. Any I2C device driver
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that attempt to submit such message will receive EINVAL.
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If you know that your system's drivers do not use I2C_M_NOSTART,
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you can enable this option to save around 120 bytes of flash space.
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endif
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endmenu # AVR DA/DB Peripheral Selections
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choice
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@@ -54,6 +54,7 @@ CHIP_ASRCS = avrdx_exceptions.S
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CHIP_CSRCS = avrdx_lowconsole.c avrdx_lowinit.c avrdx_init.c
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CHIP_CSRCS += avrdx_serial.c avrdx_serial_early.c
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CHIP_CSRCS += avrdx_peripherals.c
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CHIP_CSRCS += avrdx_twi.c
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# Configuration-dependent files
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1393
arch/avr/src/avrdx/avrdx_twi.c
Normal file
1393
arch/avr/src/avrdx/avrdx_twi.c
Normal file
File diff suppressed because it is too large
Load Diff
94
arch/avr/src/avrdx/avrdx_twi.h
Normal file
94
arch/avr/src/avrdx/avrdx_twi.h
Normal file
@@ -0,0 +1,94 @@
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/****************************************************************************
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* arch/avr/src/avrdx/avrdx_twi.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
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* License. You may obtain a copy of the License at
|
||||
*
|
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* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
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*
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****************************************************************************/
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#ifndef __ARCH_AVR_SRC_AVRDX_AVRDX_TWI_H
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#define __ARCH_AVR_SRC_AVRDX_AVRDX_TWI_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "avrdx_iodefs.h"
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#include <nuttx/i2c/i2c_master.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Base address of TWIn peripheral. TWI index corresponds to the location
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* of its I/O registers in memory. Ignores its parameter if the chip
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* only has one TWI.
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*/
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#ifdef CONFIG_AVR_HAVE_TWI1
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# define AVRDX_TWI(n) (*(avr_twi_t *) (0x0900 + n * 0x20))
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#else
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# define AVRDX_TWI(n) (*(avr_twi_t *) (0x0900 + 0 * 0x20))
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#endif
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Inline Functions
|
||||
****************************************************************************/
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/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
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||||
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/****************************************************************************
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* Name: avrdx_initialize_twi
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*
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* Description:
|
||||
* Initializer for TWI device. Allocates data structures and configures
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* the peripheral. May be called multiple times by multiple drivers using
|
||||
* the bus.
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*
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* Input Parameters:
|
||||
* Peripheral number, ignored if the chip only has single TWI
|
||||
*
|
||||
* Returned Value:
|
||||
* Initialized structure cast to i2c_master_s
|
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*
|
||||
****************************************************************************/
|
||||
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||||
FAR struct i2c_master_s *avrdx_initialize_twi(uint8_t twi_n);
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||||
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||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_AVR_SRC_AVRDX_AVRDX_TWI_H */
|
||||
@@ -52,6 +52,12 @@
|
||||
#define PORTMUX_USART2_NONE_GC (PORTMUX_USART2_1_bm | PORTMUX_USART2_0_bm)
|
||||
#define PORTMUX_USART2_GM (PORTMUX_USART2_1_bm | PORTMUX_USART2_0_bm)
|
||||
|
||||
/* PORTMUX.TWIROUTEA */
|
||||
|
||||
#define PORTMUX_TWI0_DEFAULT_GC (0)
|
||||
#define PORTMUX_TWI0_ALT2_GC = (PORTMUX_TWI0_1_bm)
|
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#define PORTMUX_TWI0_GM (PORTMUX_TWI0_1_bm | PORTMUX_TWI0_0_bm)
|
||||
|
||||
/* PORT.PINCONFIG */
|
||||
|
||||
#define PORT_ISC_GM ( PORT_ISC_0_bm | PORT_ISC_1_bm | PORT_ISC_2_bm )
|
||||
@@ -105,6 +111,35 @@
|
||||
#define USART_CHSIZE_7BIT_GC (USART_CHSIZE_1_bm)
|
||||
#define USART_CHSIZE_8BIT_GC (USART_CHSIZE_1_bm | USART_CHSIZE_0_bm)
|
||||
|
||||
/* TWI.MCTRLA */
|
||||
|
||||
#define TWI_FMPEN_ON_GC (TWI_FMPEN_bm)
|
||||
|
||||
#define TWI_SDAHOLD_OFF_GC (0)
|
||||
#define TWI_SDAHOLD_50NS_GC (TWI_SDAHOLD_0_bm)
|
||||
#define TWI_SDAHOLD_300NS_GC (TWI_SDAHOLD_1_bm)
|
||||
#define TWI_SDAHOLD_500NS_GC (TWI_SDAHOLD_1_bm | TWI_SDAHOLD_0_bm)
|
||||
|
||||
#define TWI_TIMEOUT_200US_GC (TWI_TIMEOUT_1_bm | TWI_TIMEOUT_0_bm)
|
||||
|
||||
/* TWI.MCTRLB */
|
||||
|
||||
#define TWI_MCMD_NOACT_GC (0)
|
||||
#define TWI_MCMD_REPSTART_GC (TWI_MCMD_0_bm)
|
||||
#define TWI_MCMD_RECVTRANS_GC (TWI_MCMD_1_bm)
|
||||
#define TWI_MCMD_STOP_GC (TWI_MCMD_0_bm | TWI_MCMD_1_bm)
|
||||
|
||||
#define TWI_ACKACT_ACK_GC (0)
|
||||
#define TWI_ACKACT_NACK_GC (TWI_ACKACT_bm)
|
||||
|
||||
/* TWI.MSTATUS */
|
||||
|
||||
#define TWI_BUSSTATE_UNKNOWN_GC (0)
|
||||
#define TWI_BUSSTATE_IDLE_GC (TWI_BUSSTATE_0_bm)
|
||||
#define TWI_BUSSTATE_OWNER_GC (TWI_BUSSTATE_1_bm)
|
||||
#define TWI_BUSSTATE_BUSY_GC (TWI_BUSSTATE_1_bm | TWI_BUSSTATE_0_bm)
|
||||
#define TWI_BUSSTATE_GM (TWI_BUSSTATE_1_bm | TWI_BUSSTATE_0_bm)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
@@ -130,6 +165,26 @@ typedef struct avr_usart_struct
|
||||
register8_t reserved_1[1];
|
||||
} avr_usart_t;
|
||||
|
||||
typedef struct avr_twi_struct
|
||||
{
|
||||
register8_t CTRLA; /* Control A */
|
||||
register8_t DUALCTRL; /* Dual Control */
|
||||
register8_t DBGCTRL; /* Debug Control Register */
|
||||
register8_t MCTRLA; /* Host Control A */
|
||||
register8_t MCTRLB; /* Host Control B */
|
||||
register8_t MSTATUS; /* Host Status */
|
||||
register8_t MBAUD; /* Host Baud Rate Control */
|
||||
register8_t MADDR; /* Host Address */
|
||||
register8_t MDATA; /* Host Data */
|
||||
register8_t SCTRLA; /* Client Control A */
|
||||
register8_t SCTRLB; /* Client Control B */
|
||||
register8_t SSTATUS; /* Client Status */
|
||||
register8_t SADDR; /* Client Address */
|
||||
register8_t SDATA; /* Client Data */
|
||||
register8_t SADDRMASK; /* Client Address Mask */
|
||||
register8_t reserved_1[1];
|
||||
} avr_twi_t;
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
@@ -71,6 +71,18 @@
|
||||
#define PORTMUX_USART5_NONE_GC (PORTMUX_USART5_1_bm | PORTMUX_USART5_0_bm)
|
||||
#define PORTMUX_USART5_GM (PORTMUX_USART5_1_bm | PORTMUX_USART5_0_bm)
|
||||
|
||||
/* PORTMUX.TWIROUTEA */
|
||||
|
||||
#define PORTMUX_TWI0_DEFAULT_GC (0)
|
||||
#define PORTMUX_TWI0_ALT1_GC = (PORTMUX_TWI0_0_bm)
|
||||
#define PORTMUX_TWI0_ALT2_GC = (PORTMUX_TWI0_1_bm)
|
||||
#define PORTMUX_TWI0_GM (PORTMUX_TWI0_1_bm | PORTMUX_TWI0_0_bm)
|
||||
|
||||
#define PORTMUX_TWI1_DEFAULT_GC (0)
|
||||
#define PORTMUX_TWI1_ALT1_GC = (PORTMUX_TWI1_0_bm)
|
||||
#define PORTMUX_TWI1_ALT2_GC = (PORTMUX_TWI1_1_bm)
|
||||
#define PORTMUX_TWI1_GM (PORTMUX_TWI1_1_bm | PORTMUX_TWI1_0_bm)
|
||||
|
||||
/* PORT.PINCONFIG */
|
||||
|
||||
#define PORT_ISC_GM ( PORT_ISC_0_bm | PORT_ISC_1_bm | PORT_ISC_2_bm )
|
||||
@@ -124,6 +136,35 @@
|
||||
#define USART_CHSIZE_7BIT_GC (USART_CHSIZE_1_bm)
|
||||
#define USART_CHSIZE_8BIT_GC (USART_CHSIZE_1_bm | USART_CHSIZE_0_bm)
|
||||
|
||||
/* TWI.MCTRLA */
|
||||
|
||||
#define TWI_FMPEN_ON_GC (TWI_FMPEN_bm)
|
||||
|
||||
#define TWI_SDAHOLD_OFF_GC (0)
|
||||
#define TWI_SDAHOLD_50NS_GC (TWI_SDAHOLD_0_bm)
|
||||
#define TWI_SDAHOLD_300NS_GC (TWI_SDAHOLD_1_bm)
|
||||
#define TWI_SDAHOLD_500NS_GC (TWI_SDAHOLD_1_bm | TWI_SDAHOLD_0_bm)
|
||||
|
||||
#define TWI_TIMEOUT_200US_GC (TWI_TIMEOUT_1_bm | TWI_TIMEOUT_0_bm)
|
||||
|
||||
/* TWI.MCTRLB */
|
||||
|
||||
#define TWI_MCMD_NOACT_GC (0)
|
||||
#define TWI_MCMD_REPSTART_GC (TWI_MCMD_0_bm)
|
||||
#define TWI_MCMD_RECVTRANS_GC (TWI_MCMD_1_bm)
|
||||
#define TWI_MCMD_STOP_GC (TWI_MCMD_0_bm | TWI_MCMD_1_bm)
|
||||
|
||||
#define TWI_ACKACT_ACK_GC (0)
|
||||
#define TWI_ACKACT_NACK_GC (TWI_ACKACT_bm)
|
||||
|
||||
/* TWI.MSTATUS */
|
||||
|
||||
#define TWI_BUSSTATE_UNKNOWN_GC (0)
|
||||
#define TWI_BUSSTATE_IDLE_GC (TWI_BUSSTATE_0_bm)
|
||||
#define TWI_BUSSTATE_OWNER_GC (TWI_BUSSTATE_1_bm)
|
||||
#define TWI_BUSSTATE_BUSY_GC (TWI_BUSSTATE_1_bm | TWI_BUSSTATE_0_bm)
|
||||
#define TWI_BUSSTATE_GM (TWI_BUSSTATE_1_bm | TWI_BUSSTATE_0_bm)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
@@ -149,6 +190,26 @@ typedef struct avr_usart_struct
|
||||
register8_t reserved_1[1];
|
||||
} avr_usart_t;
|
||||
|
||||
typedef struct avr_twi_struct
|
||||
{
|
||||
register8_t CTRLA; /* Control A */
|
||||
register8_t DUALCTRL; /* Dual Control */
|
||||
register8_t DBGCTRL; /* Debug Control Register */
|
||||
register8_t MCTRLA; /* Host Control A */
|
||||
register8_t MCTRLB; /* Host Control B */
|
||||
register8_t MSTATUS; /* Host Status */
|
||||
register8_t MBAUD; /* Host Baud Rate Control */
|
||||
register8_t MADDR; /* Host Address */
|
||||
register8_t MDATA; /* Host Data */
|
||||
register8_t SCTRLA; /* Client Control A */
|
||||
register8_t SCTRLB; /* Client Control B */
|
||||
register8_t SSTATUS; /* Client Status */
|
||||
register8_t SADDR; /* Client Address */
|
||||
register8_t SDATA; /* Client Data */
|
||||
register8_t SADDRMASK; /* Client Address Mask */
|
||||
register8_t reserved_1[1];
|
||||
} avr_twi_t;
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
@@ -71,6 +71,18 @@
|
||||
#define PORTMUX_USART5_NONE_GC (PORTMUX_USART5_1_bm | PORTMUX_USART5_0_bm)
|
||||
#define PORTMUX_USART5_GM (PORTMUX_USART5_1_bm | PORTMUX_USART5_0_bm)
|
||||
|
||||
/* PORTMUX.TWIROUTEA */
|
||||
|
||||
#define PORTMUX_TWI0_DEFAULT_GC (0)
|
||||
#define PORTMUX_TWI0_ALT1_GC = (PORTMUX_TWI0_0_bm)
|
||||
#define PORTMUX_TWI0_ALT2_GC = (PORTMUX_TWI0_1_bm)
|
||||
#define PORTMUX_TWI0_GM (PORTMUX_TWI0_1_bm | PORTMUX_TWI0_0_bm)
|
||||
|
||||
#define PORTMUX_TWI1_DEFAULT_GC (0)
|
||||
#define PORTMUX_TWI1_ALT1_GC = (PORTMUX_TWI1_0_bm)
|
||||
#define PORTMUX_TWI1_ALT2_GC = (PORTMUX_TWI1_1_bm)
|
||||
#define PORTMUX_TWI1_GM (PORTMUX_TWI1_1_bm | PORTMUX_TWI1_0_bm)
|
||||
|
||||
/* PORT.PINCONFIG */
|
||||
|
||||
#define PORT_ISC_GM ( PORT_ISC_0_bm | PORT_ISC_1_bm | PORT_ISC_2_bm )
|
||||
@@ -124,6 +136,35 @@
|
||||
#define USART_CHSIZE_7BIT_GC (USART_CHSIZE_1_bm)
|
||||
#define USART_CHSIZE_8BIT_GC (USART_CHSIZE_1_bm | USART_CHSIZE_0_bm)
|
||||
|
||||
/* TWI.MCTRLA */
|
||||
|
||||
#define TWI_FMPEN_ON_GC (TWI_FMPEN_bm)
|
||||
|
||||
#define TWI_SDAHOLD_OFF_GC (0)
|
||||
#define TWI_SDAHOLD_50NS_GC (TWI_SDAHOLD_0_bm)
|
||||
#define TWI_SDAHOLD_300NS_GC (TWI_SDAHOLD_1_bm)
|
||||
#define TWI_SDAHOLD_500NS_GC (TWI_SDAHOLD_1_bm | TWI_SDAHOLD_0_bm)
|
||||
|
||||
#define TWI_TIMEOUT_200US_GC (TWI_TIMEOUT_1_bm | TWI_TIMEOUT_0_bm)
|
||||
|
||||
/* TWI.MCTRLB */
|
||||
|
||||
#define TWI_MCMD_NOACT_GC (0)
|
||||
#define TWI_MCMD_REPSTART_GC (TWI_MCMD_0_bm)
|
||||
#define TWI_MCMD_RECVTRANS_GC (TWI_MCMD_1_bm)
|
||||
#define TWI_MCMD_STOP_GC (TWI_MCMD_0_bm | TWI_MCMD_1_bm)
|
||||
|
||||
#define TWI_ACKACT_ACK_GC (0)
|
||||
#define TWI_ACKACT_NACK_GC (TWI_ACKACT_bm)
|
||||
|
||||
/* TWI.MSTATUS */
|
||||
|
||||
#define TWI_BUSSTATE_UNKNOWN_GC (0)
|
||||
#define TWI_BUSSTATE_IDLE_GC (TWI_BUSSTATE_0_bm)
|
||||
#define TWI_BUSSTATE_OWNER_GC (TWI_BUSSTATE_1_bm)
|
||||
#define TWI_BUSSTATE_BUSY_GC (TWI_BUSSTATE_1_bm | TWI_BUSSTATE_0_bm)
|
||||
#define TWI_BUSSTATE_GM (TWI_BUSSTATE_1_bm | TWI_BUSSTATE_0_bm)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
@@ -149,6 +190,26 @@ typedef struct avr_usart_struct
|
||||
register8_t reserved_1[1];
|
||||
} avr_usart_t;
|
||||
|
||||
typedef struct avr_twi_struct
|
||||
{
|
||||
register8_t CTRLA; /* Control A */
|
||||
register8_t DUALCTRL; /* Dual Control */
|
||||
register8_t DBGCTRL; /* Debug Control Register */
|
||||
register8_t MCTRLA; /* Host Control A */
|
||||
register8_t MCTRLB; /* Host Control B */
|
||||
register8_t MSTATUS; /* Host Status */
|
||||
register8_t MBAUD; /* Host Baud Rate Control */
|
||||
register8_t MADDR; /* Host Address */
|
||||
register8_t MDATA; /* Host Data */
|
||||
register8_t SCTRLA; /* Client Control A */
|
||||
register8_t SCTRLB; /* Client Control B */
|
||||
register8_t SSTATUS; /* Client Status */
|
||||
register8_t SADDR; /* Client Address */
|
||||
register8_t SDATA; /* Client Data */
|
||||
register8_t SADDRMASK; /* Client Address Mask */
|
||||
register8_t reserved_1[1];
|
||||
} avr_twi_t;
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
Reference in New Issue
Block a user