- Added PWM driver support for the RA4M1 microcontroller using the GPT timer.
- This driver supports Saw-wave mode and one of the two output channels (A or B).
- Added necessary configurations in CMakeLists.txt, Kconfig, and Make.defs.
- Created new header file for GPT.
Signed-off-by: leocafonso <leocafonso@gmail.com>
If the initial value of the MSR_IA32_TSC_ADJUST register is not 0 (may be modified by BIOS or bootloader), it may cause timing errors. This commit addressed the issue.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
On newer x86 CPUs, the MSR_IA32_TSC_ADJUST register is utilized to fine-tune the offset of the Time Stamp Counter (TSC). This commit introduces support for MSR_IA32_TSC_ADJUST and enhances the TSC tickless
driver, optimizing its performance.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
This commit aligned the arm64 generic timer count to the tick boundary. Notice that this is just a work-around. We should pass both the current system ticks and the delay ticks as input parameters. But we only have the delay tick here due to the oneshot interfaces.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
Use clock_get_sched_tclock_systime_ticks() to access system ticks
in order to fix the build error and improve code safety.
Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>
The .align N syntax in GHS means the alignment is N Bytes. In GCC
compiler, it means 2**N Bytes. Therefore, .align 32 in GHS and
.align 5 in GCC are equivalent.
Co-authored-by: Chengdong Wang <wangchengdong@lixiang.com>
Signed-off-by: xiezhanpeng3 <xiezhanpeng3@lixiang.com>
The $+0x0 is not accepted by Ghs compiler. Therefore, we change it to a
more common syntax " b ." for endless self loop.
Signed-off-by: xiezhanpeng3 <xiezhanpeng3@lixiang.com>
The GreenHills Compiler uses Unified Assembler Language by default and
it does not recognize .syntax unified instruction. Therefore, remove
them if GHS compiler is used.
Co-authored-by: Chengdong Wang <wangchengdong@lixiang.com>
Signed-off-by: xiezhanpeng3 <xiezhanpeng3@lixiang.com>
The GreenHills Compiler uses different grammer for the .type directive
in asm, this patch adds support for the grammer for arm-v8r.
Similar change for arm-v7r was done in pull request #12883.
Co-authored-by: Chengdong Wang <wangchengdong@lixiang.com>
Signed-off-by: xiezhanpeng3 <xiezhanpeng3@lixiang.com>
We found that specific chip pin definitions were used in the generic UART source file. Since pin definitions vary across different chips, the UART pin definitions have been moved to the corresponding chip-specific directory.
Co-authored-by: Chengdong Wang <wangchengdong@lixiang.com>
Signed-off-by: Qinshuo Duan <duanqinshuo@lixiang.com>
1. up_irq_save should not mask fiq if CONFIG_ARCH_HIPRI_INTERRUPT=y
2. up_irq_save should mask fiq if CONFIG_ARCH_TRUSTZONE_SECURE=y
3. up_irq_save should mask irq if CONFIG_ARCH_TRUSTZONE_SECURE=n
4. add up_secure_irq in arm64
5. add ARCH_HAVE_TRUSTZONE support for ARCH_CORTEX_R82
Signed-off-by: hujun5 <hujun5@xiaomi.com>
MTDIOC_RESET ioctl command executes "Reset Enable" and "Reset Memory"
commands to enter a power-on reset condition.
Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
Fix a transfer issue in the Kinetis DSPI driver when operating
with transmit and receive FIFOs disabled (`MCR[DIS_TXF]=1`,
`MCR[DIS_RXF]=1`). In this mode, the DSPI module behaves as a
simple double-buffered SPI interface without TX staging.
When FIFOs are disabled, `PUSHR` acts as a single 32-bit
command/data register. Partial (16-bit) writes to its upper or
lower halves can result in incomplete or corrupted transfers.
This patch ensures the full 32-bit packet is prepared and
written in a single operation.
* Resolves broken SPI transactions with LAN9252 (EasyCAT).
* Improves reliability in non-FIFO DSPI configurations.
* No impact on DMA or FIFO-enabled modes.
Signed-off-by: trns1997 <trns1997@gmail.com>
In MSS CAN transmit function, the check of net pkt data len is not neccessary. Since there are cases that the pkt len can exceed the expected 16 bytes of can_frame but the pkt is still valid. Such a case is when CONFIG_NET_CAN_RAW_TX_DEADLINE is enabled which has pkt len to become 32 bytes due to cmsghdr overhead.
Signed-off-by: haitomatic <hai.to@unikie.com>
Introduces a very basic frame buffer driver implementation for the RPi4B
which is registered at startup and works with frame buffer graphics
examples (and LVGL). Graphics are displayed on the HDMI0 and HDMI1
output, depending which one is plugged into the display. I have not
tested using both at once, nor does the driver account for that. They
are both referred to as display 0, plane 0 since the RPi4B frame buffer
interface does not seem to have a way of distinguishing.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
Gdbstub demo::
The Qemu version must be above 9.2 to support two serial ports.
One window:
./tools/configure.sh qemu-armv8a:gdbstub; make -j25
qemu-system-aarch64 -cpu cortex-a53 -nographic -machine virt,virtualization=on,gic-version=3 -net none -kernel ./nuttx -serial mon:stdio -serial pty
char device redirected to /dev/pts/27 (label serial1)
- Ready to Boot Primary CPU
- Boot from EL2
- Boot from EL1
- Boot to C runtime for OS Initialize
Another window:
gdb-multiarch nuttx -ex "target remot /dev/pts/27"
GNU gdb (Ubuntu 15.0.50.20240403-0ubuntu1) 15.0.50.20240403-git
Copyright (C) 2024 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Type "show copying" and "show warranty" for details.
This GDB was configured as "x86_64-linux-gnu".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<https://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
<http://www.gnu.org/software/gdb/documentation/>.
For help, type "help".
Type "apropos word" to search for commands related to "word"...
Reading symbols from nuttx...
Remote debugging using /dev/pts/26
gdb_get_registers (state=0x403e1590) at gdbstub/lib_gdbstub.c:1020
1020 reg = state->running_regs;
(gdb) c
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Replace the spinlock/sched_lock pair in xtensa/esp32s2 with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in xtensa/esp32 with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in renesas/rx65n with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in arm64/imx9 with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in arm/stm32 with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in arm/sam34 with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in arm/s32k3xx with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in arm/s32k1xx with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in arm/kinetis with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
Replace the spinlock/sched_lock pair in arm/imx9 with
spin_lock_irqsave_nopreempt() to improve code clarity and consistency.
Signed-off-by: Chengdong Wang wangchengdong@lixiang.com
The Nuttx MSS CAN driver has an exclusive interface to the integrated MSS CAN peripheral residing in Polarfire SoC FPGAs. There are two CAN block 0 and 1 that can be configured for use. In normal mode (non AMP), CAN0 and CAN1 block base register addresses are 0x2010C000UL and 0x2010D000UL.
Signed-off-by: Hai To <hai.to@tii.ae>
By default, the full configured DTCM region is assigned to the heap for
dynamic allocation. In scenarios requiring deterministic memory regions
for static buffers or control structures, you can reduce the heap
allocation to reserve part of DTCM for manual/static use.
This kconfig symbol allows to limit the size.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Updates the SPI Flash driver used for user storage MTD.
Moves ESP32 and ESP32S3 to use common driver.
Updates KConfig options to keep backwards compatibility.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
