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arch/arm64/src/imx9/imx9_flexspi_nor.c: Implement MTDIOC_RESET command
MTDIOC_RESET ioctl command executes "Reset Enable" and "Reset Memory" commands to enter a power-on reset condition. Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
This commit is contained in:
committed by
Xiang Xiao
parent
c793572c1c
commit
97c228c517
@@ -252,6 +252,8 @@
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#define M25P_WECR 0x61 /* 1 Write Enhanched config 0 0 1 */
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#define M25P_RFSR 0x70 /* 1 Read Flag Status Register 0 0 1 */
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#define M25P_4B_ENTER 0xB7 /* 1 Enter 4byte addressing 0 0 0 */
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#define M25P_RSTEN 0x66 /* 1 Reset Enable 0 0 0 */
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#define M25P_RSTMEM 0x99 /* 1 Reset Memory 0 0 0 */
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/* Quad commands */
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#define M25P_Q_FAST_RD 0x6c /* 1 Quad output fast read 4 0 1-256 */
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@@ -281,6 +283,8 @@ enum
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ENTER_DDR,
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READ_FAST,
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ENTER_4BYTE,
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RESET_ENABLE,
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RESET_MEMORY,
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/* Quad SPI instructions */
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@@ -376,6 +380,18 @@ static const uint32_t g_flexspi_nor_lut[][4] =
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FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_DUMMY_SDR, FLEXSPI_1PAD, 0x08,
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FLEXSPI_COMMAND_READ_SDR, FLEXSPI_1PAD, 0x04)
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},
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[RESET_ENABLE] =
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{
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FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_SDR, FLEXSPI_1PAD, M25P_RSTEN,
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FLEXSPI_COMMAND_STOP, FLEXSPI_1PAD, 0x00),
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},
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[RESET_MEMORY] =
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{
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FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_SDR, FLEXSPI_1PAD, M25P_RSTMEM,
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FLEXSPI_COMMAND_STOP, FLEXSPI_1PAD, 0x00),
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},
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};
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/****************************************************************************
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@@ -974,6 +990,23 @@ static int imx9_flexspi_nor_ioctl(struct mtd_dev_s *dev,
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break;
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case MTDIOC_RESET:
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{
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/* Reset the memory */
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imx9_flexspi_nor_write_cmd(priv, RESET_ENABLE);
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up_udelay(1);
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ret = imx9_flexspi_nor_write_cmd(priv, RESET_MEMORY);
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if (ret)
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{
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ferr("reset memory failed\n");
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}
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imx9_flexspi_nor_wait_bus_busy(priv);
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FLEXSPI_SOFTWARE_RESET(priv->flexspi);
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}
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break;
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default:
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ret = -ENOTTY; /* Bad/unsupported command */
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break;
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