prepare for 0.2.6 release

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@255 42af7a65-404d-4744-a932-0658087f49c3

ChangeLog

@@ -3,3 +3,152 @@
 	* Initial Release
 	* Support for Linux user mode simulation and TI
 	  TMS320C5471 (Arm7) provided
+
+0.1.1 2007-03-14  Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* Corrected an error in interrupt level context switching
+	  for C5471
+	* Added fgets() and gets() logic; verified c5471 console read.
+	* Corrected error in reading from the C5471 serial port:
+          Improper use of semaphore can cause deadlock.
+	* Fixed an error in the memory cleanup:  The idle task
+	  cannot take sempahores (because it must always be ready
+	  to run).
+	* Tasks can now accept a configurable maximum number of
+	  input parameters (argc)
+	* _task_init() was divided into separate functions that
+	  require fewer parameters.  This was necessary to keep
+	  the stack usage down for the 8051/2 (which has only
+	  256 bytes of stack).
+	* Attempts to use C5471 console from interrupt handlers
+	  can cause errors. Added a special path for this case.
+	* Refuse calls to sem_wait and sem_trywait from interrupt
+	  handlers.  This was happening because interrupt handlers
+	  were calling printf-like functions.
+	* Added strtok() and strtok_r()
+	* Added a simple shell called nsh (see examples/nsh).
+	* Platform support for 8052 is complete but not stable
+	  when the timer interrupt is enabled.  Seems to be an
+	  issue when SP enters indirect address space.
+	* Documentation updates
+
+0.1.2 2007-03-19  Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* Add dirent.h, opendir(), readdir(), closedir(), etc.
+	* Add strerror()
+	* Added 'ls' command to nsh
+	* Added C5471 watchdog driver
+	* Fixed another bug where free() is called from IDLE task.
+	  Can't do this; the caller must be able to wait for access
+	  to memory.
+	* Fixed bugs associated with debug output:
+          Cannot do dbg() in middle of context switch logic.
+	  because it may require use of semaphores and cause
+	  additional context switches. lldbg() is safe.
+	* Interrupt must be disabled throughout all context switches.
+	* Separated C5471 serial driver; a shareable part is
+	  in drivers/. ; the C5471 specific part is in arch/C5471.
+	  serial.h defines the interface.
+	* Fixed mq_receive() and mq_send() -- bad memcpy()
+	* Fixed C5471 signal deliver logic: use of dbg() and
+          other actions by use signal handler can alter errno.
+          need to protect errno during signal handling.
+	* Fixed uninitialized variable in filesystem that could
+	  cause various problems
+	* Added a test for roundrobin scheduler.
+
+0.2.1 2007-03-22  Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* Fix error in handing signed decimal in vsprintf().
+	* Major restructuring of header files to get closer to
+	  POSIX compliance.
+	* Eliminate compilation warnings that that crept into
+	  recent check-ins
+	* Add kill()
+	* Added support for POSIX timers
+	* Some Documentation updates
+	* Added support for the Neuros OSD / DM320
+
+0.2.2 2007-03-26 Gregory Nutt <spudmonkey@racsa.co.cr>
+	* Created the configs/ directory; separated board configuration
+	  from processor architecture logic
+	* Add memory leak detection test to examples/ostest
+	* Corrected memory leak in OS pthread join logic
+	* Corrected memory leaks in examples/ostest due to failures
+	  to join or detach from pthreads.
+	* Added pthread_once(), pthread_kill(), pthread_sigmask()
+	* Added pthread_barrierattr_*() APIs
+	* Added pthread_barrier_init(), pthread_barrier_destroy(), and
+	  pthread_barrier_wait();
+	* Added pthread barrier test
+	* Added protection so that errno cannot be modified from
+	  interrupt handling.
+	* sched_setparam(), sched_setscheduler() now correctly set
+	  errno; pthread_setscheduler() now returns the correct errno.
+	* Added pthread_setschedprio().
+	* Added directories to hold board-specific header files
+	* Added directories to hold board-specific drivers
+
+0.2.3 2007-03-29 Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* mq_receive and mq_send now return errno's appropriately
+	* mq_receive and mq_send are now correctly awakened by signals.
+	* Fixed an unmatched sched_lock/unlock pair in task_delete().
+	* sched_lock must be called in _exit() because operation of
+	  task_delete() can cause pending tasks to be merged and a
+	  context switch to occur.
+	* Added mq_timedreceive() and mq_timedsend()
+	* signal mask is now inherited by both child tasks and threads.
+	* Improved sharebility of stdout among pthreads (only).  Nothing
+	  was broken, but by moving the mutual exclusion logic to a
+	  higher level, the printf output is more readable.
+	* Fixed a bug in file system cleanup:  A list was being deleted
+	  before the buffers contained in the list.
+	* Fixed a bug in the wait-for-message-queue-not-empty logic.
+	* Added a test of timed mqueue operations; detected and corrected
+	  some mqueue errors.
+	* Identified and corrected a race condition associated with
+	  pthread_join.  In the failure condition, memory was being
+	  deallocated while still in use.
+
+0.2.4 2007-04-28 Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* Verfied c5471 build under Cygwin on WinXP
+	* Makesystem changes to better support different SoCs.
+	* Made arch/c5471/include and arch/dm320/include identical in
+	  preparation for merging into arch/arm
+	* Logic from arch/c5471 and arch/dm320 combined into arch/arm.
+	  arch/c5471 and arch/dm320 are deprecated and will be removed
+	  when the new c5471 and dm320 logic is verified.
+
+0.2.5 2007-05-19 Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* Corrected some build/configuration issues introduced with the
+	  last release.
+	* Added support for the NXP 214x processor on the mcu123.com lpc214x
+	  development board (untested)
+	* Added support for block devices.
+	* Simulated target now exports a VFAT filesystem
+	* Begin support for VFAT filesystem (missing functionalit)
+	* Added mount() and umount()
+	* Fix bug in memcmp return value
+	* Fix errors in timeslice calculation (several places)
+	* Added missing irqrestore() in timer_deletall().
+	* close() was not closing the underlying device.
+	* Added fsync()
+	* Added strspn() and strcspn()
+
+0.2.6 2007-05-26 Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* Added unlink(), mkdir(), rmdir(), and rename()
+	* Fixed several serious FAT errors with oflags handling (&& instead of &)
+	* Added FAT support for unlink(), mkdir(), rmdir(), and rename
+	* Added FAT support for opendir(), closedir(), readdir(), seekdir(),
+	  telldir(), rewindir().
+	* Fixed ARM compilation errors introduced in 0.2.5 (that is what I get
+	  for only testing on the simulation).
+
+0.2.7 2007-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* Started m68322
+

Documentation/NuttX.html

@@ -3,73 +3,606 @@
 <title>NuttX</title>
 </head>
 <body background="backgd.gif">
-<hr>
-<hr>
-<center><h1><i>Under Construction</i></h1></center>
-<hr>
-<hr>
-<h1>Overview</h1>
+<hr><hr>
+<table width ="100%">
+  <tr align="center" bgcolor="#e4e4e4">
+    <td>
+      <h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
+      <p>Last Updated: May 26, 2007</p>
+    </td>
+  </tr>
+</table>
+<hr><hr>
+<table width ="100%">
+  <tr bgcolor="#e4e4e4">
+    <td>
+  <h1>Table of Contents</h1>
+    </td>
+  </tr>
+</table>
+
+<center><table width ="80%">
+<tr>
+<td>
+<table>
+<tr>
+  <td><img src="favicon.ico"></td>
+  <td><a href="#overview">Overview</a></td>
+</tr>
+<tr>
+  <td><img src="favicon.ico"></td>
+  <td><a href="#downloads">Downloads</a></td>
+</tr>
+<tr>
+  <td><img src="favicon.ico"></td>
+  <td><a href="#platforms">Supported Platforms</a></td>
+</tr>
+<tr>
+  <td><img src="favicon.ico"></td>
+  <td><a href="#footprint">Memory Footprint</a></td>
+</tr>
+<tr>
+  <td><img src="favicon.ico"></td>
+  <td><a href="#licensing">Licensing</a></td>
+</tr>
+<tr>
+  <td><img src="favicon.ico"></td>
+  <td><a href="#history">Release History</a></td>
+</tr>
+<tr>
+  <td><img src="favicon.ico"></td>
+  <td><a href="#documentation">Other Documentation</a></td>
+</tr>
+</table>
+</td>
+</td>
+</table></center>
+
+<table width ="100%">
+  <tr bgcolor="#e4e4e4">
+  <td>
+    <a name="overview"><h1>Overview</h1></a>
+  </td>
+  </tr>
+</table>
+
 <p>
+  <b>Goals</b>.
   Nuttx is a real timed embedded operating system (RTOS).
   Its goals are:
 <p>
-<ol>
-  <li>A very small footprint usable in all but the tightest micro-controller environments,</li>
-  <li>Fully scalable from tiny (8-bit) to moderate embedded (32-bit),</li>
-  <li>High degree of standards compliance.</li>
-  <li>Totally open.</li>
-</ol>
+<center><table width="90%">
+<tr>
+  <td valign="top"><img src="favicon.ico"></td>
+  <td bgcolor="#5eaee1">
+    <b>Small Footprint</b>
+  </td>
+</tr>
+<tr>
+  <td><br></td>
+  <td>
+    <p>
+      Usable in all but the tightest micro-controller environments,
+      The focus is on the tiny-to-small, deeply embedded environment.
+    </p>
+</tr>
+<tr>
+  <td valign="top"><img src="favicon.ico"></td>
+  <td bgcolor="#5eaee1">
+    <b>Rich Feature OS Set</b>
+  </td>
+</tr>
+<tr>
+  <td><br></td>
+  <td>
+    <p>
+      The goal is to provide most standard POSIX OS interfaces to support
+      a rich, multi-threaded development environment for deeply embedded
+      processors.
+    </p>
+      NON-GOALS: (1) It is not a goal to provide the rich level of OS
+      features like those provided with Linux.
+      Small footprint is more important than features.
+      Standard compliance is more important than small footprint.
+      (2) There is no MMU-based support for processes.
+      At present, NuttX assumes a flat address space.
+    </p>
+</tr>
+<tr>
+  <td valign="top"><img src="favicon.ico"></td>
+  <td bgcolor="#5eaee1">
+    <b>Highly Scalable</b>
+  </td>
+</tr>
+<tr>
+  <td><br></td>
+  <td>
+    <p>
+      Fully scalable from tiny (8-bit) to moderate embedded (32-bit).
+      Scalability with rich feature set is accomplished with:
+      Many tiny source files, link from static libraries, highly configurable, use of
+      weak symbols when available.
+    </p>
+</tr>
+<tr>
+  <td valign="top"><img src="favicon.ico"></td>
+  <td bgcolor="#5eaee1">
+    <b>Standards Compliance</b>
+  </td>
+</tr>
+<tr>
+  <td><br></td>
+  <td>
+    <p>
+      NuttX strives to achieve a high degree of standards compliance.
+      The primary governing standards are POSIX and ANSI standards.
+      Additional standard APIs from Unix and other common RTOS's are
+      adopted for functionality not available under these standards
+      or for functionaly that is not appropriate for the deeply-embedded
+      RTOS (such as <code>fork()</code>).
+    </p>
+    <p>
+      Because of this standards conformance, software developed under other
+      standard OSs (such as Linux) should port easily to NuttX.
+    </p>
+</tr>
+<tr>
+  <td valign="top"><img src="favicon.ico"></td>
+  <td bgcolor="#5eaee1">
+    <b>Real-Time</b>
+  </td>
+</tr>
+<tr>
+  <td><br></td>
+  <td>
+    <p>
+      Fully pre-emptible, fixed priority and round-robin scheduling.
+    </p>
+</tr>
+<tr>
+  <td valign="top"><img src="favicon.ico"></td>
+  <td bgcolor="#5eaee1">
+    <b>Totally Open</b>
+  </td>
+</tr>
+<tr>
+  <td><br></td>
+  <td>
+    <p>
+      Non-restrictive BSD license.
+    </p>
+</tr>
+</table></center>
 
-<h1>Supported Platforms</h1>
+<table width ="100%">
+  <tr bgcolor="#e4e4e4">
+  <td>
+    <a name="downloads"><h1>Downloads</h1></a>
+  </td>
+  </tr>
+</table>
 
-<ul>
-<li><b>x86 Linux Simulation</b>.  Fully functional.</li>
-<li>TI <b>TMS320C5471</b> (also called <b>TMS320DM180</b>).
-    NuttX operates on the ARM7 of this dual core processor.
-    This port uses the <a href="http://www.spectrumdigital.com/">Spectrum Digital</a>
-    evaluation board with a GNU arm-elf toolchain*.
-    This port is complete, verified, and included in the initial NuttX
-    release.</li>
-<li><b>8051 Microcontroller</b>.
-    This port uses the <a href="http://www.pjrc.com/">PJRC</a> 87C52 development system
-    and the <a href="http://sdcc.sourceforge.net/">SDCC</a> toolchain.
-    This port will require a few more weeks before it is ready for prime time.</li>
-<li><b>Other ports</b>.
-    I also have partial ports for the TI TMS320DM270 and for MIPS. 
-</ul>
+<p>
+   The 9th release of NuttX (nuttx-0.2.6) is available for download
+   from the <a href="http://sourceforge.net/project/showfiles.php?group_id=189573">SourceForge</a>
+   website.
+   The change log associated with the release is available <a href="#currentrelease">here</a>.
+   Unreleased changes after this release are avalable in CVS.
+   These unreleased changes are listed <a href="#pendingchanges">here</a>.
+</p>
+
+<table width ="100%">
+  <tr bgcolor="#e4e4e4">
+  <td>
+    <a name="platforms"><h1>Supported Platforms</h1></a>
+  </td>
+  </tr>
+</table>
+
+<center><table width="90%">
+<tr>
+  <td valign="top"><img src="favicon.ico"></td>
+  <td bgcolor="#5eaee1">
+    <b>Linux User Mode</b>
+  </td>
+</tr>
+<tr>
+  <td><br></td>
+  <td>
+    <p>
+      A user-mode port of NuttX to the x86 Linux platform is available.
+      The purpose of this port is primarily to support OS feature developement.
+    </p>
+    <p>
+      <b>STATUS:</b>
+      Does not support interrupts but is otherwise fully functional.
+    </p>
+   </td>
+</tr>
+<tr>
+  <td valign="top"><img src="favicon.ico"></td>
+  <td bgcolor="#5eaee1">
+    <b>ARM7TDMI</b>.
+  </td>
+</tr>
+<tr>
+  <td><br></td>
+  <td>
+    <p>
+      <b>TI TMS320C5471</b> (also called a <b>C5471</b> or <b>TMS320DM180</b>).
+      NuttX operates on the ARM7 of this dual core processor.
+      This port uses the <a href="http://www.spectrumdigital.com/">Spectrum Digital</a>
+      evaluation board with a GNU arm-elf toolchain*.
+    </p>
+    <p>
+      <b>STATUS:</b>
+      This port is complete, verified, and included in the initial NuttX release.
+    </p>
+   </td>
+</tr>
+<tr>
+  <td><br></td>
+  <td>
+    <p>
+      <b>NXP LPC214x</b>.
+      Support is provided for the NXP LPC214x family of processors.  In particular,
+      support is provided for the mcu123.com lpc214x evaluation board (LPC2148).
+      This port also used the GNU arm-eld toolchain*.
+    </p>
+    <p>
+      <b>STATUS:</b>
+        This port is in progress and should be available in the nuttx-0.2.7 release.
+    </p>
+  </td>
+</tr>
+<tr>
+  <td valign="top"><img src="favicon.ico"></td>
+  <td bgcolor="#5eaee1">
+    <b>ARM9EJS</b>.
+  </td>
+</tr>
+<tr>
+  <td><br></td>
+  <td>
+    <p>
+      <b>TI TMS320DM320</b> (also called <b>DM320</b>).
+      NuttX operates on the ARM9 of this dual core processor.
+      This port uses the
+      <a href="http://wiki.neurostechnology.com/index.php/Developer_Welcome">Neuros OSD</a>
+      with a GNU arm-elf toolchain*.
+    </p>
+    <p>
+      <b>STATUS:</b>
+      This port is code complete but totally untested due to hardware issues with my OSD.
+    </p>
+   </td>
+</tr>
+<tr>
+  <td valign="top"><img src="favicon.ico"></td>
+  <td bgcolor="#5eaee1">
+    <b>8052 Microcontroller</b>
+  </td>
+</tr>
+<tr>
+  <td><br></td>
+  <td>
+    <p>
+      <b>PJRC 87C52 Development Board</b>.
+      This port uses the <a href="http://www.pjrc.com/">PJRC</a> 87C52 development system
+      and the <a href="http://sdcc.sourceforge.net/">SDCC</a> toolchain.
+    </p>
+    <p>
+     <b>STATUS:</b>
+      This port is complete but not stable with timer interrupts enabled.
+      There seems to be some issue when the stack pointer enters into the indirect IRAM
+      address space during interrupt handling.
+    </p>
+   </td>
+</tr>
+<tr>
+  <td valign="top"><img src="favicon.ico"></td>
+  <td bgcolor="#5eaee1">
+    <b>Other ports</b>
+  </td>
+</tr>
+<tr>
+  <td><br></td>
+  <td>
+    <p>
+      There are partial ports for the TI TMS320DM270 and for MIPS.
+    </p>
+   </td>
+</tr>
+</table></center>
 
 <blockquote>* A highly modified <a href="http://buildroot.uclibc.org/">buildroot</a>
 is available that be used to build a NuttX-compatible arm-elf toolchain.</blockquote>
 
-<h1>Memory Footprint</h1>
+<table width ="100%">
+  <tr bgcolor="#e4e4e4">
+  <td>
+    <a name="footprint"><h1>Memory Footprint</h1></a>
+  </td>
+  </tr>
+</table>
 
+<ul>
 <p><b>C5471 (Arm7)</b>
   The build for this ARM7 target that includes most of the OS features and
   a broad range of OS tests.  The size of this executable as given by the
-  Linux <tt>size</tt> command is:
+  Linux <tt>size</tt> command is (3/9/07):
 </p>
 <pre>
    text    data     bss     dec     hex filename
   53272     428    3568   57268    dfb4 nuttx
 </pre>
 <p><b>87C52</b>
-  A reduced functionality OS test for the 8051 target requires only
-  about 18Kb (see <a href="codesize-070301.xls">spreadsheet</a> for details).
+  A reduced functionality OS test for the 8052 target requires only
+  about 18-19Kb:
 </p>
+<pre>
+Stack starts at: 0x21 (sp set to 0x20) with 223 bytes available.
 
-<h1>Licensing</h1>
+Other memory:
+   Name             Start    End      Size     Max
+   ---------------- -------- -------- -------- --------
+   PAGED EXT. RAM                         0      256
+   EXTERNAL RAM     0x0100   0x02fd     510     7936
+   ROM/EPROM/FLASH  0x2100   0x6e55   19798    24384
+</pre>
+</ul>
 
-<p>NuttX is available under the highly permissive
+<table width ="100%">
+  <tr bgcolor="#e4e4e4">
+  <td>
+    <a name="licensing"><h1>Licensing</h1></a>
+  </td>
+  </tr>
+</table>
+
+<ul>
+<p>
+  NuttX is available under the highly permissive
   <a href="http://en.wikipedia.org/wiki/BSD_license">BSD license</a>.
-  Other than some fine print that you agree to respect my copyright
+  Other than some fine print that you agree to respect the copyright
   you should feel absolutely free to use NuttX in any environment and
   without any concern for jeopardizing any proprietary software that
-  you may link with it.</p>
+  you may link with it.
+</p>
+</ul>
 
-<h1>Other Documentation</h1>
+<table width ="100%">
+  <tr bgcolor="#e4e4e4">
+  <td>
+    <a name="history"><h1>Release History</h1></a>
+  </td>
+  </tr>
+</table>
 
-<li><a href="NuttxUserGuide.html">User Guide</li>
-<li><a href="NuttxPortingGuide.html">Porting Guide</li>
+<center><table width ="80%">
+<tr>
+  <td><img src="favicon.ico"></td>
+   <td>
+      <a href="#olderreleases">Change Logs for Older Releases</a><br>
+   </td>
+</tr>
+<tr>
+  <td><img src="favicon.ico"></td>
+   <td>
+      <a href="#currentrelease">ChangeLog for Current Release</a><br>
+   </td>
+</tr>
+<tr>
+  <td><img src="favicon.ico"></td>
+   <td>
+      <a href="#pendingchanges">Unreleased Changes</a>
+   </td>
+</tr>
+</table></center>
+
+<table width ="100%">
+  <tr bgcolor="#e4e4e4">
+  <td>
+    <a name="olderreleases>Change Logs for Older Releases</a>
+  </td>
+  </tr>
+</table>
+
+<ul><pre>
+0.1.0 2007-03-09  Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* Initial Release
+	* Support for Linux user mode simulation and TI
+	  TMS320C5471 (Arm7) provided
+
+0.1.1 2007-03-14  Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* Corrected an error in interrupt level context switching
+	  for C5471
+	* Added fgets() and gets() logic; verified c5471 console read.
+	* Corrected error in reading from the C5471 serial port:
+          Improper use of semaphore can cause deadlock.
+	* Fixed an error in the memory cleanup:  The idle task
+	  cannot take sempahores (because it must always be ready
+	  to run).
+	* Tasks can now accept a configurable maximum number of
+	  input parameters (argc)
+	* _task_init() was divided into separate functions that
+	  require fewer parameters.  This was necessary to keep
+	  the stack usage down for the 8051/2 (which has only
+	  256 bytes of stack).
+	* Attempts to use C5471 console from interrupt handlers
+	  can cause errors. Added a special path for this case.
+	* Refuse calls to sem_wait and sem_trywait from interrupt
+	  handlers.  This was happening because interrupt handlers
+	  were calling printf-like functions.
+	* Added strtok() and strtok_r()
+	* Added a simple shell called nsh (see examples/nsh).
+	* Platform support for 8052 is complete but not stable
+	  when the timer interrupt is enabled.  Seems to be an
+	  issue when SP enters indirect address space.
+	* Documentation updates
+
+0.1.2 2007-03-19  Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* Add dirent.h, opendir(), readdir(), closedir(), etc.
+	* Add strerror()
+	* Added 'ls' command to nsh
+	* Added C5471 watchdog driver
+	* Fixed another bug where free() is called from IDLE task.
+	  Can't do this; the caller must be able to wait for access
+	  to memory.
+	* Fixed bugs associated with debug output:
+          Cannot do dbg() in middle of context switch logic.
+	  because it may require use of semaphores and cause
+	  additional context switches. lldbg() is safe.
+	* Interrupt must be disabled throughout all context switches.
+	* Separated C5471 serial driver; a shareable part is
+	  in drivers/. ; the C5471 specific part is in arch/C5471.
+	  serial.h defines the interface.
+	* Fixed mq_receive() and mq_send() -- bad memcpy()
+	* Fixed C5471 signal deliver logic: use of dbg() and
+          other actions by use signal handler can alter errno.
+          need to protect errno during signal handling.
+	* Fixed uninitialized variable in filesystem that could
+	  cause various problems
+	* Added a test for roundrobin scheduler.
+
+0.2.1 2007-03-22  Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* Fix error in handing signed decimal in vsprintf().
+	* Major restructuring of header files to get closer to
+	  POSIX compliance.
+	* Eliminate compilation warnings that that crept into
+	  recent check-ins
+	* Add kill()
+	* Added support for POSIX timers
+	* Some Documentation updates
+	* Added support for the Neuros OSD / DM320
+
+0.2.2 2007-03-26 Gregory Nutt <spudmonkey@racsa.co.cr>
+	* Created the configs/ directory; separated board configuration
+	  from processor architecture logic
+	* Add memory leak detection test to examples/ostest
+	* Corrected memory leak in OS pthread join logic
+	* Corrected memory leaks in examples/ostest due to failures
+	  to join or detach from pthreads.
+	* Added pthread_once(), pthread_kill(), pthread_sigmask()
+	* Added pthread_barrierattr_*() APIs
+	* Added pthread_barrier_init(), pthread_barrier_destroy(), and
+	  pthread_barrier_wait();
+	* Added pthread barrier test
+	* Added protection so that errno cannot be modified from
+	  interrupt handling.
+	* sched_setparam(), sched_setscheduler() now correctly set
+	  errno; pthread_setscheduler() now returns the correct errno.
+	* Added pthread_setschedprio().
+	* Added directories to hold board-specific header files
+	* Added directories to hold board-specific drivers
+
+0.2.3 2007-03-29 Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* mq_receive and mq_send now return errno's appropriately
+	* mq_receive and mq_send are now correctly awakened by signals.
+	* Fixed an unmatched sched_lock/unlock pair in task_delete().
+	* sched_lock must be called in _exit() because operation of
+	  task_delete() can cause pending tasks to be merged and a
+	  context switch to occur.
+	* Added mq_timedreceive() and mq_timedsend()
+	* signal mask is now inherited by both child tasks and threads.
+	* Improved sharebility of stdout among pthreads (only).  Nothing
+	  was broken, but by moving the mutual exclusion logic to a
+	  higher level, the printf output is more readable.
+	* Fixed a bug in file system cleanup:  A list was being deleted
+	  before the buffers contained in the list.
+	* Fixed a bug in the wait-for-message-queue-not-empty logic.
+	* Added a test of timed mqueue operations; detected and corrected
+	  some mqueue errors.
+	* Identified and corrected a race condition associated with
+	  pthread_join.  In the failure condition, memory was being
+	  deallocated while still in use.
+
+0.2.4 2007-04-28 Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* Verfied c5471 build under Cygwin on WinXP
+	* Makesystem changes to better support different SoCs.
+	* Made arch/c5471/include and arch/dm320/include identical in
+	  preparation for merging into arch/arm
+	* Logic from arch/c5471 and arch/dm320 combined into arch/arm.
+	  arch/c5471 and arch/dm320 are deprecated and will be removed
+	  when the new c5471 and dm320 logic is verified.
+
+0.2.5 2007-05-19 Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* Corrected some build/configuration issues introduced with the
+	  last release.
+	* Added support for the NXP 214x processor on the mcu123.com lpc214x
+	  development board (untested)
+	* Added support for block devices.
+	* Simulated target now exports a VFAT filesystem
+	* Begin support for VFAT filesystem (missing functionalit)
+	* Added mount() and umount()
+	* Fix bug in memcmp return value
+	* Fix errors in timeslice calculation (several places)
+	* Added missing irqrestore() in timer_deletall().
+	* close() was not closing the underlying device.
+	* Added fsync()
+	* Added strspn() and strcspn()
+</pre></ul>
+
+<table width ="100%">
+  <tr bgcolor="#e4e4e4">
+  <td>
+    <a name="currentrelease">ChangeLog for Current Release</a>
+  </td>
+  </tr>
+</table>
+
+<pre><ul>
+0.2.6 2007-05-26 Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* Added unlink(), mkdir(), rmdir(), and rename()
+	* Fixed several serious FAT errors with oflags handling (&& instead of &)
+	* Added FAT support for unlink(), mkdir(), rmdir(), and rename
+	* Added FAT support for opendir(), closedir(), readdir(), seekdir(),
+	  telldir(), rewindir().
+	* Fixed ARM compilation errors introduced in 0.2.5 (that is what I get
+	  for only testing on the simulation).
+</pre></ul>
+
+<table width ="100%">
+  <tr bgcolor="#e4e4e4">
+  <td>
+    <a name="pendingchanges">Unreleased Changes</a>
+  </td>
+  </tr>
+</table>
+
+<pre><ul>
+
+0.2.7 2007-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* Started m68322
+</pre></ul>
+
+<table width ="100%">
+  <tr bgcolor="#e4e4e4">
+  <td>
+    <a name="documentation"><h1>Other Documentation</h1></a>
+  </td>
+  </tr>
+</table>
+
+<ul><table>
+<tr>
+  <td><img src="favicon.ico"></td>
+  <td><a href="NuttxUserGuide.html">User Guide</td>
+</tr>
+<tr>
+  <td><img src="favicon.ico"></td>
+  <td><a href="NuttxPortingGuide.html">Porting Guide</td>
+</tr>
+</center></ul>
 
 </body>
 </html>

Documentation/NuttXBanner.html

@@ -11,9 +11,23 @@
     </a>
   </td>
   <td>
-    <big><b>NuttX RTOS</b></big><br>
-    <a href="http://sourceforge.net/projects/nuttx" target="_top">Project</a><br>
-    <a href="http://nuttx.sourceforge.net" target="_top">Home</a>
+    <table width="100%">
+      <tr>
+        <td bgcolor="#e4e4e4">
+          <big><b><i><font color="#3c34ec">NuttX RTOS</font></i></b></big>
+        </td>
+      </tr>
+      <tr>
+        <td>
+          <a href="http://sourceforge.net/projects/nuttx" target="_top">Project</a><br>
+        </td>
+      </tr>
+      <tr>
+        <td>
+          <a href="http://nuttx.sourceforge.net" target="_top">Home</a>
+        </td>
+      </tr>
+    </table>
   </td>
   </tr>
 </body>

Documentation/index.html

@@ -2,7 +2,7 @@
 <head>
 <title>NuttX</title>
 </head>
-<frameset rows="75,*" framespacing="0" border="0" frameborder="0">
+<frameset rows="80,*" framespacing="0" border="0" frameborder="0">
   <frame name="header" scrolling="no" target="main" src="NuttXBanner.html" marginwidth="0" marginheight="0">
   <frame name="main" src="NuttX.html">
   <noframes>

Makefile

@@ -39,6 +39,8 @@ TOPDIR		= ${shell pwd}
 
 ARCH_DIR	= arch/$(CONFIG_ARCH)
 ARCH_SRC	= $(ARCH_DIR)/src
+ARCH_INC	= $(ARCH_DIR)/include
+BOARD_DIR	= configs/$(CONFIG_ARCH_BOARD)
 
 SUBDIRS		= sched lib $(ARCH_SRC) mm fs drivers examples/$(CONFIG_EXAMPLE)
 
@@ -51,20 +53,89 @@ BIN		= nuttx$(EXEEXT)
 all: $(BIN)
 .PHONY: clean context clean_context distclean
 
+# Build the mkconfig tool used to create include/nuttx/config.h
 tools/mkconfig:
 	$(MAKE) -C tools -f Makefile.mkconfig TOPDIR=$(TOPDIR)  mkconfig
 
-include/nuttx/config.h: $(ARCH_DIR)/defconfig tools/mkconfig
-	tools/mkconfig $(ARCH_DIR) > include/nuttx/config.h
+# Create the include/nuttx/config.h file
+include/nuttx/config.h: $(TOPDIR)/.config tools/mkconfig
+	tools/mkconfig $(TOPDIR) > include/nuttx/config.h
 
-include/arch: include/nuttx/config.h
-	ln -sf $(TOPDIR)/$(ARCH_DIR)/include include/arch
+# link the arch/<arch-name>/include dir to include/arch
+include/arch: Make.defs
+	@if [ -h include/arch ]; then \
+		rm -f include/arch ; \
+	else \
+		if [ -e include/arch ]; then \
+			echo "include/arch exists but is not a symbolic link" ; \
+			exit 1 ; \
+		fi ; \
+	fi
+	@ln -s $(TOPDIR)/$(ARCH_DIR)/include include/arch
 
-context: check_context include/nuttx/config.h include/arch
+# Link the configs/<board-name>/include dir to include/arch/board
+include/arch/board: Make.defs include/arch
+	@if [ -h include/arch/board ]; then \
+			rm -f include/arch/board ; \
+	else \
+		if [ -e include/arch/board ]; then \
+			echo "include/arch/board exists but is not a symbolic link" ; \
+			exit 1 ; \
+		fi ; \
+	fi
+	@ln -s $(TOPDIR)/$(BOARD_DIR)/include include/arch/board
+
+# Link the configs/<board-name>/src dir to arch/<arch-name>/src/board
+$(ARCH_SRC)/board: Make.defs
+	@if [ -h $(ARCH_SRC)/board ]; then \
+		rm -f $(ARCH_SRC)/board ; \
+	else \
+		if [ -e $(ARCH_SRC)/board ]; then \
+			echo "$(ARCH_SRC)/board exists but is not a symbolic link" ; \
+			exit 1 ; \
+		fi ; \
+	fi
+	@ln -s $(TOPDIR)/$(BOARD_DIR)/src $(ARCH_SRC)/board
+
+# Link arch/<arch-name>/include/<chip-name> to arch/<arch-name>/include/chip
+$(ARCH_SRC)/chip: Make.defs
+ifneq ($(CONFIG_ARCH_CHIP),)
+	@if [ -h $(ARCH_SRC)/chip ]; then \
+		rm -f $(ARCH_SRC)/chip ; \
+	else \
+		if [ -e $(ARCH_SRC)/chip ]; then \
+			echo "$(ARCH_SRC)/chip exists but is not a symbolic link" ; \
+			exit 1 ; \
+		fi ; \
+	fi
+	@ln -s $(CONFIG_ARCH_CHIP) $(ARCH_SRC)/chip
+endif
+
+# Link arch/<arch-name>/src/<chip-name> to arch/<arch-name>/src/chip
+$(ARCH_INC)/chip: Make.defs
+ifneq ($(CONFIG_ARCH_CHIP),)
+	@if [ -e $(ARCH_INC)/chip ]; then \
+		if [ -h $(ARCH_INC)/chip ]; then \
+			rm -f $(ARCH_INC)/chip ; \
+		else \
+			echo "$(ARCH_INC)/chip exists but is not a symbolic link" ; \
+			exit 1 ; \
+		fi ; \
+	fi
+	@ln -s $(CONFIG_ARCH_CHIP) $(ARCH_INC)/chip
+endif
+
+dirlinks: include/arch include/arch/board $(ARCH_SRC)/board $(ARCH_SRC)/chip $(ARCH_INC)/chip
+
+context: check_context include/nuttx/config.h dirlinks
 
 clean_context:
-	rm -f include/nuttx/config.h
-	rm -f include/arch
+	@rm -f include/nuttx/config.h include/arch
+	@if [ -h include/arch ]; then rm -f include/arch ; fi
+	@if [ -h $(ARCH_INC)/board ]; then rm -f $(ARCH_INC)/board ; fi
+	@if [ -h $(ARCH_SRC)/board ]; then rm -f $(ARCH_SRC)/board ; fi
+	@if [ -h $(ARCH_INC)/chip ]; then rm -f $(ARCH_INC)/chip ; fi
+	@if [ -h $(ARCH_SRC)/chip ]; then rm -f $(ARCH_SRC)/chip ; fi
 
 check_context:
 	@if [ ! -e ${TOPDIR}/.config -o ! -e ${TOPDIR}/Make.defs ]; then \
@@ -102,19 +173,26 @@ depend:
 		$(MAKE) -C $$dir TOPDIR=$(TOPDIR) depend ; \
 	done
 
-clean:
+subdir_clean:
 	@for dir in $(SUBDIRS) ; do \
-		$(MAKE) -C $$dir TOPDIR=$(TOPDIR) clean ; \
+		if [ -e $$dir/Makefile ]; then \
+			$(MAKE) -C $$dir TOPDIR=$(TOPDIR) clean ; \
+		fi \
 	done
 	$(MAKE) -C tools -f Makefile.mkconfig TOPDIR=$(TOPDIR) clean
 	$(MAKE) -C mm -f Makefile.test TOPDIR=$(TOPDIR) clean
+
+clean: subdir_clean
 	rm -f $(BIN) $(BIN).* mm_test *.map *~
 
-distclean: clean clean_context
+subdir_distclean:
 	@for dir in $(SUBDIRS) ; do \
-		$(MAKE) -C $$dir TOPDIR=$(TOPDIR) distclean ; \
+		if [ -e $$dir/Makefile ]; then \
+			$(MAKE) -C $$dir TOPDIR=$(TOPDIR) distclean ; \
+		fi \
 	done
-	$(MAKE) -C examples/$(CONFIG_EXAMPLE) TOPDIR=$(TOPDIR) distclean
+
+distclean: clean subdir_distclean clean_context
 	rm -f Make.defs setenv.sh .config
 
 

ReleaseNotes

@@ -1,12 +1,15 @@
-Nuttx-0.1.0
+nuttx-0.2.6
 ^^^^^^^^^^^
 
-This is the initial.  This initial includes the complete NuttX RTOS
-with support for the Linux user mode simulation and the TI TMS320C5471
-(Arm7) processor.  Partial support for the 87C52 is included.
+This is the 9th release of NuttX.  This is primarily a bugfix release
+to correct a number of problems introduced with the 0.2.5 release. This release
+does include some FAT filesystem extensions including unlink(), mkdir(),
+rmdir(), rename(), opendir(), closedir(), readdir(), seekdir(),  telldir(),
+rewindir().  There are some pending FAT changes that did not make it into
+this release including stat(), truncate(), and long file names.
 
-This release has been verified on both the Linux user-mode and C5471
-platforms using the test program under examples/ostest.  Test results
-for the C5471 can be found in arch/c5471/doc/test-results.txt.
+See the ChangeLog for a complete list of changes.
 
-This tarball contains a complete CVS snapshot from March 9,2007.
+This release has been verified only on the Linux user-mode platform.
+
+This tarball contains a complete CVS snapshot from May 26, 2007.

TODO

@@ -0,0 +1,83 @@
+NuttX TODO List
+^^^^^^^^^^^^^^^
+
+o Task/Scheduler
+- When a tasks exits, shouldn't all of its child pthreads also be terminated?
+- Should task_delete() cause atexit() function to be called?
+- Implement sys/mman.h and functions
+- Implement sys/wait.h and functions
+- Implement priority inheritance
+- Make the system timer frequency configurable via defconfig.  See:
+   _POSIX_CLOCKRES_MIN in limits.h
+   CLK_TCK in time.h
+   MSEC_PER_TICK in sched/clock_internal.h
+- Consider implementing wait, waitpid, waitid.  At present, a parent has
+  no information about child tasks.
+- Several APIs do not set errno.  Need to review all APIs.
+
+o Memory Managment
+- Add an option to free all memory allocated by a task when the task exits.
+  This is probably not be worth the overhead for a deeply embedded system.
+- Current logic adapts size_t for 16-bit address machines vs. 32-bit address
+  machines.  But a small memory option should also be provided so that
+  the small offset option can be used with 32-bit machines that have small
+  RAM memories (like the lpc2148)
+
+o Signals
+- 'Standard' signals and signal actions are not supported.
+
+o pthreads
+- pthread_cancel():  Should implemenent cancellation points and pthread_testcancel()
+
+o Network
+- Port FreeBSD TCP/IP stack
+
+o USB
+
+o Libraries
+- sscanf() and lib_vsprintf() do not support floating point values.
+
+o File system
+- Add disk usage stats, stat(), chmod(), truncate().
+- FAT32: long file names
+
+o Console Output
+
+o Documentation
+- Document fs/ & driver/ logic
+- Document C-library APIs
+
+o Build system
+- Some names under arch are still incorrect.  These should be processor architecture
+  names:  pjrc-8051 should be 805x
+- configs/pjrc-8051 should be configs/pjrc-87c52
+- Last change to create the arch/arm directory breaks dependencies in arch/arm/src.
+  Probably need to add the path to the chip or common subdirectorys when
+  running tools/mkdeps.sh
+
+o Applications & Tests
+
+o C5471
+
+o DM320
+
+o LPC214x
+- Finish
+
+o pjrc-8052 / MCS51
+- Current status:
+  - Basic OS task management seems OK
+  - Fails when interrupts enabled.  The stack pointer is around 0x6e
+    before the failure occurs.  It looks like some issue when the
+    stack pointer moves from the directly to indirectly addressable
+    region (0x80 boundary).
+  - Work on the 8052 is temporarily on hold
+- Use timer 0 as system timer.  Timer 2 is needed for second UART.
+  Logic is implemented, but there needs to be a system configuration
+  to change the ticks-per-second value to match the timer interrupt
+  rate
+- During build, there are several integer overflows reported:
+  gmtime_r.c aroud lines 184 and 185
+  clock_initialize.c at line 107
+  pthread_create.c at 330
+  sighand.c at 225 and 244

arch/README.txt

@@ -11,160 +11,65 @@ Table of Contents
 Architecture-Specific Code
 ^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-The file include/nuttx/arch.h identifies all of the APIs that must
-be provided by the architecture specific logic.  (It also includes
+The NuttX configuration consists of:
+
+o Processor architecture specific files.  These are the files contained
+  in the arch/<arch-name>/ directory discussed in this README.
+
+o Chip/SoC specific files.  Each processor processor architecture
+  is embedded in chip or System-on-a-Chip (SoC) architecture.  The
+  full chip architecture includes the processor architecture plus
+  chip-specific interrupt logic, general purpose I/O (GIO) logic, and
+  specialized, internal peripherals (such as UARTs, USB, etc.).
+
+  These chip-specific files are contained within chip-specific
+  sub-directories in the arch/<arch-name>/ directory and are selected
+  via the CONFIG_ARCH_name selection
+
+o Board specific files.  In order to be usable, the chip must be
+  contained in a board environment.  The board configuration defines
+  additional properties of the board including such things as
+  peripheral LEDs, external peripherals (such as network, USB, etc.).
+
+  These board-specific configuration files can be found in the
+  configs/<board-name>/ sub-directories.
+
+This README will address the processor architecture specific files
+that are contained in the arch/<arch-name>/ directory. The file
+include/nuttx/arch.h identifies all of the APIs that must
+be provided by this architecture specific logic.  (It also includes
 arch/<arch-name>/arch.h as described below).
 
 Directory Structure
 ^^^^^^^^^^^^^^^^^^^
 
-Thie arch directory contains architecture specific logic.  Each aructure
-provide a a subdirectory <arch-name>under arch/ with the folling characteristics:
+The arch directory contains architecture specific logic.  The complete
+board port in is defined by the architecture-specific code in this
+directory (plus the board-specific configurations in the config/
+subdirectory).  Each architecture must provide a subdirectory <arch-name>
+under arch/ with the following characteristics:
 
 
-	<arch-name>
-	|-- Make.defs
-	|-- defconfig
-	|-- setenv.sh
-	|-- include
+	<arch-name>/
+	|-- include/
+	|   |--<chip-name>/
+	|   |  `-- (chip-specific header files)
+	|   |--<other-chips>/
 	|   |-- arch.h
 	|   |-- irq.h
 	|   `-- types.h
-	`-- src
+	`-- src/
+	    |--<chip-name>/
+	    |  `-- (chip-specific source files)
+	    |--<other-chips>/
 	    |-- Makefile
 	    `-- (architecture-specific source files)
 
 Summary of Files
 ^^^^^^^^^^^^^^^^
 
-Make.defs -- This makefile fragment provides architecture and
-  tool-specific build options.  It will be included by all other
-  makefiles in the build (once it is installed).  This make fragment
-  should define:
-
-	Tools: CC, LD, AR, NM, OBJCOPY, OBJDUMP
-	Tool options: CFLAGS, LDFLAGS
-
-  When this makefile fragment runs, it will be passed TOPDIR which
-  is the path to the root directory of the build.  This makefile
-  fragment may include ${TOPDIR}/.config to perform configuration
-  specific settings.  For example, the CFLAGS will most likely be
-  different if CONFIG_DEBUG=y.
-
-defconfig -- This is a configuration file similar to the Linux
-  configuration file.  In contains varialble/value pairs like:
-
-	CONFIG_VARIABLE=value
-
-  This configuration file will be used at build time:
-
-    (1) as a makefile fragment included in other makefiles, and
-    (2) to generate include/nuttx/config.h which is included by
-        most C files in the system.
-
-  The following variables are recognized by the build (you may
-  also include architecture-specific settings).
-
-	Architecture selection:
-
-		CONFIG_ARCH - identifies the arch subdirectory
-		CONFIG_ARCH_name - for use in C code
-
-	General OS setup
-
-		CONFIG_EXAMPLE - identifies the subdirectory in examples
-		  that will be used in the build
-		CONFIG_DEBUG - enables built-in debug options
-		CONFIG_DEBUG_VERBOSE - enables verbose debug output
-		CONFIG_HAVE_LOWPUTC - architecture supports low-level, boot
-		  time console output
-		CONFIG_MM_REGIONS - If the architecture includes multiple
-		  regions of memory to allocate from, this specifies the
-		  number of memory regions that the memory manager must
-		  handle and enables the API mm_addregion(start, end);
-		CONFIG_RR_INTERVAL - The round robin timeslice will be set
-		  this number of milliseconds;  Round robin scheduling can
-		  be disabled by setting this value to zero.
-		CONFIG_SCHED_INSTRUMENTATION - enables instrumentation in 
-		  scheduler to monitor system performance
-		CONFIG_TASK_NAME_SIZE - Spcifies that maximum size of a
-		  task name to save in the TCB.  Useful if scheduler
-		  instrumentation is selected.  Set to zero to disable.
-		CONFIG_START_YEAR, CONFIG_START_MONTH, CONFIG_START_DAY -
-		  Used to initialize the internal time logic.
-		CONFIG_JULIAN_TIME - Enables Julian time conversions
-		CONFIG_DEV_CONSOLE - Set if architecture-specific logic
-		  provides /dev/console.  Enables stdout, stderr, stdin.
-
-	The following can be used to disable categories of APIs supported
-	by the OS.  If the compiler supports weak functions, then it
-	should not be necessary to disable functions unless you want to
-	restrict usage of those APIs.
-
-	There are certain dependency relationships in these features.
-
-	o mq_notify logic depends on signals to awaken tasks
-	  waiting for queues to become full or empty.
-	o pthread_condtimedwait() depends on signals to wake
-	  up waiting tasks.
-
-		CONFIG_DISABLE_CLOCK, CONFIG_DISABLE_PTHREAD.
-		CONFIG_DISABLE_SIGNALS, CONFIG_DISABLE_MQUEUE
-
-
-	Misc libc settings
-
-		CONFIG_NOPRINTF_FIELDWIDTH - sprintf-related logic is a
-		   little smaller if we do not support fieldwidthes
-
-	Allow for architecture optimized implementations
-
-		The architecture can provide optimized versions of the
-		following to improve sysem performance
-
-		CONFIG_ARCH_MEMCPY, CONFIG_ARCH_MEMCMP, CONFIG_ARCH_MEMMOVE
-		CONFIG_ARCH_MEMSET, CONFIG_ARCH_STRCMP, CONFIG_ARCH_STRCPY
-		CONFIG_ARCH_STRNCPY, CONFIG_ARCH_STRLEN, CONFIG_ARCH_BZERO
-		CONFIG_ARCH_KMALLOC, CONFIG_ARCH_KZMALLOC, CONFIG_ARCH_KFREE
-
-	Sizes of configurable things (0 disables)
-
-		CONFIG_MAX_TASKS - The maximum number of simultaneously
-		  active tasks.  This value must be a power of two.
-		CONFIG_NPTHREAD_KEYS - The number of items of thread-
-		  specific data that can be retained
-		CONFIG_NFILE_DESCRIPTORS - The maximum number of file
-		  descriptors (one for each open)
-		CONFIG_NFILE_STREAMS - The maximum number of streams that
-		  can be fopen'ed
-		CONFIG_STDIO_BUFFER_SIZE - Size of the buffer to allocate
-		  on fopen. (Only if CONFIG_NFILE_STREAMS > 0)
-		CONFIG_NUNGET_CHARS - Number of characters that can be
-		  buffered by ungetc() (Only if CONFIG_NFILE_STREAMS > 0)
-		CONFIG_PREALLOC_MQ_MSGS - The number of pre-allocated message
-		  structures.  The system manages a pool of preallocated
-		  message structures to minimize dynamic allocations
-		CONFIG_MQ_MAXMSGSIZE - Message structures are allocated with
-		  a fixed payload size given by this settin (does not include
-		  other message structure overhead.
-		CONFIG_PREALLOC_WDOGS - The number of pre-allocated watchdog
-		  structures.  The system manages a pool of preallocated
-		  watchdog structures to minimize dynamic allocations
-
-	Stack and heap information
-
-		CONFIG_BOOT_FROM_FLASH - Some configurations support XIP
-		  operation from FLASH.
-		CONFIG_STACK_POINTER - The initial stack pointer
-		CONFIG_PROC_STACK_SIZE - The size of the initial stack
-		CONFIG_PTHREAD_STACK_MIN - Minimum pthread stack size
-		CONFIG_PTHREAD_STACK_DEFAULT - Default pthread stack size
-		CONFIG_HEAP_BASE - The beginning of the heap
-		CONFIG_HEAP_SIZE - The size of the heap
-
-setenv.sh -- This is a script that you can include that will be installed at
-  the toplevel of the directory structure and can be sourced to set any
-  necessary environment variables.
+include/<chip-name>/
+  This sub-directory contains chip-specific header files.
 
 include/arch.h
   This is a hook for any architecture specific definitions that may
@@ -205,6 +110,9 @@ include/irq.h
   This file must also define NR_IRQS, the total number of IRQs supported
   by the board.
 
+src/<chip-name>/
+  This sub-directory contains chip-specific source files.
+
 src/Makefile
   This makefile will be executed to build the targets src/libup.a and
   src/up_head.o.  The up_head.o file holds the entry point into the system
@@ -215,36 +123,53 @@ src/Makefile
 Supported Architectures
 ^^^^^^^^^^^^^^^^^^^^^^^
 
-arch/c5471
-    TI TMS320C5471 (also called TMS320DM180).
-    NuttX operates on the ARM7 of this dual core processor. This port
-    uses the Spectrum Digital evaluation board with a GNU arm-elf toolchain*.
-    This port is in progress and partially functional (However, my board
-    is dead at the moment so it will be awhile before I fix it).
+arch/sim
+    A user-mode port of NuttX to the x86 Linux platform is available.
+    The purpose of this port is primarily to support OS feature developement.
+    This port does not support interrupts or a real timer (and hence no
+    round robin scheduler)  Otherwise, it is complete.
+
+arch/arm
+    This directory holds common ARM architectures.  At present, this includes
+    the following subdirectories:
+
+    arch/arm/include and arch/arm/common
+        Common ARM logic.
+
+    arch/arm/include/c5471 and arch/arm/src/c5471
+        TI TMS320C5471 (also called TMS320DM180 or just C5471).
+        NuttX operates on the ARM7 of this dual core processor. This port
+        complete, verified, and included in the NuttX release 0.1.1.
+
+    arch/arm/include/dm320 and arch/arm/src/dm320
+        TI TMS320DM320 (also called just DM320).
+        NuttX operates on the ARM9EJS of this dual core processor.  This port
+        complete, verified, and included in the NuttX release 0.2.1.
+
+    arch/arm/include/lpc214x and arch/arm/src/lpc214x
+        These directories provide support for NXP LPC214x family of
+        processors.
+        STATUS: This port is in progress and should be available in the
+        nuttx-0.2.5 release.
+
+arch/m68322
+    A work in progress.
+    STATUS:  Stalled for the moment.
 
 arch/pjrc-8051
-    8051 Microcontroller.  This port uses the PJRC 87C52 development system
-    and the SDCC toolchain.   This port is not quite ready for prime time.
+    8051 Microcontroller.  This port is not quite ready for prime time.
 
-arch/sim
-  x86 Linux Simulation</b>.  Fully functional.
+The following architecture directories are deprecated.  They have been
+replaced by the logic in arm/arm and will deleted when arch/arm is fully
+verified.
+
+arch/c5471
+    Replaced with arch/arm/include/c5471 and arch/arm/src/c5471
+
+arch/dm320
+    Replaced with arch/arm/include/dm320 and arch/arm/src/dm320
 
 Other ports for the for the TI TMS320DM270 and for MIPS are in various states
 of progress
 
-Configuring NuttX
-^^^^^^^^^^^^^^^^^
-
-Configuring NuttX requires only copying
-
-  arch/<arch-name>/Make.def to ${TOPDIR}/Make.defs
-  arch/<arch-name>/setenv.sh to ${TOPDIR}/setenv.sh
-  arch/<arch-name>/defconfig to ${TOPDIR}/.config
-
-There is a script that automates these steps.  The following steps will
-accomplish the same configuration:
-
-  cd tools
-  ./configure.sh <arch-name>
-
 

arch/arm/include/arch.h

@@ -0,0 +1,80 @@
+/************************************************************
+ * arch/arch.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/* This file should never be included directed but, rather,
+ * only indirectly through nuttx/arch.h
+ */
+
+#ifndef __ARCH_ARCH_H
+#define __ARCH_ARCH_H
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/************************************************************
+ * Inline functions
+ ************************************************************/
+
+/************************************************************
+ * Public Types
+ ************************************************************/
+
+/************************************************************
+ * Public Variables
+ ************************************************************/
+
+/************************************************************
+ * Public Function Prototypes
+ ************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ARCH_ARCH_H */
+

arch/arm/include/c5471/irq.h

@@ -0,0 +1,105 @@
+/************************************************************
+ * arch/c5471/irq.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/* This file should never be included directed but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_C5471_IRQ_H
+#define __ARCH_C5471_IRQ_H
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/* C5471 Interrupts */
+
+#define C5471_IRQ_TIMER0         0
+#define C5471_IRQ_TIMER1         1
+#define C5471_IRQ_TIMER2         2
+#define C5471_IRQ_GPIO0          3
+#define C5471_IRQ_ETHER          4
+#define C5471_IRQ_KBGPIO_0_7     5
+#define C5471_IRQ_UART           6
+#define C5471_IRQ_UART_IRDA      7
+#define C5471_IRQ_KBGPIO_8_15    8
+#define C5471_IRQ_GPIO3          9
+#define C5471_IRQ_GPIO2         10
+#define C5471_IRQ_I2C           11
+#define C5471_IRQ_GPIO1         12
+#define C5471_IRQ_SPI           13
+#define C5471_IRQ_GPIO_4_19     14
+#define C5471_IRQ_API           15
+
+#define C5471_IRQ_WATCHDOG      C5471_IRQ_TIMER0
+#define C5471_IRQ_SYSTIMER      C5471_IRQ_TIMER2
+#define NR_IRQS                 (C5471_IRQ_API+1)
+
+/************************************************************
+ * Public Types
+ ************************************************************/
+
+/************************************************************
+ * Inline functions
+ ************************************************************/
+
+/************************************************************
+ * Public Variables
+ ************************************************************/
+
+/************************************************************
+ * Public Function Prototypes
+ ************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_C5471_IRQ_H */
+

arch/arm/include/dm320/irq.h

@@ -0,0 +1,134 @@
+/************************************************************
+ * arch/dm320/irq.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/* This file should never be included directed but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_DM320_IRQ_H
+#define __ARCH_DM320_IRQ_H
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/* DM320 Interrupts */
+
+#define DM320_IRQ_TMR0      0 /* IRQ0:  Timer 0 Interrupt */
+#define DM320_IRQ_TMR1      1 /* IRQ1:  Timer 1 Interrupt */
+#define DM320_IRQ_TMR2      2 /* IRQ2:  Timer 2 Interrupt (CCD timer 0) */
+#define DM320_IRQ_TMR3      3 /* IRQ3:  Timer 3 Interrupt (CCD timer 1) */
+#define DM320_IRQ_CCDVD0    4 /* IRQ4:  CCD VD Interrupt #0 */
+#define DM320_IRQ_CCDVD1    5 /* IRQ5:  CCD VD Interrupt #1 */
+#define DM320_IRQ_CCDWEN    6 /* IRQ6:  CCD WEN Interrupt */
+#define DM320_IRQ_VENC      7 /* IRQ7:  Video Encoder Interrupt */
+#define DM320_IRQ_SP0       8 /* IRQ8:  Serial Port 0 Interrupt (with DMA) */
+#define DM320_IRQ_SP1       9 /* IRQ9:  Serial Port 1 Interrupt */
+#define DM320_IRQ_EXTHOST  10 /* IRQ10: External host interrupt */
+#define DM320_IRQ_IMGBUF   11 /* IRQ11: Image Buffer */
+#define DM320_IRQ_UART0    12 /* IRQ12: UART0 Interrupt */
+#define DM320_IRQ_UART1    13 /* IRQ13: UART1 Interrupt */
+#define DM320_IRQ_USB0     14 /* IRQ14: USB 0 Interrupt (DMA) */
+#define DM320_IRQ_USB1     15 /* IRQ15: USB 1 Interrupt (Core) */
+#define DM320_IRQ_VLYNQ    16 /* IRQ16: VLYNQ Interrupt */
+#define DM320_IRQ_MTC0     17 /* IRQ17: Memory Traffic Controller 0 (DMA) */
+#define DM320_IRQ_MTC1     18 /* IRQ18: Memory Traffic Controller 1 (CFC_RDY) */
+#define DM320_IRQ_MMCSD0   19 /* IRQ19: MMC/SD or MS 0 Interrupt */
+#define DM320_IRQ_MMCSD1   20 /* IRQ20: MMC/SD or MS 1 Interrupt */
+#define DM320_IRQ_EXT0     21 /* IRQ21: External Interrupt #0 (GIO0) */
+#define DM320_IRQ_EXT1     22 /* IRQ22: External Interrupt #1 (GIO1) */
+#define DM320_IRQ_EXT2     23 /* IRQ23: External Interrupt #2 (GIO2) */
+#define DM320_IRQ_EXT3     24 /* IRQ24: External Interrupt #3 (GIO3) */
+#define DM320_IRQ_EXT4     25 /* IRQ25: External Interrupt #4 (GIO4) */
+#define DM320_IRQ_EXT5     26 /* IRQ26: External Interrupt #5 (GIO5) */
+#define DM320_IRQ_EXT6     27 /* IRQ27: External Interrupt #6 (GIO6) */
+#define DM320_IRQ_EXT7     28 /* IRQ28: External Interrupt #7 (GIO7) */
+#define DM320_IRQ_EXT8     29 /* IRQ29: External Interrupt #8 (GIO8) */
+#define DM320_IRQ_EXT9     30 /* IRQ30: External Interrupt #9 (GIO9) */
+#define DM320_IRQ_EXT10    31 /* IRQ31: External Interrupt #10 (GIO10) */
+#define DM320_IRQ_EXT11    32 /* IRQ32: External Interrupt #11 (GIO11) */
+#define DM320_IRQ_EXT12    33 /* IRQ33: External Interrupt #12 (GIO12) */
+#define DM320_IRQ_EXT13    34 /* IRQ34: External Interrupt #13 (GIO13) */
+#define DM320_IRQ_EXT14    35 /* IRQ35: External Interrupt #14 (GIO14) */
+#define DM320_IRQ_EXT15    36 /* IRQ36: External Interrupt #15 (GIO15) */
+#define DM320_IRQ_PREV0    37 /* IRQ37: Preview Engine 0 (Preview Over) */
+#define DM320_IRQ_PREV1    38 /* IRQ38: Preview Engine 1 (Preview Historgram Over) */
+#define DM320_IRQ_WDT      39 /* IRQ39: Watchdog Timer Interrupt */
+#define DM320_IRQ_I2C      40 /* IRQ40: I2C Interrupt */
+#define DM320_IRQ_CLKC     41 /* IRQ41: Clock controller Interrupt (wake up) */
+#define DM320_IRQ_E2ICE    42 /* IRQ42: Embedded ICE Interrupt */
+#define DM320_IRQ_ARMCOMRX 43 /* IRQ43: ARMCOMM Receive Interrupt */
+#define DM320_IRQ_ARMCOMTX 44 /* IRQ44: ARMCOMM Transmit Interrupt */
+#define DM320_IRQ_RSV      45 /* IRQ45: Reserved Interrupt */
+
+#define DM320_IRQ_SYSTIMER DM320_IRQ_TMR0
+#define NR_IRQS            (DM320_IRQ_RSV+1)
+
+/************************************************************
+ * Public Types
+ ************************************************************/
+
+/************************************************************
+ * Inline functions
+ ************************************************************/
+
+/************************************************************
+ * Public Variables
+ ************************************************************/
+
+/************************************************************
+ * Public Function Prototypes
+ ************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_DM320_IRQ_H */
+

arch/arm/include/irq.h

@@ -0,0 +1,226 @@
+/************************************************************
+ * arch/irq.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/* This file should never be included directed but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_IRQ_H
+#define __ARCH_IRQ_H
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <arch/chip/irq.h>
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/* IRQ Stack Frame Format:
+ *
+ * Context is always saved/restored in the same way:
+ *
+ *   (1) stmia rx, {r0-r14}
+ *   (2) then the PC and CPSR
+ *
+ * This results in the following set of indices that
+ * can be used to access individual registers in the
+ * xcp.regs array:
+ */
+
+#define REG_R0              (0)
+#define REG_R1              (1)
+#define REG_R2              (2)
+#define REG_R3              (3)
+#define REG_R4              (4)
+#define REG_R5              (5)
+#define REG_R6              (6)
+#define REG_R7              (7)
+#define REG_R8              (8)
+#define REG_R9              (9)
+#define REG_R10             (10)
+#define REG_R11             (11)
+#define REG_R12             (12)
+#define REG_R13             (13)
+#define REG_R14             (14)
+#define REG_R15             (15)
+#define REG_CPSR            (16)
+
+#define XCPTCONTEXT_REGS    (17)
+#define XCPTCONTEXT_SIZE    (4 * XCPTCONTEXT_REGS)
+
+#define REG_A1              REG_R0
+#define REG_A2              REG_R1
+#define REG_A3              REG_R2
+#define REG_A4              REG_R3
+#define REG_V1              REG_R4
+#define REG_V2              REG_R5
+#define REG_V3              REG_R6
+#define REG_V4              REG_R7
+#define REG_V5              REG_R8
+#define REG_V6              REG_R9
+#define REG_V7              REG_R10
+#define REG_SB              REG_R9
+#define REG_SL              REG_R10
+#define REG_FP              REG_R11
+#define REG_IP              REG_R12
+#define REG_SP              REG_R13
+#define REG_LR              REG_R14
+#define REG_PC              REG_R15
+
+/************************************************************
+ * Public Types
+ ************************************************************/
+
+/* This struct defines the way the registers are stored.  We
+ * need to save:
+ *
+ *  1	CPSR
+ *  7	Static registers, v1-v7 (aka r4-r10)
+ *  1	Frame pointer, fp (aka r11)
+ *  1	Stack pointer, sp (aka r13)
+ *  1	Return address, lr (aka r14)
+ * ---
+ * 11	(XCPTCONTEXT_USER_REG)
+ *
+ * On interrupts, we also need to save:
+ *  4	Volatile registers, a1-a4 (aka r0-r3)
+ *  1	Scratch Register, ip (aka r12)
+ *---
+ *  5	(XCPTCONTEXT_IRQ_REGS)
+ *
+ * For a total of 17 (XCPTCONTEXT_REGS)
+ */
+
+#ifndef __ASSEMBLY__
+struct xcptcontext
+{
+  /* The following function pointer is non-zero if there
+   * are pending signals to be processed.
+   */
+
+  void *sigdeliver; /* Actual type is sig_deliver_t */
+
+  /* These are saved copies of LR and CPSR used during
+   * signal processing.
+   */
+
+  uint32 saved_pc;
+  uint32 saved_cpsr;
+
+  /* Register save area */
+
+  uint32 regs[XCPTCONTEXT_REGS];
+};
+#endif
+
+/************************************************************
+ * Inline functions
+ ************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* Save the current interrupt enable state & disable IRQs */
+
+static inline irqstate_t irqsave(void)
+{
+  unsigned int flags;
+  unsigned int temp;
+  __asm__ __volatile__
+    (
+     "\tmrs    %0, cpsr\n"
+     "\torr    %1, %0, #128\n"
+     "\tmsr    cpsr_c, %1"
+     : "=r" (flags), "=r" (temp)
+     :
+     : "memory");
+  return flags;
+}
+
+/* Restore saved IRQ & FIQ state */
+
+static inline void irqrestore(irqstate_t flags)
+{
+  __asm__ __volatile__
+    (
+     "msr    cpsr_c, %0"
+     :
+     : "r" (flags)
+     : "memory");
+}
+
+static inline void system_call(swint_t func, int parm1,
+			       int parm2, int parm3)
+{
+  __asm__ __volatile__
+    (
+     "mov\tr0,%0\n\t"
+     "mov\tr1,%1\n\t"
+     "mov\tr2,%2\n\t"
+     "mov\tr3,%3\n\t"
+     "swi\t0x900001\n\t"
+     :
+     : "r" ((long)(func)),  "r" ((long)(parm1)),
+       "r" ((long)(parm2)), "r" ((long)(parm3))
+     : "r0", "r1", "r2", "r3", "lr");
+}
+#endif
+
+/************************************************************
+ * Public Variables
+ ************************************************************/
+
+/************************************************************
+ * Public Function Prototypes
+ ************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_IRQ_H */
+

arch/arm/include/limits.h

@@ -0,0 +1,75 @@
+/************************************************************
+ * limits.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+#ifndef __ARCH_LIMITS_H
+#define __ARCH_LIMITS_H
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+#define CHAR_BIT        8
+#define SCHAR_MIN	0x80
+#define SCHAR_MAX	0x7f
+#define UCHAR_MAX	0xff
+
+/* These could be different on machines where char is unsigned */
+
+#define CHAR_MIN	SCHAR_MIN
+#define CHAR_MAX	SCHAR_MAX
+
+#define SHRT_MIN	0x8000
+#define SHRT_MAX	0x7fff
+#define USHRT_MAX	0xffff
+
+#define INT_MIN         0x80000000
+#define INT_MAX         0x7fffffff
+#define UINT_MAX	0xffffffff
+
+/* These change on 32-bit and 64-bit platforms */
+
+#define LONG_MAX	0x80000000
+#define LONG_MIN	0x7fffffff
+#define ULONG_MAX	0xffffffff
+
+#define LLONG_MAX	0x8000000000000000
+#define LLONG_MIN	0x7fffffffffffffff
+#define ULLONG_MAX	0xffffffffffffffff
+
+#endif /* __ARCH_LIMITS_H */

arch/arm/include/lpc214x/irq.h

@@ -0,0 +1,126 @@
+/****************************************************************************
+ * arch/lpc214x/irq.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_LPC214X_IRQ_H
+#define __ARCH_LPC214X_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* LPC214X Interrupts */
+
+#define LPC214X_WDT_IRQ        0 /* Watchdog */
+#define LPC214X_RESERVED_IRQ   1 /* SWI only */
+#define LPC214X_DBGCOMMRX_IRQ  2 /* Embedded debug */
+#define LPC214X_DBGCOMMTX_IRQ  3 /* Embedded debug */
+#define LPC214X_TIMER0_IRQ     4 /* Timer 0 */
+#define LPC214X_TIMER1_IRQ     5 /* Timer 1 */
+#define LPC214X_UART0_IRQ      6 /* UART 0 */
+#define LPC214X_UART1_IRQ      7 /* UART 1 */
+#define LPC214X_PWM0_IRQ       8 /* PWM 0 */
+#define LPC214X_I2C0_IRQ       9 /* I2C 0 */
+#define LPC214X_SPI0_IRQ      10 /* SPI 0 */
+#define LPC214X_SPI1_IRQ      11 /* SPI 1 */
+#define LPC214X_PLL_IRQ       12 /* PLL Lock IRQ */
+#define LPC214X_RTC_IRQ       13 /* Real Time Clock */
+#define LPC214X_EINT0_IRQ     14 /* External interrupt 0 */
+#define LPC214X_EINT1_IRQ     15 /* External interrupt 1 */
+#define LPC214X_EINT2_IRQ     16 /* External interrupt 2 */
+#define LPC214X_EINT3_IRQ     17 /* External interrupt 3 */
+#define LPC214X_ADC0_IRQ      18 /* ADC 0 */
+#define LPC214X_I2C1_IRQ      19 /* I2C 1 */
+#define LPC214X_BOD_IRQ       20 /* Brown Out Detect */
+#define LPC214X_ADC1_IRQ      21 /* ADC 1 */
+#define LPC214X_USB_IRQ       22 /* USB */
+
+#define LPC214X_IRQ_SYSTIMER  LPC214X_TIMER0_IRQ
+#define NR_IRQS               23
+
+/* There are 16 vectored interrupts.  If vectored interrupts are enabled, the
+ * following will be used by the system.
+ */
+
+#define LPC214X_SYSTEMER_VEC  0 /* System timer */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*vic_vector_t)(uint32 *regs);
+#endif
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#ifndef CONFIG_VECTORED_INTERRUPTS
+EXTERN void up_attach_vector(int irq, int vector, vic_vector_t handler);
+EXTERN void up_detach_vector(int vector);
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_LPC214X_IRQ_H */
+

arch/arm/include/serial.h

@@ -0,0 +1,61 @@
+/************************************************************
+ * arch/serial.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+#ifndef __ARCH_SERIAL_H
+#define __ARCH_SERIAL_H
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/* IOCTL commands supported by the ARM serial driver */
+
+#define TIOCSBRK        0x5401  /* BSD compatibility */
+#define TIOCCBRK        0x5402  /* " " "           " */
+#define TIOCSERGSTRUCT  0x5403  /* Get up_dev_t for port */
+
+/************************************************************
+ * Public Data
+ ************************************************************/
+
+/************************************************************
+ * Public Functions
+ ************************************************************/
+
+#endif /* __ARCH_SERIAL_H */

arch/arm/include/types.h

@@ -0,0 +1,82 @@
+/************************************************************
+ * arch/types.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/* This file should never be included directed but, rather,
+ * only indirectly through sys/types.h
+ */
+
+#ifndef __ARCH_TYPES_H
+#define __ARCH_TYPES_H
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/************************************************************
+ * Type Declarations
+ ************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* These are the sizes of the standard GNU types */
+
+typedef char sbyte;
+typedef unsigned char ubyte;
+typedef unsigned char uint8;
+typedef unsigned char boolean;
+typedef short sint16;
+typedef unsigned short uint16;
+typedef int sint32;
+typedef unsigned int uint32;
+typedef long long sint64;
+typedef unsigned long long uint64;
+
+/* This is the size of the interrupt state save returned by
+ * irqsave()
+ */
+
+typedef unsigned int irqstate_t;
+
+#endif /* __ASSEMBLY__ */
+
+/************************************************************
+ * Global Function Prototypes
+ ************************************************************/
+
+#endif /* __ARCH_TYPES_H */

arch/arm/include/watchdog.h

@@ -0,0 +1,63 @@
+/************************************************************
+ * watchdog.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+#ifndef __ARCH_WATCHDOG_H
+#define __ARCH_WATCHDOG_H
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/* IOCTL commands supported by the C5471 watchdog driver */
+
+#define WDIOC_KEEPALIVE 0x5701  /* Restart the watchdog timer */
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/************************************************************
+ * Private Functions
+ ************************************************************/
+
+/************************************************************
+ * Public Functions
+ ************************************************************/
+
+#endif /* __ARCH_WATCHDOG_H */

arch/arm/src/Makefile

@@ -0,0 +1,124 @@
+############################################################################
+# Makefile
+#
+#   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name Gregory Nutt nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+-include $(TOPDIR)/Make.defs
+-include chip/Make.defs
+
+MKDEP 		= $(TOPDIR)/tools/mkdeps.sh
+ARCH_SRCDIR	= $(TOPDIR)/arch/$(CONFIG_ARCH)/src
+CFLAGS		+= -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(TOPDIR)/sched
+
+HEAD_AOBJ	= $(HEAD_ASRC:.S=$(OBJEXT))
+
+ASRCS		= $(CHIP_ASRCS) $(CMN_ASRCS)
+AOBJS		= $(ASRCS:.S=$(OBJEXT))
+
+CSRCS		= $(CHIP_CSRCS) $(CMN_CSRCS)
+COBJS		= $(CSRCS:.c=$(OBJEXT))
+
+SRCS		= $(ASRCS) $(CSRCS)
+OBJS		= $(AOBJS) $(COBJS)
+
+LDFLAGS		= $(ARCHSCRIPT)
+EXTRA_LIBS	=
+
+LINKLIBS	=
+LDPATHES	= $(addprefix -L$(TOPDIR)/,$(dir $(LINKLIBS)))
+LDLIBS		= $(patsubst lib%,-l%,$(basename $(notdir $(LINKLIBS))))
+
+BOARDDIR	= $(TOPDIR)/arch/$(CONFIG_ARCH)/src/board
+
+LIBGCC		= ${shell $(CC) -print-libgcc-file-name}
+
+VPATH		= chip:common
+
+all: $(HEAD_OBJ) libarch$(LIBEXT)
+
+$(AOBJS) $(HEAD_AOBJ): %$(OBJEXT): %.S
+	$(CC) -c $(CFLAGS) -D__ASSEMBLY__ $< -o $@
+
+$(COBJS): %$(OBJEXT): %.c
+	$(CC) -c $(CFLAGS) $< -o $@
+
+libarch$(LIBEXT): $(OBJS)
+	@( for obj in $(OBJS) ; do \
+		$(AR) $@ $${obj} || \
+			{ echo "$(AR) $@ $obj FAILED!" ; exit 1 ; } ; \
+	done ; )
+
+board/libboard$(LIBEXT):
+	$(MAKE) -C board TOPDIR=$(TOPDIR) libboard$(LIBEXT)
+
+nuttx: $(HEAD_AOBJ) board/libboard$(LIBEXT)
+	$(LD) --entry=__start $(LDFLAGS) $(LDPATHES) -L$(BOARDDIR) -o $(TOPDIR)/$@ $(HEAD_AOBJ) \
+		--start-group $(LDLIBS) -lboard --end-group $(EXTRA_LIBS) $(LIBGCC) 
+	@$(NM) $(TOPDIR)/$@ | \
+	grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
+	sort > $(TOPDIR)/System.map
+	@export vflashstart=`$(OBJDUMP) --all-headers $(TOPDIR)/$@ | grep _vflashstart | cut -d' ' -f1`;  \
+	if [ ! -z "$$vflashstart" ]; then \
+		$(OBJCOPY) --adjust-section-vma=.vector=0x$$vflashstart $(TOPDIR)/$@ $(TOPDIR)/$@.flashimage; \
+		mv $(TOPDIR)/$@.flashimage $(TOPDIR)/$@; \
+	fi
+ifeq ($(CONFIG_RRLOAD_BINARY),y)
+	@$(TOPDIR)/tools/mkimage.sh --Prefix $(CROSSDEV) $(TOPDIR)/$@ $(TOPDIR)/$@.rr
+	@if [ -w /tftpboot ] ; then \
+		cp -f $(TOPDIR)/$@.rr /tftpboot/$@.rr.${CONFIG_ARCH}; \
+	fi
+endif
+
+.depend: Makefile chip/Make.defs $(SRCS)
+	@if [ -e board/Makefile ]; then \
+		$(MAKE) -C board TOPDIR=$(TOPDIR) depend ; \
+	fi
+	$(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep
+	@touch $@
+
+depend: .depend
+
+clean:
+	@if [ -e board/Makefile ]; then \
+		$(MAKE) -C board TOPDIR=$(TOPDIR) clean ; \
+	fi
+	@rm -f libarch$(LIBEXT) *~
+	@if [ ! -z "$(OBJEXT)" ]; then rm -f *$(OBJEXT); fi
+
+distclean: clean
+	@if [ -e board/Makefile ]; then \
+		$(MAKE) -C board TOPDIR=$(TOPDIR) distclean ; \
+	fi
+	@rm -f Make.dep .depend
+
+-include Make.dep

arch/arm/src/c5471/Make.defs

@@ -0,0 +1,48 @@
+############################################################################
+# c5471/Make.defs
+#
+#   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name Gregory Nutt nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+HEAD_ASRC	= up_nommuhead.S
+
+CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S
+CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
+		  up_createstack.c up_dataabort.c up_delay.c up_doirq.c \
+		  up_exit.c up_idle.c up_initialize.c up_initialstate.c \
+		  up_interruptcontext.c up_prefetchabort.c up_releasepending.c \
+		  up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \
+		  up_sigdeliver.c up_syscall.c up_unblocktask.c \
+		  up_undefinedinsn.c up_usestack.c
+
+CHIP_ASRCS	= c5471_lowputc.S c5471_vectors.S
+CHIP_CSRCS	= c5471_irq.c c5471_serial.c c5471_timerisr.c c5471_watchdog.c

arch/arm/src/c5471/c5471_irq.c

@@ -0,0 +1,242 @@
+/************************************************************
+ * c5471/c5471_irq.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <nuttx/irq.h>
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+#define ILR_EDGESENSITIVE 0x00000020
+#define ILR_PRIORITY      0x0000001E
+
+/************************************************************
+ * Public Data
+ ************************************************************/
+
+uint32 *current_regs;
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/* The value of _vflashstart is defined in ld.script.  It
+ * could be hard-coded because we know that correct IRAM
+ * area is 0xffc00000.
+ */
+
+extern int _svectors; /* Type does not matter */
+
+/* The C5471 has FLASH at the low end of memory.  The
+ * rrload bootloaer will catch all interrupts and re-vector
+ * them to vectors stored in IRAM.  The following table is
+ * used to initialize those vectors.
+ */
+
+static up_vector_t g_vectorinittab[] =
+{
+  (up_vector_t)NULL,
+  up_vectorundefinsn,
+  up_vectorswi,
+  up_vectorprefetch,
+  up_vectordata,
+  up_vectoraddrexcptn,
+  up_vectorirq,
+  up_vectorfiq
+};
+#define NVECTORS ((sizeof(g_vectorinittab)) / sizeof(up_vector_t))
+
+/************************************************************
+ * Private Functions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_ackirq
+ *
+ * Description:
+ *   Acknowlede the IRQ.Bit 0 of the Interrupt Control
+ *   Register ==  New IRQ agreement (NEW_IRQ_AGR). Reset IRQ
+ *   output. Clear source IRQ register. Enables a new IRQ
+ *   generation. Reset by internal logic.
+ *
+ ************************************************************/
+
+static inline void up_ackirq(unsigned int irq)
+{
+  uint32 reg;
+  reg = getreg32(SRC_IRQ_REG);              /* Insure appropriate IT_REG bit clears */
+  putreg32(reg | 0x00000001, INT_CTRL_REG); /* write the NEW_IRQ_AGR bit. */
+}
+
+/************************************************************
+ * Name: up_ackfiq
+ *
+ * Description:
+ *   Acknowledge the FIQ.  Bit 1 of the Interrupt Control
+ *   Register ==  New FIQ agreement (NEW_FIQ_AGR). Reset FIQ
+ *   output. Clear source FIQ register. Enables a new FIQ
+ *   generation. Reset by internal logic.
+ *
+ ************************************************************/
+
+static inline void up_ackfiq(unsigned int irq)
+{
+  uint32 reg;
+  reg = getreg32(SRC_FIQ_REG);              /* Insure appropriate IT_REG bit clears */
+  putreg32(reg | 0x00000002, INT_CTRL_REG); /* write the NEW_FIQ_AGR bit. */
+}
+
+/************************************************************
+ * Name: up_vectorinitialize
+ ************************************************************/
+
+static inline void up_vectorinitialize(void)
+{
+  up_vector_t *src  = g_vectorinittab;
+  up_vector_t *dest = (up_vector_t*)&_svectors;
+  int i;
+
+  for (i = 0; i < NVECTORS; i++)
+    {
+      *dest++ = *src++;
+    }
+}
+
+/************************************************************
+ * Public Funtions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_irqinitialize
+ ************************************************************/
+
+void up_irqinitialize(void)
+{
+  /* Disable all interrupts. */
+
+  putreg32(0x0000ffff, MASK_IT_REG);
+
+  /* Clear any pending interrupts */
+
+  up_ackirq(0);
+  up_ackfiq(0);
+  putreg32(0x00000000, IT_REG);
+
+  /* Override hardware defaults */
+
+  putreg32(ILR_EDGESENSITIVE | ILR_PRIORITY, ILR_IRQ2_REG);
+  putreg32(ILR_EDGESENSITIVE | ILR_PRIORITY, ILR_IRQ4_REG);
+  putreg32(ILR_PRIORITY,                     ILR_IRQ6_REG);
+  putreg32(ILR_EDGESENSITIVE | ILR_PRIORITY, ILR_IRQ15_REG);
+
+  /* Initialize hardware interrupt vectors */
+
+  up_vectorinitialize();
+  current_regs = NULL;
+
+  /* And finally, enable interrupts */
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+  irqrestore(SVC_MODE | PSR_F_BIT);
+#endif
+}
+
+/************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ *   Disable the IRQ specified by 'irq'
+ *
+ ************************************************************/
+
+void up_disable_irq(int irq)
+{
+  if ((unsigned)irq < NR_IRQS)
+    {
+      uint32 reg = getreg32(MASK_IT_REG);
+      putreg32(reg | (1 << irq), MASK_IT_REG);
+    }
+}
+
+/************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ *   Enable the IRQ specified by 'irq'
+ *
+ ************************************************************/
+
+void up_enable_irq(int irq)
+{
+  if ((unsigned)irq < NR_IRQS)
+    {
+      uint32 reg = getreg32(MASK_IT_REG);
+      putreg32(reg & ~(1 << irq), MASK_IT_REG);
+    }
+}
+
+/************************************************************
+ * Name: up_maskack_irq
+ *
+ * Description:
+ *   Mask the IRQ and acknowledge it
+ *
+ ************************************************************/
+
+void up_maskack_irq(int irq)
+{
+  uint32 reg = getreg32(INT_CTRL_REG);
+
+  /* Mask the interrupt */
+
+  reg = getreg32(MASK_IT_REG);
+  putreg32(reg | (1 << irq), MASK_IT_REG);
+
+  /* Set the NEW_IRQ_AGR bit.  This clears the IRQ src register
+   * enables generation of a new IRQ.
+   */
+
+  reg = getreg32(INT_CTRL_REG);
+  putreg32(reg | 0x00000001, INT_CTRL_REG); /* write the NEW_IRQ_AGR bit. */
+}

arch/arm/src/c5471/c5471_lowputc.S

@@ -0,0 +1,127 @@
+/**************************************************************************
+ * c5471/c5471_lowputc.S
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ **************************************************************************/
+
+/**************************************************************************
+ * Included Files
+ **************************************************************************/
+
+#include <nuttx/config.h>
+#include "up_internal.h"
+#include "up_arch.h"
+
+/**************************************************************************
+ * Private Definitions
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Types
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Function Prototypes
+ **************************************************************************/
+
+/**************************************************************************
+ * Global Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Public Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Name: up_lowputc
+ **************************************************************************/
+
+/* This assembly language version has the advantage that it can does not
+ * require a C stack and uses only r0-r1.  Hence it can be used during
+ * early boot phases.
+ */
+
+	.text
+	.global	up_lowputc
+	.type	up_lowputc, function
+up_lowputc:
+	/* On entry, r0 holds the character to be printed */
+
+#ifdef CONFIG_SERIAL_IRDA_CONSOLE
+	ldr	r2, =UART_IRDA_BASE	/* r2=IRDA UART base */
+#else
+	ldr	r2, =UART_MODEM_BASE	/* r2=Modem UART base */
+#endif
+
+	/* Poll bit 0 of the UART_SSR register.  When the bit
+	 * is clear, the TX FIFO is no longer full
+	 */
+
+1:	ldr	r1, [r2, #UART_SSR_OFFS]
+	tst	r1, #UART_SSR_TXFULL
+	bne	1b
+
+	/* Send the character by writing it into the UART_THR
+	 * register.
+	 */
+
+	str     r0, [r2, #UART_THR_OFFS]
+
+	/* Wait for the tranmsit holding regiser (THR) to be
+	 * emptied. This is detemined when bit 6 of the LSR
+	 * is set.
+	 */
+
+2:	ldr     r1, [r2, #UART_LSR_OFFS]
+	tst     r1, #0x00000020
+	beq     2b
+
+	/* If the character that we just sent was a linefeed,
+	 * then send a carriage return as well.
+	 */
+
+	teq     r0, #'\n'
+	moveq   r0, #'\r'
+	beq     1b
+
+	/* And return */
+
+	mov     pc, lr
+

arch/arm/src/c5471/c5471_serial.c

@@ -0,0 +1,811 @@
+/************************************************************
+ * c5471/c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471c5471_serial.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <unistd.h>
+#include <semaphore.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/serial.h>
+#include <arch/serial.h>
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+#define BASE_BAUD     115200
+
+#if defined(CONFIG_UART_IRDA_HWFLOWCONTROL) || defined(CONFIG_UART_MODEM_HWFLOWCONTROL)
+# define CONFIG_UART_HWFLOWCONTROL
+#endif
+
+/************************************************************
+ * Private Types
+ ************************************************************/
+
+struct uart_regs_s
+{
+  uint32  ier;
+  uint32  lcr;
+  uint32  fcr;
+#ifdef CONFIG_UART_HWFLOWCONTROL
+  uint32  efr;
+  uint32  tcr;
+#endif
+};
+
+struct up_dev_s
+{
+  unsigned int         uartbase;	/* Base address of UART
+					 * registers */
+  unsigned int         baud_base;	/* Base baud for conversions */
+  unsigned int         baud;		/* Configured baud */
+  ubyte                xmit_fifo_size;	/* Size of transmit FIFO */
+  ubyte                irq;		/* IRQ associated with
+					 * this UART */
+  ubyte                parity;		/* 0=none, 1=odd, 2=even */
+  ubyte                bits;		/* Number of bits (7 or 8) */
+#ifdef CONFIG_UART_HWFLOWCONTROL
+  boolean              flowcontrol;	/* TRUE: Hardware flow control
+					 * is enabled. */
+#endif
+  boolean              stopbits2;	/* TRUE: Configure with 2
+					 * stop bits instead of 1 */
+  struct uart_regs_s   regs;		/* Shadow copy of readonly regs */
+};
+
+/************************************************************
+ * Private Function Prototypes
+ ************************************************************/
+
+static int     up_setup(struct uart_dev_s *dev);
+static void    up_shutdown(struct uart_dev_s *dev);
+static int     up_interrupt(int irq, void *context);
+static int     up_ioctl(struct file *filep, int cmd, unsigned long arg);
+static int     up_receive(struct uart_dev_s *dev, unsigned int *status);
+static void    up_rxint(struct uart_dev_s *dev, boolean enable);
+static boolean up_rxfifonotempty(struct uart_dev_s *dev);
+static void    up_send(struct uart_dev_s *dev, int ch);
+static void    up_txint(struct uart_dev_s *dev, boolean enable);
+static boolean up_txfifonotfull(struct uart_dev_s *dev);
+static boolean up_txfifoempty(struct uart_dev_s *dev);
+
+/************************************************************
+ * Private Variables
+ ************************************************************/
+
+struct uart_ops_s g_uart_ops =
+{
+  .setup          = up_setup,
+  .shutdown       = up_shutdown,
+  .handler        = up_interrupt,
+  .ioctl          = up_ioctl,
+  .receive        = up_receive,
+  .rxint          = up_rxint,
+  .rxfifonotempty = up_rxfifonotempty,
+  .send           = up_send,
+  .txint          = up_txint,
+  .txfifonotfull  = up_txfifonotfull,
+  .txfifoempty    = up_txfifoempty,
+};
+
+/* I/O buffers */
+
+static char g_irdarxbuffer[CONFIG_UART_IRDA_RXBUFSIZE];
+static char g_irdatxbuffer[CONFIG_UART_IRDA_TXBUFSIZE];
+static char g_modemrxbuffer[CONFIG_UART_MODEM_RXBUFSIZE];
+static char g_modemtxbuffer[CONFIG_UART_MODEM_TXBUFSIZE];
+
+/* This describes the state of the C5471 serial IRDA port. */
+
+static struct up_dev_s g_irdapriv =
+{
+  .xmit_fifo_size = UART_IRDA_XMIT_FIFO_SIZE,
+  .baud_base      = BASE_BAUD,
+  .uartbase       = UART_IRDA_BASE,
+  .baud           = CONFIG_UART_IRDA_BAUD,
+  .parity         = CONFIG_UART_IRDA_PARITY,
+  .bits           = CONFIG_UART_IRDA_BITS,
+#ifdef CONFIG_UART_IRDA_HWFLOWCONTROL
+  .flowcontrol    = TRUE,
+#endif
+  .stopbits2      = CONFIG_UART_IRDA_2STOP,
+};
+
+static uart_dev_t g_irdaport =
+{
+  .irq      = C5471_IRQ_UART_IRDA,
+  .recv     =
+  {
+    .size   = CONFIG_UART_IRDA_RXBUFSIZE,
+    .buffer = g_irdarxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART_IRDA_TXBUFSIZE,
+    .buffer = g_irdatxbuffer,
+   },
+  .ops      = &g_uart_ops,
+  .priv     = &g_irdapriv,
+};
+
+/* This describes the state of the C5471 serial Modem port. */
+
+static struct up_dev_s g_modempriv =
+{
+  .xmit_fifo_size = UART_XMIT_FIFO_SIZE,
+  .baud_base      = BASE_BAUD,
+  .uartbase       = UART_MODEM_BASE,
+  .baud           = CONFIG_UART_MODEM_BAUD,
+  .parity         = CONFIG_UART_MODEM_PARITY,
+  .bits           = CONFIG_UART_MODEM_BITS,
+#ifdef CONFIG_UART_MODEM_HWFLOWCONTROL
+  .flowcontrol    = TRUE,
+#endif
+  .stopbits2      = CONFIG_UART_MODEM_2STOP,
+};
+
+static uart_dev_t g_modemport =
+{
+  .irq      = C5471_IRQ_UART,
+  .recv     =
+  {
+    .size   = CONFIG_UART_MODEM_RXBUFSIZE,
+    .buffer = g_modemrxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART_MODEM_TXBUFSIZE,
+    .buffer = g_modemtxbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_modempriv,
+};
+
+/* Now, which one with be tty0/console and which tty1? */
+
+#ifdef CONFIG_SERIAL_IRDA_CONSOLE
+# define CONSOLE_DEV     g_irdaport
+# define TTYS0_DEV       g_irdaport
+# define TTYS1_DEV       g_modemport
+#else
+# define CONSOLE_DEV     g_modemport
+# define TTYS0_DEV       g_modemport
+# define TTYS1_DEV       g_irdaport
+#endif
+
+/************************************************************
+ * Private Functions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_inserial
+ ************************************************************/
+
+static inline uint32 up_inserial(struct up_dev_s *priv, uint32 offset)
+{
+  return getreg32(priv->uartbase + offset);
+}
+
+/************************************************************
+ * Name: up_serialout
+ ************************************************************/
+
+static inline void up_serialout(struct up_dev_s *priv, uint32 offset, uint32 value)
+{
+  putreg32(value, priv->uartbase + offset);
+}
+
+/************************************************************
+ * Name: up_disableuartint
+ ************************************************************/
+
+static inline void up_disableuartint(struct up_dev_s *priv, uint16 *ier)
+{
+  if (ier)
+    {
+      *ier = priv->regs.ier & UART_IER_INTMASK;
+    }
+  priv->regs.ier &= ~UART_IER_INTMASK;
+  up_serialout(priv, UART_IER_OFFS, priv->regs.ier);
+}
+
+/************************************************************
+ * Name: up_restoreuartint
+ ************************************************************/
+
+static inline void up_restoreuartint(struct up_dev_s *priv, uint16 ier)
+{
+  priv->regs.ier |= ier & (UART_IER_RECVINT|UART_IER_XMITINT);
+  up_serialout(priv, UART_IER_OFFS, priv->regs.ier);
+}
+
+/************************************************************
+ * Name: up_waittxfifonotfull
+ ************************************************************/
+
+static inline void up_waittxfifonotfull(struct up_dev_s *priv)
+{
+  int tmp;
+
+  for (tmp = 1000 ; tmp > 0 ; tmp--)
+    {
+      if ((up_inserial(priv, UART_SSR_OFFS) & UART_SSR_TXFULL) == 0)
+        {
+          break;
+        }
+    }
+}
+/************************************************************
+ * Name: up_disablebreaks
+ ************************************************************/
+
+static inline void up_disablebreaks(struct up_dev_s *priv)
+{
+  priv->regs.lcr &= ~UART_LCR_BOC;
+  up_serialout(priv, UART_LCR_OFFS, priv->regs.lcr);
+}
+
+/************************************************************
+ * Name: up_enablebreaks
+ ************************************************************/
+
+static inline void up_enablebreaks(struct up_dev_s *priv)
+{
+  priv->regs.lcr |= UART_LCR_BOC;
+  up_serialout(priv, UART_LCR_OFFS, priv->regs.lcr);
+}
+
+/************************************************************
+ * Name: up_setrate
+ ************************************************************/
+
+static inline void up_setrate(struct up_dev_s *priv, unsigned int rate)
+{
+  uint32 div_bit_rate;
+
+  switch (rate)
+    {
+    case 115200:
+      div_bit_rate = BAUD_115200;
+      break;
+    case 57600:
+      div_bit_rate = BAUD_57600;
+      break;
+    case 38400:
+      div_bit_rate = BAUD_38400;
+      break;
+    case 19200:
+      div_bit_rate = BAUD_19200;
+      break;
+    case 4800:
+      div_bit_rate = BAUD_4800;
+      break;
+    case 2400:
+      div_bit_rate = BAUD_2400;
+      break;
+    case 1200:
+      div_bit_rate = BAUD_1200;
+      break;
+    case 9600:
+    default:
+      div_bit_rate = BAUD_9600;
+      break;
+    }
+
+  up_serialout(priv, UART_DIV_BIT_RATE_OFFS, div_bit_rate);
+}
+
+/************************************************************
+ * Name: up_setup
+ *
+ * Description:
+ *   Configure the UART baud, bits, parity, fifos, etc. This
+ *   method is called the first time that the serial port is
+ *   opened.
+ *
+ ************************************************************/
+
+static int up_setup(struct uart_dev_s *dev)
+{
+#ifdef CONFIG_SUPPRESS_UART_CONFIG
+  struct up_dev_s *priv = dev->priv;
+  unsigned int cval;
+
+  if (priv->bits == 7)
+    {
+      cval = UART_LCR_7BITS;
+    }
+  else
+    {
+      cval = UART_LCR_8BITS;
+    }
+
+  if (priv->stopbits2)
+    {
+      cval |= UART_LCR_2STOP;
+    }
+
+  if (priv->parity == 1)   /* Odd parity */
+    {
+      cval |= (UART_LCR_PAREN|UART_LCR_PARODD);
+    }
+  else if (priv->parity == 2)  /* Even parity */
+    {
+      cval |= (UART_LCR_PAREN|UART_LCR_PAREVEN);
+    }
+
+  /* Both the IrDA and MODEM UARTs support RESET and UART mode. */
+
+  up_serialout(priv, UART_MDR_OFFS, MDR_RESET_MODE);
+  up_delay(5);
+  up_serialout(priv, UART_MDR_OFFS, MDR_UART_MODE);
+  up_delay(5);
+
+  priv->regs.ier = up_inserial(priv, UART_IER_OFFS);
+  priv->regs.lcr = up_inserial(priv, UART_LCR_OFFS);
+#ifdef CONFIG_UART_HWFLOWCONTROL
+  if (priv->flowcontrol)
+    {
+      priv->regs.efr = up_inserial(priv, UART_EFR_OFFS);
+      priv->regs.tcr = up_inserial(priv, UART_TCR_OFFS);
+    }
+#endif
+
+  up_disableuartint(priv, NULL);
+
+  up_serialout(priv, UART_EFR_OFFS,  0x0010);           /* Enable fifo control */
+  up_serialout(priv, UART_TFCR_OFFS, 0);                /* Reset to 0 */
+  up_serialout(priv, UART_RFCR_OFFS, UART_FCR_RX_CLR);  /* Clear RX fifo */
+  up_serialout(priv, UART_TFCR_OFFS, UART_FCR_TX_CLR);  /* Clear TX fifo */
+  up_serialout(priv, UART_TFCR_OFFS, UART_FCR_FIFO_EN); /* Enable RX/TX fifos */
+
+  up_disablebreaks(priv);
+
+  priv->regs.fcr = (priv->regs.fcr & 0xffffffcf) | (val & 0x30);
+  up_serialout(priv, UART_RFCR_OFFS, priv->regs.fcr);
+
+  priv->regs.fcr = (priv->regs.fcr & 0xffffff3f) | (val & 0xc0);
+  up_serialout(priv, UART_RFCR_OFFS, priv->regs.fcr);
+
+  up_setrate(priv, priv->baud);
+
+  priv->regs.lcr &= 0xffffffe0;      /* clear original field, and... */
+  priv->regs.lcr |= (uint32)mode;    /* Set new bits in that field. */
+  up_serialout(priv, UART_LCR_OFFS, priv->regs.lcr);
+
+#ifdef CONFIG_UART_HWFLOWCONTROL
+  if (priv->flowcontrol)
+    {
+      /* Set the FIFO level triggers for flow control
+       * Halt = 48 bytes, resume = 12 bytes
+       */
+
+      priv->regs.tcr = (priv->regs.tcr & 0xffffff00) | 0x0000003c;
+      up_serialout(priv, UART_TCR_OFFS, priv->regs.tcr);
+
+      /* Enable RTS/CTS flow control */
+
+      priv->regs.efr |= 0x000000c0;
+      up_serialout(priv, UART_EFR_OFFS, priv->regs.efr);
+    }
+  else
+    {
+      /* Disable RTS/CTS flow control */
+
+      priv->regs.efr &= 0xffffff3f;
+      up_serialout(priv, UART_EFR_OFFS, priv->regs.efr);
+    }
+#endif
+#endif
+  return OK;
+}
+
+/************************************************************
+ * Name: up_shutdown
+ *
+ * Description:
+ *   Disable the UART.  This method is called when the serial port is closed
+ *
+ ************************************************************/
+
+static void up_shutdown(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
+  up_disableuartint(priv, NULL);
+}
+
+/************************************************************
+ * Name: up_interrupt
+ *
+ * Description:
+ *   This is the UART interrupt handler.  It will be invoked
+ *   when an interrupt received on the 'irq'  It should call
+ *   uart_transmitchars or uart_receivechar to perform the
+ *   appropriate data transfers.  The interrupt handling logic\
+ *   must be able to map the 'irq' number into the approprite
+ *   uart_dev_s structure in order to call these functions.
+ *
+ ************************************************************/
+
+static int up_interrupt(int irq, void *context)
+{
+  struct uart_dev_s *dev = NULL;
+  struct up_dev_s   *priv;
+  volatile uint32    cause;
+
+  if (g_irdaport.irq == irq)
+    {
+      dev = &g_irdaport;
+    }
+  else if (g_modemport.irq == irq)
+    {
+      dev = &g_modemport;
+    }
+  else
+    {
+      PANIC(OSERR_INTERNAL);
+    }
+  priv = (struct up_dev_s*)dev->priv;
+
+  cause = up_inserial(priv, UART_ISR_OFFS) & 0x0000003f;
+
+  if ((cause & 0x0000000c) == 0x0000000c)
+    {
+      uint32 ier_val = 0;
+
+      /* Is this an interrupt from the IrDA UART? */
+
+      if (irq == C5471_IRQ_UART_IRDA)
+         {
+           /* Save the currently enabled IrDA UART interrupts
+            * so that we can restore the IrDA interrupt state
+            * below.
+            */
+
+           ier_val = up_inserial(priv, UART_IER_OFFS);
+
+           /* Then disable all IrDA UART interrupts */
+
+           up_serialout(priv, UART_IER_OFFS, 0);
+         }
+
+      /* Receive characters from the RX fifo */
+
+      uart_recvchars(dev);
+
+      /* read UART_RHR to clear int condition
+       * toss = up_inserialchar(priv,&status);
+       */
+
+      /* Is this an interrupt from the IrDA UART? */
+
+      if (irq == C5471_IRQ_UART_IRDA)
+         {
+           /* Restore the IrDA UART interrupt enables */
+
+           up_serialout(priv, UART_IER_OFFS, ier_val);
+         }
+    }
+  else if ((cause & 0x0000000c) == 0x00000004)
+    {
+      uart_recvchars(dev);
+    }
+
+  if ((cause & 0x00000002) != 0)
+    {
+      uart_xmitchars(dev);
+    }
+
+  return OK;
+}
+
+/************************************************************
+ * Name: up_ioctl
+ *
+ * Description:
+ *   All ioctl calls will be routed through this method
+ *
+ ************************************************************/
+
+static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+  struct inode      *inode = filep->f_inode;
+  struct uart_dev_s *dev   = inode->i_private;
+  struct up_dev_s   *priv  = (struct up_dev_s*)dev->priv;
+  int                ret    = OK;
+
+  switch (cmd)
+    {
+    case TIOCSERGSTRUCT:
+      {
+         struct up_dev_s *user = (struct up_dev_s*)arg;
+         if (!user)
+           {
+             *get_errno_ptr() = EINVAL;
+             ret = ERROR;
+           }
+         else
+           {
+             memcpy(user, dev, sizeof(struct up_dev_s));
+           }
+       }
+       break;
+
+    case TIOCSBRK:  /* BSD compatibility: Turn break on, unconditionally */
+      {
+        irqstate_t flags = irqsave();
+        up_enablebreaks(priv);
+        irqrestore(flags);
+      }
+      break;
+
+    case TIOCCBRK:  /* BSD compatibility: Turn break off, unconditionally */
+      {
+        irqstate_t flags;
+        flags = irqsave();
+        up_disablebreaks(priv);
+        irqrestore(flags);
+      }
+      break;
+
+    default:
+      *get_errno_ptr() = ENOTTY;
+      ret = ERROR;
+      break;
+    }
+
+  return ret;
+}
+
+/************************************************************
+ * Name: up_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one character from
+ * the UART.  Error bits associated with the receipt are provided in the
+ * the return 'status'.
+ *
+ ************************************************************/
+
+static int up_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  uint32 rhr;
+  uint32 lsr;
+
+  /* Construct a 16bit status word that uses the high byte to
+   * hold the status bits associated with framing,parity,break
+   * and a low byte that holds error bits of LSR for
+   * conditions such as overflow, etc.
+   */
+
+  rhr = up_inserial(priv, UART_RHR_OFFS);
+  lsr = up_inserial(priv, UART_LSR_OFFS);
+
+  *status = (unsigned int)((rhr & 0x0000ff00) | (lsr & 0x000000ff));
+
+  return rhr & 0x000000ff;
+}
+
+/************************************************************
+ * Name: up_rxint
+ *
+ * Description:
+ *   Call to enable or disable RX interrupts
+ *
+ ************************************************************/
+
+static void up_rxint(struct uart_dev_s *dev, boolean enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  if (enable)
+    {
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      priv->regs.ier |= UART_IER_RECVINT;
+      up_serialout(priv, UART_IER_OFFS, priv->regs.ier);
+#endif
+    }
+  else
+    {
+      priv->regs.ier &= ~UART_IER_RECVINT;
+      up_serialout(priv, UART_IER_OFFS, priv->regs.ier);
+    }
+}
+
+/************************************************************
+ * Name: up_rxfifonotempty
+ *
+ * Description:
+ *   Return TRUE if the receive fifo is not empty
+ *
+ ************************************************************/
+
+static boolean up_rxfifonotempty(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return up_inserial(priv, UART_LSR_OFFS) & UART_RX_FIFO_NOEMPTY;
+}
+
+/************************************************************
+ * Name: up_send
+ *
+ * Description:
+ *   This method will send one byte on the UART
+ *
+ ************************************************************/
+
+static void up_send(struct uart_dev_s *dev, int ch)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_serialout(priv, UART_THR_OFFS, (ubyte)ch);
+}
+
+/************************************************************
+ * Name: up_txint
+ *
+ * Description:
+ *   Call to enable or disable TX interrupts
+ *
+ ************************************************************/
+
+static void up_txint(struct uart_dev_s *dev, boolean enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  if (enable)
+    {
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      priv->regs.ier |= UART_IER_XMITINT;
+      up_serialout(priv, UART_IER_OFFS, priv->regs.ier);
+#endif
+    }
+  else
+    {
+      priv->regs.ier &= ~UART_IER_XMITINT;
+      up_serialout(priv, UART_IER_OFFS, priv->regs.ier);
+    }
+}
+
+/************************************************************
+ * Name: up_txfifonotfull
+ *
+ * Description:
+ *   Return TRUE if the tranmsit fifo is not full
+ *
+ ************************************************************/
+
+static boolean up_txfifonotfull(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return (up_inserial(priv, UART_SSR_OFFS) & UART_SSR_TXFULL) == 0;
+}
+
+/************************************************************
+ * Name: up_txfifoempty
+ *
+ * Description:
+ *   Return TRUE if the transmit fifo is empty
+ *
+ ************************************************************/
+
+static boolean up_txfifoempty(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return (up_inserial(priv, UART_LSR_OFFS) & UART_LSR_TREF) != 0;
+}
+
+/************************************************************
+ * Public Funtions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Performs the low level UART initialization early in 
+ *   debug so that the serial console will be available
+ *   during bootup.  This must be called before up_serialinit.
+ *
+ ************************************************************/
+
+void up_earlyserialinit(void)
+{
+  up_disableuartint(TTYS0_DEV.priv, NULL);
+  up_disableuartint(TTYS1_DEV.priv, NULL);
+
+  CONSOLE_DEV.isconsole = TRUE;
+  up_setup(&CONSOLE_DEV);
+}
+
+/************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Register serial console and serial ports.  This assumes
+ *   that up_earlyserialinit was called previously.
+ *
+ ************************************************************/
+
+void up_serialinit(void)
+{
+  (void)uart_register("/dev/console", &CONSOLE_DEV);
+  (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+  (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+}
+
+/************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug
+ *   writes
+ *
+ ************************************************************/
+
+int up_putc(int ch)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
+  uint16  ier;
+
+  up_disableuartint(priv, &ier);
+  up_waittxfifonotfull(priv);
+  up_serialout(priv, UART_THR_OFFS, (ubyte)ch);
+
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      up_waittxfifonotfull(priv);
+      up_serialout(priv, UART_THR_OFFS, '\r');
+    }
+
+  up_waittxfifonotfull(priv);
+  up_restoreuartint(priv, ier);
+  return ch;
+}
+

arch/arm/src/c5471/c5471_timerisr.c

@@ -0,0 +1,125 @@
+/************************************************************
+ * c5471/c5471_timerisr.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include "clock_internal.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/* We want the general purpose timer running at the rate
+ * MSEC_PER_TICK. The C5471 clock is 47.5MHz and we're using
+ * a timer PTV value of 3 (3 == divide incoming frequency by
+ * 16) which then yields a 16 bitCLKS_PER_INT value
+ * of 29687.
+ *
+ *   47500000 / 16 = 2968750 clocks/sec
+ *   2968750 / 100 = 29687   clocks/ 100Hz interrupt
+ *
+ */
+
+#define CLKS_PER_INT       29687
+#define CLKS_PER_INT_SHIFT 5
+#define AR                 0x00000010
+#define ST                 0x00000008
+#define PTV                0x00000003
+
+/************************************************************
+ * Private Types
+ ************************************************************/
+
+/************************************************************
+ * Private Function Prototypes
+ ************************************************************/
+
+/************************************************************
+ * Global Functions
+ ************************************************************/
+
+/************************************************************
+ * Function:  up_timerisr
+ *
+ * Description:
+ *   The timer ISR will perform a variety of services for
+ *   various portions of the systems.
+ *
+ ************************************************************/
+
+int up_timerisr(int irq, uint32 *regs)
+{
+   /* Process timer interrupt */
+
+   sched_process_timer();
+   return 0;
+}
+
+/************************************************************
+ * Function:  up_timerinit
+ *
+ * Description:
+ *   This function is called during start-up to initialize
+ *   the timer interrupt.
+ *
+ ************************************************************/
+
+void up_timerinit(void)
+{
+  uint32 val;
+
+  up_disable_irq(C5471_IRQ_SYSTIMER);
+
+  /* Start the general purpose timer running in auto-reload mode
+   * so that an interrupt is generated at the rate MSEC_PER_TICK.
+   */
+
+  val = ((CLKS_PER_INT-1) << CLKS_PER_INT_SHIFT) | AR | ST | PTV;
+  putreg32(val, C5471_TIMER2_CTRL);
+
+  /* Attach and enable the timer interrupt */
+
+  irq_attach(C5471_IRQ_SYSTIMER, (xcpt_t)up_timerisr);
+  up_enable_irq(C5471_IRQ_SYSTIMER);
+}
+

arch/arm/src/c5471/c5471_vectors.S

@@ -0,0 +1,449 @@
+/********************************************************************
+ * c5471/c5471_vectors.S
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************/
+
+/********************************************************************
+ * Included Files
+ ********************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+#include "up_arch.h"
+
+/********************************************************************
+ * Definitions
+ ********************************************************************/
+
+/********************************************************************
+ * Global Data
+ ********************************************************************/
+
+	.data
+g_irqtmp:
+	.word	0		/* Saved lr */
+	.word	0		/* Saved spsr */
+g_undeftmp:
+	.word	0		/* Saved lr */
+	.word	0		/* Saved spsr */
+g_aborttmp:
+	.word	0		/* Saved lr */
+	.word	0		/* Saved spsr */
+
+/********************************************************************
+ * Assembly Macros
+ ********************************************************************/
+
+/********************************************************************
+ * Private Functions
+ ********************************************************************/
+
+	.text
+
+/********************************************************************
+ * Public Functions
+ ********************************************************************/
+
+	.text
+
+/********************************************************************
+ * Name: up_vectorirq
+ *
+ * Description:
+ *   Interrupt excetpion. Entered in IRQ mode with spsr = SVC
+ *   CPSR, lr = SVC PC
+ ********************************************************************/
+
+	.globl	up_vectorirq
+	.type	up_vectorirq, %function
+up_vectorirq:
+	/* On entry, we are in IRQ mode.  We are free to use
+	 * the IRQ mode r13 and r14.
+         *
+	 */
+
+	ldr	r13, .Lirqtmp
+	sub	lr, lr, #4
+	str	lr, [r13]			@ save lr_IRQ
+	mrs	lr, spsr
+	str	lr, [r13, #4]			@ save spsr_IRQ
+
+	/* Then switch back to SVC mode */
+
+	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
+	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
+	msr	cpsr_c, lr		/* Switch to SVC mode */
+
+	/* Create a context structure.  First set aside a stack frame
+	 * and store r0-r12 into the frame.
+	 */
+
+	sub	sp, sp, #XCPTCONTEXT_SIZE
+	stmia	sp, {r0-r12}		/* Save the SVC mode regs */
+
+	/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
+
+	add	r1, sp, #XCPTCONTEXT_SIZE
+	mov	r2, r14
+
+	/* Get the values for r15(pc) and CPSR in r3 and r4 */
+
+	ldr	r0, .Lirqtmp		/* Points to temp storage */
+	ldmia	r0, {r3, r4}		/* Recover r1=lr_IRQ, r2=spsr_IRQ */
+
+	add	r0, sp, #(4*REG_SP)	/* Offset to pc, cpsr storage */
+	stmia	r0, {r1-r4}
+
+	/* Now decode the interrupt */
+
+#if 0
+	ldr	lr, =SRC_IRQ_BIN_REG	/* Fetch encoded IRQ */
+	ldr	r0, [lr]
+	and	r0, r0, #0x0f		/* Valid range is 0..15 */
+
+	/* Problems here... cannot read SRC_IRQ_BIN_REQ (and/or
+	 * SRC_IRQ_REQ because this will clear edge triggered
+	 * interrupts.  Plus, no way to validate spurious
+	 * interrupt.
+	 */
+#else
+	ldr	r6, =SRC_IRQ_REG
+	ldr     r6, [r6]		/* Get source IRQ reg */
+	mov     r0, #0			/* Assume IRQ0_IRQ set */
+.Lmorebits:
+	tst     r6, #1			/* Is IRQ set? */
+	bne     .Lhaveirq		/* Yes... we have the IRQ */
+	add     r0, r0, #1		/* Setup next IRQ */
+	mov     r6, r6, lsr #1		/* Shift right one */
+	cmp     r0, #16			/* Only 16 valid bits */
+	bcc     .Lmorebits		/* Keep until we have looked
+					 * at all bits */
+	b	.Lnoirqset		/* If we get here, there is
+					 * no pending interrupt */
+.Lhaveirq:
+#endif
+	/* Then call the IRQ handler with interrupt disabled. */
+
+	mov	fp, #0			/* Init frame pointer */
+	mov	r1, sp			/* Get r1=xcp */
+	bl	up_doirq		/* Call the handler */
+
+	/* Restore the CPSR, SVC modr registers and return */
+.Lnoirqset:
+	ldr	r0, [sp, #(4*REG_CPSR)]	/* Setup the SVC mode SPSR */
+	msr	spsr, r0
+	ldmia	sp, {r0-r15}^		/* Return */
+
+.Lirqtmp:
+	.word	g_irqtmp
+
+	.align	5
+
+/********************************************************************
+ * Function: up_vectorswi
+ * 
+ * Description:
+ *   SWI interrupt. We enter the SWI in SVC mode
+ ********************************************************************/
+
+	.globl	up_vectorswi
+	.type	up_vectorswi, %function
+up_vectorswi:
+
+	/* The c547x rrload bootloader intemediates all
+	 * interrupts.  For the* case of the SWI, it mucked
+	 * with the stack to create some temporary registers.
+	 * We'll have to recover from this mucking here.
+	 */
+
+	ldr	r14, [sp,#-0x4]		/* rrload workaround */
+
+	/* Create a context structure.  First set aside a stack frame
+	 * and store r0-r12 into the frame.
+	 */
+
+	sub	sp, sp, #XCPTCONTEXT_SIZE
+	stmia	sp, {r0-r12}		/* Save the SVC mode regs */
+
+	/* Get the correct values of r13(sp), r14(lr), r15(pc)
+	 * and CPSR in r1-r4 */
+
+	add	r1, sp, #XCPTCONTEXT_SIZE
+	mov	r2, r14			/* R14 is altered on return from SWI */
+	mov	r3, r14			/* Save r14 as the PC as well */
+	mrs	r4, spsr		/* Get the saved CPSR */
+
+	add	r0, sp, #(4*REG_SP)	/* Offset to pc, cpsr storage */
+	stmia	r0, {r1-r4}
+
+	/* Then call the SWI handler with interrupt disabled.
+	 * void up_syscall(struct xcptcontext *xcp)
+	 */
+
+	mov	fp, #0			/* Init frame pointer */
+	mov	r0, sp			/* Get r0=xcp */
+	bl	up_syscall		/* Call the handler */
+
+	/* Restore the CPSR, SVC modr registers and return */
+
+	ldr	r0, [sp, #(4*REG_CPSR)]	/* Setup the SVC mode SPSR */
+	msr	spsr, r0
+	ldmia	sp, {r0-r15}^		/* Return */
+
+	.align	5
+
+/********************************************************************
+ * Name: up_vectordata
+ *
+ * Description:
+ *   Data abort Exception dispatcher. Give control to data
+ *   abort handler.  This function is entered in ABORT mode
+ *   with spsr = SVC CPSR, lr = SVC PC
+ *
+ ********************************************************************/
+	
+	.globl	up_vectordata
+	.type	up_vectordata, %function
+up_vectordata:
+	/* On entry we are free to use the ABORT mode registers
+	 * r13 and r14
+	 */
+
+	ldr	r13, .Ldaborttmp	/* Points to temp storage */
+	sub	lr, lr, #8		/* Fixup return */
+	str	lr, [r13]		/* Save in temp storage */
+	mrs	lr, spsr		/* Get SPSR */
+	str	lr, [r13, #4]		/* Save in temp storage */
+
+	/* Then switch back to SVC mode */
+
+	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
+	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
+	msr	cpsr_c, lr		/* Switch to SVC mode */
+
+	/* Create a context structure.  First set aside a stack frame
+	 * and store r0-r12 into the frame.
+	 */
+
+	sub	sp, sp, #XCPTCONTEXT_SIZE
+	stmia	sp, {r0-r12}		/* Save the SVC mode regs */
+
+	/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
+
+	add	r1, sp, #XCPTCONTEXT_SIZE
+	mov	r2, r14
+
+	/* Get the values for r15(pc) and CPSR in r3 and r4 */
+
+	ldr	r0, .Ldaborttmp		/* Points to temp storage */
+	ldmia	r0, {r3, r4}		/* Recover r1=lr_IRQ, r2=spsr_IRQ */
+
+	add	r0, sp, #(4*REG_SP)	/* Offset to pc, cpsr storage */
+	stmia	r0, {r1-r4}
+
+	/* Then call the data abort handler with interrupt disabled.
+	 * void up_dataabort(struct xcptcontext *xcp)
+	 */
+
+	mov	fp, #0			/* Init frame pointer */
+	mov	r0, sp			/* Get r0=xcp */
+	bl	up_dataabort		/* Call the handler */
+
+	/* Restore the CPSR, SVC modr registers and return */
+
+	ldr	r0, [sp, #(4*REG_CPSR)]	/* Setup the SVC mode SPSR */
+	msr	spsr_cxsf, r0
+	ldmia	sp, {r0-r15}^		/* Return */
+
+.Ldaborttmp:
+	.word	g_aborttmp
+
+	.align	5
+
+/********************************************************************
+ * Name: up_vectorprefetch
+ *
+ * Description:
+ *    Prefetch abort exception.  Entered in ABT mode with
+ *    spsr = SVC CPSR, lr = SVC PC
+ ********************************************************************/
+	
+	.globl	up_vectorprefetch
+	.type	up_vectorprefetch, %function
+up_vectorprefetch:
+	/* On entry we are free to use the ABORT mode registers
+	 * r13 and r14
+	 */
+
+	ldr	r13, .Lpaborttmp	/* Points to temp storage */
+	sub	lr, lr, #4		/* Fixup return */
+	str	lr, [r13]		/* Save in temp storage */
+	mrs	lr, spsr		/* Get SPSR */
+	str	lr, [r13, #4]		/* Save in temp storage */
+
+	/* Then switch back to SVC mode */
+
+	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
+	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
+	msr	cpsr_c, lr		/* Switch to SVC mode */
+
+	/* Create a context structure.  First set aside a stack frame
+	 * and store r0-r12 into the frame.
+	 */
+
+	sub	sp, sp, #XCPTCONTEXT_SIZE
+	stmia	sp, {r0-r12}		/* Save the SVC mode regs */
+
+	/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
+
+	add	r1, sp, #XCPTCONTEXT_SIZE
+	mov	r2, r14
+
+	/* Get the values for r15(pc) and CPSR in r3 and r4 */
+
+	ldr	r0, .Lpaborttmp		/* Points to temp storage */
+	ldmia	r0, {r3, r4}		/* Recover r1=lr_IRQ, r2=spsr_IRQ */
+
+	add	r0, sp, #(4*REG_SP)	/* Offset to pc, cpsr storage */
+	stmia	r0, {r1-r4}
+
+	/* Then call the prefetch abort handler with interrupt disabled.
+	 * void up_prefetchabort(struct xcptcontext *xcp)
+	 */
+
+	mov	fp, #0			/* Init frame pointer */
+	mov	r0, sp			/* Get r0=xcp */
+	bl	up_prefetchabort	/* Call the handler */
+
+	/* Restore the CPSR, SVC modr registers and return */
+
+	ldr	r0, [sp, #(4*REG_CPSR)]	/* Setup the SVC mode SPSR */
+	msr	spsr_cxsf, r0
+	ldmia	sp, {r0-r15}^		/* Return */
+
+.Lpaborttmp:
+	.word	g_aborttmp
+
+	.align	5
+
+/********************************************************************
+ * Name: up_vectorundefinsn
+ *
+ * Description:
+ *   Undefined instruction entry exception.  Entered in
+ *   UND mode, spsr = SVC  CPSR, lr = SVC PC
+ *
+ ********************************************************************/
+	
+	.globl	up_vectorundefinsn
+	.type	up_vectorundefinsn, %function
+up_vectorundefinsn:
+	/* On entry we are free to use the UND mode registers
+	 * r13 and r14
+	 */
+
+	ldr	r13, .Lundeftmp		/* Points to temp storage */
+	str	lr, [r13]		/* Save in temp storage */
+	mrs	lr, spsr		/* Get SPSR */
+	str	lr, [r13, #4]		/* Save in temp storage */
+
+	/* Then switch back to SVC mode */
+
+	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
+	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
+	msr	cpsr_c, lr		/* Switch to SVC mode */
+
+	/* Create a context structure.  First set aside a stack frame
+	 * and store r0-r12 into the frame.
+	 */
+
+	sub	sp, sp, #XCPTCONTEXT_SIZE
+	stmia	sp, {r0-r12}		/* Save the SVC mode regs */
+
+	/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
+
+	add	r1, sp, #XCPTCONTEXT_SIZE
+	mov	r2, r14
+
+	/* Get the values for r15(pc) and CPSR in r3 and r4 */
+
+	ldr	r0, .Lundeftmp		/* Points to temp storage */
+	ldmia	r0, {r3, r4}		/* Recover r1=lr_IRQ, r2=spsr_IRQ */
+
+	add	r0, sp, #(4*REG_SP)	/* Offset to pc, cpsr storage */
+	stmia	r0, {r1-r4}
+
+	/* Then call the undef insn handler with interrupt disabled.
+	 * void up_undefinedinsn(struct xcptcontext *xcp)
+	 */
+
+	mov	fp, #0			/* Init frame pointer */
+	mov	r0, sp			/* Get r0=xcp */
+	bl	up_undefinedinsn	/* Call the handler */
+
+	/* Restore the CPSR, SVC modr registers and return */
+
+	ldr	r0, [sp, #(4*REG_CPSR)]	/* Setup the SVC mode SPSR */
+	msr	spsr_cxsf, r0
+	ldmia	sp, {r0-r15}^		/* Return */
+
+.Lundeftmp:
+	.word	g_undeftmp
+
+	.align	5
+
+/********************************************************************
+ * Name: up_vectorfiq
+ *
+ * Description:
+ *   Shouldn't happen
+ ********************************************************************/
+
+	.globl	up_vectorfiq
+	.type	up_vectorfiq, %function
+up_vectorfiq:
+	subs	pc, lr, #4
+
+/********************************************************************
+ *  Name: up_vectoraddrexcption
+ *
+ * Description:
+ *   Shouldn't happen
+ *
+ ********************************************************************/
+
+	.globl	up_vectoraddrexcptn
+	.type	up_vectoraddrexcptn, %function
+up_vectoraddrexcptn:
+	b	up_vectoraddrexcptn
+	.end

arch/arm/src/c5471/c5471_watchdog.c

@@ -0,0 +1,392 @@
+/**************************************************************************
+ * c5471/c5471_watchdog.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ **************************************************************************/
+
+/**************************************************************************
+ * Included Files
+ **************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdio.h>
+#include <debug.h>
+#include <errno.h>
+#include <nuttx/fs.h>
+#include <nuttx/irq.h>
+#include <arch/watchdog.h>
+#include "up_arch.h"
+
+/**************************************************************************
+ * Definitions
+ **************************************************************************/
+
+#undef CONFIG_SOFTWARE_TEST
+#undef CONFIG_SOFTWARE_REBOOT
+#undef CONFIG_WATCHDOG_STRICT
+
+#define MAX_WDT_USEC           353200
+#define MAX_PRESCALER          256
+#define C5471_TIMER_STOP       0
+
+#define C5471_TIMER_PRESCALER  0x07          /* Bits 0-2: Prescale value */
+#define C5471_TIMER_STARTBIT   (1 << 3)      /* Bit 3: Start timer bit */
+#define C5471_TIMER_AUTORELOAD (1 << 4)      /* Bit 4: Auto-reload timer */
+#define C5471_TIMER_LOADTIM    (0xffff << 5) /* Bits 20-5: Load timer value */
+#define C5471_TIMER_MODE       (1 << 21)     /* Bit 21: Timer mode */
+#define C5471_DISABLE_VALUE1   (0xf5 << 22)  /* Bits 29-22: WD disable */
+#define C5471_DISABLE_VALUE2   (0xa0 << 22)
+
+#define CLOCK_KHZ              47500
+#define CLOCK_MHZx2            95
+
+/* Macros to manage access to to watchdog timer macros */
+
+#define c5471_wdt_cntl  (*(volatile uint32*)C5471_TIMER0_CTRL)
+#define c5471_wdt_count (*(volatile uint32*)C5471_TIMER0_CNT)
+
+/**************************************************************************
+ * Private Types
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Function Prototypes
+ **************************************************************************/
+
+/* Local implementation of timer interface */
+
+static inline unsigned int wdt_prescaletoptv(unsigned int prescale);
+
+static int     wdt_setusec(uint32 usec);
+static int     wdt_interrupt(int irq, void *context);
+
+static int     wdt_open(struct file *filep);
+static int     wdt_close(struct file *filep);
+static ssize_t wdt_read(struct file *filep, char *buffer, size_t buflen);
+static ssize_t wdt_write(struct file *filep, const char *buffer, size_t buflen);
+static int     wdt_ioctl(struct file *filep, int cmd, uint32 arg);
+
+/**************************************************************************
+ * Private Data
+ **************************************************************************/
+
+static boolean g_wdtopen;
+
+struct file_operations g_wdtops =
+{
+  .open  = wdt_open,
+  .close = wdt_close,
+  .read  = wdt_read,
+  .write = wdt_write,
+  .ioctl = wdt_ioctl,
+};
+
+/**************************************************************************
+ * Private Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Name: wdt_prescaletoptv
+ **************************************************************************/
+
+static inline unsigned int wdt_prescaletoptv(unsigned int prescale)
+{
+  unsigned int ptv = 0;
+
+  if (prescale > 255)
+    {
+      ptv = 7;
+    }
+  else
+    {
+      unsigned int value = prescale >> 1;
+
+      /* 0: 0-2
+       * 1: 3-4
+       * 2: 5-8
+       * 3: 9-16
+       * 4: 17-32
+       * 5: 33-64
+       * 6: 65-128
+       * 7: 129-
+       */
+
+      while (value > 1)
+        {
+          value >>= 1;
+          ptv++;
+        }
+    }
+
+  dbg("prescale=%d -> ptv=%d\n", prescale, ptv);
+  return ptv;
+}
+
+/**************************************************************************
+ * Name: wdt_setusec
+ **************************************************************************/
+
+static int wdt_setusec(uint32 usec)
+{
+  /* prescaler: clock / prescaler = #clock ticks per counter in ptv
+   * divisor:   #counts until the interrupt comes.
+   */
+
+  uint32 prescaler = MAX_PRESCALER;
+  uint32 divisor   = 1;
+  uint32 mode;
+
+  dbg("usec=%d\n", usec);
+
+  /* Calculate a value of prescaler and divisor that will be able
+   * to count to the usec.  It may not be exact or the best
+   * possible set, but it's a quick and simple algorithm.
+   *
+   *    divisor max = 0x10000
+   *    prescaler max = MAX_PRESCALER
+   */
+
+  do
+    {
+      divisor = (CLOCK_MHZx2 * usec) / (prescaler * 2);
+      dbg("divisor=0x%x prescaler=0x%x\n", divisor, prescaler);
+
+      if (divisor >= 0x10000)
+        {
+          if (prescaler == MAX_PRESCALER)
+            { 
+              /* This is the max possible ~2.5 seconds. */
+
+              dbg("prescaler=0x%x too big!\n", prescaler);
+              return ERROR;
+            }
+
+          prescaler <<= 1;
+          if (prescaler > MAX_PRESCALER)
+            {
+              prescaler = MAX_PRESCALER;
+            }
+        }
+    }
+  while (divisor >= 0x10000);
+
+  dbg("prescaler=0x%x divisor=0x%x\n", prescaler, divisor);
+
+  mode  = wdt_prescaletoptv(prescaler);
+  mode &= ~C5471_TIMER_AUTORELOAD; /* One shot mode. */
+  mode |= divisor << 5;
+  dbg("mode=0x%x\n", mode);
+
+  c5471_wdt_cntl = mode;
+
+  /* Now start the watchdog */
+
+  c5471_wdt_cntl |= C5471_TIMER_STARTBIT;
+  dbg("cntl_timer=0x%x\n", c5471_wdt_cntl);
+
+  return 0;
+}
+
+/**************************************************************************
+ * Private Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Name: wdt_interrupt
+ **************************************************************************/
+
+static int wdt_interrupt(int irq, void *context)
+{
+  dbg("expired\n");
+
+#if defined(CONFIG_SOFTWARE_REBOOT)
+#  if defined(CONFIG_SOFTWARE_TEST)
+  dbg("  Test only\n");
+#  else
+  dbg("  Re-booting\n");
+#    warning "Add logic to reset CPU here"
+#  endif
+#else
+  dbg("  No reboot\n");
+#endif
+  return OK;
+}
+
+/**************************************************************************
+ * Name: wdt_read
+ **************************************************************************/
+
+static ssize_t wdt_read(struct file *filep, char *buffer, size_t buflen)
+{
+  /* We are going to return "NNNNNNNN NNNNNNNN."  The followig logic will
+   * not work if the user provides a buffer smaller than 18 bytes.
+   */
+
+  dbg("buflen=%d\n", buflen);
+  if (buflen >= 18)
+    {
+      sprintf(buffer, "#08x %08x\n", c5471_wdt_cntl, c5471_wdt_count);
+      return 18;
+    }
+  return 0;
+}
+
+/**************************************************************************
+ * Name: wdt_write
+ **************************************************************************/
+
+static ssize_t wdt_write(struct file *filep, const char *buffer, size_t buflen)
+{
+  dbg("buflen=%d\n", buflen);
+  if (buflen)
+    {
+      /* Reset the timer to the maximum delay */
+
+      wdt_setusec(MAX_WDT_USEC);
+      return 1;
+    }
+
+  return 0;
+}
+
+/**************************************************************************
+ * Name: wdt_ioctl
+ **************************************************************************/
+
+static int wdt_ioctl(struct file *filep, int cmd, uint32 arg)
+{
+  dbg("ioctl Call: cmd=0x%x arg=0x%x", cmd, arg);
+
+  /* Process the the IOCTL command (see arch/watchdog.h) */
+
+  switch(cmd)
+    {
+    case WDIOC_KEEPALIVE:
+      wdt_setusec(MAX_WDT_USEC);
+      break;
+
+    default:
+      *get_errno_ptr() = ENOTTY;
+      return ERROR;
+    }
+
+  return OK;
+}
+
+/**************************************************************************
+ * Name: wdt_open
+ **************************************************************************/
+
+static int wdt_open(struct file *filep)
+{
+  dbg("");
+
+  if (g_wdtopen)
+    {
+      *get_errno_ptr() = EBUSY;
+    }
+
+  /* This will automatically load the timer with its max
+   * count and start it running.
+   */
+
+  c5471_wdt_cntl = C5471_DISABLE_VALUE1;
+  c5471_wdt_cntl = C5471_DISABLE_VALUE2;
+
+  g_wdtopen = TRUE;
+  return OK;
+}
+
+/**************************************************************************
+ * Name: wdt_close
+ **************************************************************************/
+
+static int wdt_close(struct file *filep)
+{
+  dbg("");
+
+  /* The task controlling the watchdog has terminated.  Take the timer
+   *  the
+   * watchdog in interrupt mode -- we are going to reset unless the
+   * reopened again soon.
+   */
+
+#ifndef CONFIG_WATCHDOG_STRICT
+  c5471_wdt_cntl = C5471_TIMER_MODE;
+#endif
+
+  g_wdtopen = FALSE;
+  return 0;
+}
+
+/**************************************************************************
+ * Public Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Name: up_wdtinit
+ **************************************************************************/
+
+int up_wdtinit(void)
+{
+  int ret;
+
+  dbg("C547x Watchdog Driver\n");
+
+  /* Register as /dev/wdt */
+
+  ret = register_driver("/dev/wdt", &g_wdtops, 0666, NULL);
+  if (ret)
+    {
+      return ERROR;
+    }
+
+  /* Register for an interrupt level callback through wdt_interrupt */
+
+  dbg("Attach to IRQ=%d\n", C5471_IRQ_WATCHDOG);
+
+  /* Make sure that the timer is stopped */
+
+  c5471_wdt_cntl = C5471_TIMER_STOP;
+
+  /* Request the interrupt. */
+
+  ret = irq_attach(C5471_IRQ_WATCHDOG, wdt_interrupt);
+  if (ret)
+    {
+      unregister_driver("/dev/wdt");
+      return ERROR;
+    }
+
+  return OK;
+}

arch/arm/src/c5471/chip.h

@@ -0,0 +1,319 @@
+/************************************************************
+ * c5471/chip.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+#ifndef __C5471_CHIP_H
+#define __C5471_CHIP_H
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/* UARTs ****************************************************/
+
+#define UART_IRDA_BASE         0xffff0800
+#define UART_MODEM_BASE        0xffff1000
+#define UARTn_IO_RANGE         0x00000800
+
+/* Common UART Registers.  Expressed as offsets from the BASE address */
+
+#define UART_RHR_OFFS          0x00000000 /* Rcv Holding Register */
+#define UART_THR_OFFS          0x00000004 /* Xmit Holding Register */
+#define UART_FCR_OFFS          0x00000008 /* FIFO Control Register */
+#define UART_RFCR_OFFS         0x00000008 /* Rcv FIFO Control Register */
+#define UART_TFCR_OFFS         0x00000008 /* Xmit FIFO Control Register */
+#define UART_SCR_OFFS          0x0000000c /* Status Control Register */
+#define UART_LCR_OFFS          0x00000010 /* Line Control Register */
+#define UART_LSR_OFFS          0x00000014 /* Line Status Register */
+#define UART_SSR_OFFS          0x00000018 /* Supplementary Status Register */
+#define UART_MCR_OFFS          0x0000001c /* Modem Control Register */
+#define UART_MSR_OFFS          0x00000020 /* Modem Status Register */
+#define UART_IER_OFFS          0x00000024 /* Interrupt Enable Register */
+#define UART_ISR_OFFS          0x00000028 /* Interrupt Status Register */
+#define UART_EFR_OFFS          0x0000002c /* Enhanced Feature Register */
+#define UART_XON1_OFFS         0x00000030 /* XON1 Character Register */
+#define UART_XON2_OFFS         0x00000034 /* XON2 Character Register */
+#define UART_XOFF1_OFFS        0x00000038 /* XOFF1 Character Register */
+#define UART_XOFF2_OFFS        0x0000003c /* XOFF2 Character Register */
+#define UART_SPR_OFFS          0x00000040 /* Scratch-pad Register */
+#define UART_DIV_115K_OFFS     0x00000044 /* Divisor for baud generation */
+#define UART_DIV_BIT_RATE_OFFS 0x00000048 /* For baud rate generation */
+#define UART_TCR_OFFS          0x0000004c /* Transmission Control Register */
+#define UART_TLR_OFFS          0x00000050 /* Trigger Level Register */
+#define UART_MDR_OFFS          0x00000054 /* Mode Definition Register */
+
+/* Registers available only for the IrDA UART (absolute address). */
+
+#define UART_IRDA_MDR1         0xffff0854 /* Mode Definition Register 1 */
+#define UART_IRDA_MDR2         0xffff0858 /* Mode Definition Register 2 */
+#define UART_IRDA_TXFLL        0xffff085c /* LS Xmit Frame Length Register */
+#define UART_IRDA_TXFLH        0xffff0860 /* MS Xmit Frame Length Register */
+#define UART_IRDA_RXFLL        0xffff0864 /* LS Rcvd Frame Length Register */
+#define UART_IRDA_RXFLH        0xffff0868 /* MS Rcvd Frame Length Register */
+#define UART_IRDA_SFLSR        0xffff086c /* Status FIFO Line Status Reg */
+#define UART_IRDA_SFREGL       0xffff0870 /* LS Status FIFO Register */
+#define UART_IRDA_SFREGH       0xffff0874 /* MS Status FIFO Register */
+#define UART_IRDA_BLR          0xffff0878 /* Begin of File Length Register */
+#define UART_IRDA_PULSE_WIDTH  0xffff087c /* Pulse Width Register */
+#define UART_IRDA_ACREG        0xffff0880 /* Auxiliary Control Register */
+#define UART_IRDA_PULSE_START  0xffff0884 /* Start time of pulse */
+#define UART_IRDA_RX_W_PTR     0xffff0888 /* RX FIFO write pointer */
+#define UART_IRDA_RX_R_PTR     0xffff088c /* RX FIFO read pointer */
+#define UART_IRDA_TX_W_PTR     0xffff0890 /* TX FIFO write pointer */
+#define UART_IRDA_TX_R_PTR     0xffff0894 /* TX FIFO read pointer */
+#define UART_IRDA_STATUS_W_PTR 0xffff0898 /* Write pointer of status FIFO */
+#define UART_IRDA_STATUS_R_PTR 0xffff089c /* Read pointer of status FIFO */
+#define UART_IRDA_RESUME       0xffff08a0 /* Resume register */
+#define UART_IRDA_MUX          0xffff08a4 /* Selects UART_IRDA output mux */
+
+/* Registers available for the Modem UART (absolute addresses) */
+
+#define UART_MODEM_MDR         0xffff1054 /* Mode Definition Register */
+#define UART_MODEM_UASR        0xffff1058 /* UART Auto-baud Status Register */
+#define UART_MODEM_RDPTR_URX   0xffff105c /* RX FIFO Read Pointer Register */
+#define UART_MODEM_WRPTR_URX   0xffff1060 /* RX FIFO Write Pointer Register */
+#define UART_MODEM_RDPTR_UTX   0xffff1064 /* TX FIFO Read Pointer Register */
+#define UART_MODEM_WRPTR_UTX   0xffff1068 /* TX FIFO Write Pointer Register */
+
+/* UART Settings ********************************************/
+
+/* Miscellaneous UART settings. */
+
+#define UART_RX_FIFO_NOEMPTY 0x00000001
+#define UART_SSR_TXFULL      0x00000001
+#define UART_LSR_TREF        0x00000020
+
+#define UART_XMIT_FIFO_SIZE      64
+#define UART_IRDA_XMIT_FIFO_SIZE 64
+
+/* UART_LCR Register */
+                                        /* Bits 31-7: Reserved */
+#define UART_LCR_BOC         0x00000040 /* Bit 6: Break Control */
+                                        /* Bit 5: Parity Type 2 */
+#define UART_LCR_PAREVEN     0x00000010 /* Bit 4: Parity Type 1 */
+#define UART_LCR_PARODD      0x00000000
+#define UART_LCR_PAREN       0x00000008 /* Bit 3: Paity Enable */
+#define UART_LCR_PARDIS      0x00000000
+#define UART_LCR_2STOP       0x00000004 /* Bit 2: Number of stop bits */
+#define UART_LCR_1STOP       0x00000000
+#define UART_LCR_5BITS       0x00000000 /* Bits 0-1: Word-length */
+#define UART_LCR_6BITS       0x00000001
+#define UART_LCR_7BITS       0x00000002
+#define UART_LCR_8BITS       0x00000003
+
+#define UART_FCR_FTL         0x00000000
+#define UART_FCR_FIFO_EN     0x00000001
+#define UART_FCR_TX_CLR      0x00000002
+#define UART_FCR_RX_CLR      0x00000004
+
+#define UART_IER_RECVINT     0x00000001
+#define UART_IER_XMITINT     0x00000002
+#define UART_IER_LINESTSINT  0x00000004
+#define UART_IER_MODEMSTSINT 0x00000008 /* IrDA UART only */
+#define UART_IER_XOFFINT     0x00000020
+#define UART_IER_RTSINT      0x00000040 /* IrDA UART only */
+#define UART_IER_CTSINT      0x00000080 /* IrDA UART only */
+#define UART_IER_INTMASK     0x000000ff
+
+#define BAUD_115200          0x00000001
+#define BAUD_57600           0x00000002
+#define BAUD_38400           0x00000003
+#define BAUD_19200           0x00000006
+#define BAUD_9600            0x0000000C
+#define BAUD_4800            0x00000018
+#define BAUD_2400            0x00000030
+#define BAUD_1200            0x00000060
+
+#define MDR_UART_MODE        0x00000000  /* Both IrDA and Modem UARTs */
+#define MDR_SIR_MODE         0x00000001  /* IrDA UART only */
+#define MDR_AUTOBAUDING_MODE 0x00000002  /* Modem UART only */
+#define MDR_RESET_MODE       0x00000007  /* Both IrDA and Modem UARTs */
+
+/* SPI ******************************************************/
+
+#define MAX_SPI 3
+
+#define SPI_REGISTER_BASE    0xffff2000
+
+/* GIO ******************************************************/
+
+#define MAX_GIO (35)
+
+#define GIO_REGISTER_BASE    0xffff2800
+
+#define GPIO_IO              0xffff2800 /* Writeable when I/O is configured
+					 * as an output; reads value on I/O
+					 * pin when I/O is configured as an
+					 * input */
+#define GPIO_CIO             0xffff2804 /* GPIO configuration register */
+#define GPIO_IRQA            0xffff2808 /* In conjunction with GPIO_IRQB
+					 * determines the behavior when GPIO
+					 * pins configured as input IRQ */
+#define GPIO_IRQB            0xffff280c /* Determines the behavior when GPIO
+					 * pins configured as input IRQ */
+#define GPIO_DDIO            0xffff2810 /* Delta Detect Register
+					 * (detects changes in the I/O pins) */
+#define GPIO_EN              0xffff2814 /* Selects register for muxed GPIOs */
+
+#define KGIO_REGISTER_BASE   0xffff2900
+
+#define KBGPIO_IO            0xffff2900 /* Keyboard I/O bits: Writeable
+					 * when KBGPIO is configured as an
+					 * output; reads value on I/O pin
+					 * when KBGPIO is configured as an
+					 * input */
+#define KBGPIO_CIO           0xffff2904 /* KBGPIO configuration register */
+#define KBGPIO_IRQA          0xffff2908 /* In conjunction with KBGPIO_IRQB
+					 * determines the behavior when
+					 * KBGPIO pins configured as input
+					 * IRQ */
+#define KBGPIO_IRQB          0xffff290c /* In conjunction with KBGPIO_IRQA
+					 * determines the behavior when
+					 * KBGPIO pins configured as input
+					 * IRQ */
+#define KBGPIO_DDIO          0xffff2910 /* Delta Detect Register (detects
+					 * changes in the KBGPIO pins) */
+#define KBGPIO_EN            0xffff2914 /* Selects register for muxed
+					 * KBGPIOs */
+
+/* Timers ***************************************************/
+
+#define C5471_TIMER0_CTRL    0xffff2a00
+#define C5471_TIMER0_CNT     0xffff2a04
+#define C5471_TIMER1_CTRL    0xffff2b00
+#define C5471_TIMER1_CNT     0xffff2b04
+#define C5471_TIMER2_CTRL    0xffff2c00
+
+#define C5471_TIMER2_CNT     0xffff2c04
+
+/* Interrupts */
+
+#define HAVE_SRC_IRQ_BIN_REG 0
+
+#define INT_FIRST_IO         0xffff2d00
+#define INT_IO_RANGE         0x5C
+
+#define IT_REG               0xffff2d00
+#define MASK_IT_REG          0xffff2d04
+#define SRC_IRQ_REG          0xffff2d08
+#define SRC_FIQ_REG          0xffff2d0c
+#define SRC_IRQ_BIN_REG      0xffff2d10
+#define INT_CTRL_REG         0xffff2d18
+
+#define ILR_IRQ0_REG         0xffff2d1C /*  0-Timer 0       */
+#define ILR_IRQ1_REG         0xffff2d20 /*  1-Timer 1       */
+#define ILR_IRQ2_REG         0xffff2d24 /*  2-Timer 2       */
+#define ILR_IRQ3_REG         0xffff2d28 /*  3-GPIO0         */
+#define ILR_IRQ4_REG         0xffff2d2c /*  4-Ethernet      */
+#define ILR_IRQ5_REG         0xffff2d30 /*  5-KBGPIO[7:0]   */
+#define ILR_IRQ6_REG         0xffff2d34 /*  6-Uart   serial */
+#define ILR_IRQ7_REG         0xffff2d38 /*  7-Uart   IRDA   */
+#define ILR_IRQ8_REG         0xffff2d3c /*  8-KBGPIO[15:8]  */
+#define ILR_IRQ9_REG         0xffff2d40 /*  9-GPIO3         */
+#define ILR_IRQ10_REG        0xffff2d44 /* 10-GPIO2         */
+#define ILR_IRQ11_REG        0xffff2d48 /* 11-I2C           */
+#define ILR_IRQ12_REG        0xffff2d4c /* 12-GPIO1         */
+#define ILR_IRQ13_REG        0xffff2d50 /* 13-SPI           */
+#define ILR_IRQ14_REG        0xffff2d54 /* 14-GPIO[19:4]    */
+#define ILR_IRQ15_REG        0xffff2d58 /* 15-API           */
+
+/* I2C ******************************************************/
+
+#define MAX_I2C 1
+
+/* API ******************************************************/
+
+#define DSPRAM_BASE          0xffe00000  /* DSPRAM base address */
+#define DSPRAM_END           0xffe03fff
+
+/* This is the API address range in the DSP address space. */
+
+#define DSPMEM_DSP_START     0x2000
+#define DSPMEM_DSP_END       0x3fff
+
+/* This is the API address range in the ARM address space. */
+
+#define DSPMEM_ARM_START     DSPRAM_BASE /* Defined in hardware.h */
+#define DSPMEM_ARM_END       DSPRAM_END
+
+/* DSPMEM_IN_RANGE is a generic macro to test is a value is within
+ * a range of values.
+ */
+
+#define DSPMEM_IN_RANGE(addr, start, end) \
+  ((((__u32)(addr)) >= (start)) && (((__u32)(addr)) <= (end)))
+
+/* DSPMEM_ADDR_ALIGNED verifies that a potential DSP address is
+ * properly word aligned.
+ */
+
+#define DSPMEM_ADDR_ALIGNED(addr, cpu) ((((__u32)(addr)) & 1) == 0)
+
+/* DSPMEM_DSP_ADDR checks if a DSP address lies in within the
+ * DSP's API address range.
+ */
+
+#define DSPMEM_DSP_ADDR(addr, cpu) \
+  DSPMEM_IN_RANGE(addr, DSPMEM_DSP_START, DSPMEM_DSP_END)
+
+/* DSPMEM_ARM_ADDR checks if a ARM address lies in within the
+ * ARM's API address range.
+ */
+
+#define DSPMEM_ARM_ADDR(addr) \
+  DSPMEM_IN_RANGE(addr, DSPMEM_ARM_START, DSPMEM_ARM_END)
+
+/* DSPMEM_DSP_TO_ARM maps a DSP API address into an ARM API address */
+
+#define DSPMEM_DSP_TO_ARM(addr, cpu) \
+  ((((__u32)(addr) - DSPMEM_DSP_START) << 1) + DSPMEM_ARM_START)
+
+/* DSPMEM_ARM_TO_DSP maps an ARM API address into a DSP API address */
+
+#define DSPMEM_ARM_TO_DSP(addr) \
+  ((((__u32)(addr) - DSPMEM_ARM_START) >> 1) + DSPMEM_DSP_START)
+
+/************************************************************
+ * Inline Functions
+ ************************************************************/
+
+/************************************************************
+ * Public Function Prototypes
+ ************************************************************/
+
+#endif  /* __C5471_CHIP_H */

arch/arm/src/common/arm.h

@@ -0,0 +1,254 @@
+/************************************************************************************
+ * common/arm.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARM_H
+#define __ARM_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+# include <sys/types.h>
+#endif
+
+/**************************************************************************
+ * Conditional Compilation
+ **************************************************************************/
+
+#undef CONFIG_ALIGNMENT_TRAP
+#undef CONFIG_DCACHE_WRITETHROUGH
+#undef CONFIG_CACHE_ROUND_ROBIN
+#undef CONFIG_DCACHE_DISABLE
+#undef CONFIG_ICACHE_DISABLE
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* ARM9EJS **************************************************************************/
+
+/* PSR bits */
+
+#define MODE_MASK       0x0000001f
+#define USR26_MODE      0x00000000
+#define FIQ26_MODE      0x00000001
+#define IRQ26_MODE      0x00000002
+#define SVC26_MODE      0x00000003
+#define USR_MODE        0x00000010
+#define FIQ_MODE        0x00000011
+#define IRQ_MODE        0x00000012
+#define SVC_MODE        0x00000013
+#define ABT_MODE        0x00000017
+#define UND_MODE        0x0000001b
+#define MODE32_BIT      0x00000010
+#define SYSTEM_MODE     0x0000001f
+#define PSR_T_BIT       0x00000020
+#define PSR_F_BIT       0x00000040
+#define PSR_I_BIT       0x00000080
+#define PSR_J_BIT       0x01000000
+#define PSR_Q_BIT       0x08000000
+#define PSR_V_BIT       0x10000000
+#define PSR_C_BIT       0x20000000
+#define PSR_Z_BIT       0x40000000
+#define PSR_N_BIT       0x80000000
+
+/* CR1 bits (CP#15 CR1) */
+
+#define CR_M            0x00000001 /* MMU enable                          */
+#define CR_A            0x00000002 /* Alignment abort enable              */
+#define CR_C            0x00000004 /* Dcache enable                       */
+#define CR_W            0x00000008 /* Write buffer enable                 */
+#define CR_P            0x00000010 /* 32-bit exception handler            */
+#define CR_D            0x00000020 /* 32-bit data address range           */
+#define CR_L            0x00000040 /* Implementation defined              */
+#define CR_B            0x00000080 /* Big endian                          */
+#define CR_S            0x00000100 /* System MMU protection               */
+#define CR_R            0x00000200 /* ROM MMU protection                  */
+#define CR_F            0x00000400 /* Implementation defined              */
+#define CR_Z            0x00000800 /* Implementation defined              */
+#define CR_I            0x00001000 /* Icache enable                       */
+#define CR_V            0x00002000 /* Vectors relocated to 0xffff0000     */
+#define CR_RR           0x00004000 /* Round Robin cache replacement       */
+#define CR_L4           0x00008000 /* LDR pc can set T bit                */
+#define CR_DT           0x00010000
+#define CR_IT           0x00040000
+#define CR_ST           0x00080000
+#define CR_FI           0x00200000 /* Fast interrupt (lower latency mode) */
+#define CR_U            0x00400000 /* Unaligned access operation          */
+#define CR_XP           0x00800000 /* Extended page tables                */
+#define CR_VE           0x01000000 /* Vectored interrupts                 */
+
+/* Hardware page table definitions.
+ *
+ * Level 1 Descriptor (PMD)
+ *
+ * Common definitions.
+ */
+
+#define PMD_TYPE_MASK       0x00000003  /* Bits 1:0:   Type of descriptor */
+#define PMD_TYPE_FAULT      0x00000000
+#define PMD_TYPE_COARSE     0x00000001
+#define PMD_TYPE_SECT       0x00000002
+#define PMD_TYPE_FINE       0x00000003
+                                    /* Bits 3:2:   Depends on descriptor */
+#define PMD_BIT4            0x00000010  /* Bit  4:     Must be one */
+#define PMD_DOMAIN_MASK     0x000001e0  /* Bits 8:5:   Domain control bits */
+#define PMD_DOMAIN(x)       ((x) << 5)
+#define PMD_PROTECTION      0x00000200  /* Bit 9:      v5 only */
+                                    /* Bits 31:10: Depend on descriptor */
+
+/* Level 1 Section Descriptor.  Section descriptors allow fast, single
+ * level mapping between 1Mb address regions.
+ */
+                                        /* Bits 1:0:   Type of mapping */
+#define PMD_SECT_BUFFERABLE 0x00000004  /* Bit  2:     1=bufferable */
+#define PMD_SECT_CACHEABLE  0x00000008  /* Bit  3:     1=cacheable */
+                                        /* Bit  4:     Common, must be one */
+                                        /* Bits 8:5:   Common domain control */
+                                        /* Bit  9:     Common protection */
+#define PMD_SECT_AP_MASK    0x00000c00  /* Bits 11:10: Access permission */
+#define PMD_SECT_AP_WRITE   0x00000400
+#define PMD_SECT_AP_READ    0x00000800
+                                        /* Bits 19:20: Should be zero */
+#define PMD_SECT_TEX_MASK   0xfff00000  /* Bits 31:20: v5, Physical page */
+#define PMD_SECT_APX        0x00008000  /* Bit  15:    v6 only */
+#define PMD_SECT_S          0x00010000  /* Bit  16:    v6 only */
+#define PMD_SECT_nG         0x00020000  /* Bit  17:    v6 only */
+
+#define PMD_SECT_UNCACHED   (0)
+#define PMD_SECT_BUFFERED   (PMD_SECT_BUFFERABLE)
+#define PMD_SECT_WT         (PMD_SECT_CACHEABLE)
+#define PMD_SECT_WB         (PMD_SECT_CACHEABLE|PMD_SECT_BUFFERABLE)
+#define PMD_SECT_MINICACHE  (PMD_SECT_TEX(1)|PMD_SECT_CACHEABLE)
+#define PMD_SECT_WBWA       (PMD_SECT_TEX(1)|PMD_SECT_CACHEABLE|PMD_SECT_BUFFERABLE)
+
+/* Level 1 Coarse Table Descriptor.  Coarse Table Descriptors support
+ * two level mapping between 16Kb memory regions.
+ */
+                                        /* Bits 1:0:   Type of mapping */
+                                        /* Bits 3:2:   Should be zero */
+                                        /* Bit  4:     Common, must be one */
+                                        /* Bits 8:5:   Common domain control */
+                                        /* Bits 9:     Should be zero */
+#define PMD_COARSE_TEX_MASK 0xfffffc00  /* Bits 31:10: v5, Physical page */
+
+/* Level 1 Fine Table Descriptor.  Coarse Table Descriptors support
+ * two level mapping between 4Kb memory regions.
+ */
+
+                                        /* Bits 1:0:   Type of mapping */
+                                        /* Bits 3:2:   Should be zero */
+                                        /* Bit  4:     Common, must be one */
+                                        /* Bits 8:5:   Common domain control */
+                                        /* Bits 11:9:  Should be zero */
+#define PMD_FINE_TEX_MASK   0xfffff000  /* Bits 31:12: v5, Physical page */
+
+/* Level 2 Table Descriptor (PTE).  -- All tables */
+
+#define PTE_TYPE_MASK       (3 << 0)    /* Bits: 1:0:  Type of mapping */
+#define PTE_TYPE_FAULT      (0 << 0)    /*   None */
+#define PTE_TYPE_LARGE      (1 << 0)    /*   64Kb of memory */
+#define PTE_TYPE_SMALL      (2 << 0)    /*    4Kb of memory */
+#define PTE_TYPE_TINY       (3 << 0)    /*    1Kb of memory (v5)*/
+#define PTE_BUFFERABLE      (1 << 2)    /* Bit  2:     1=bufferable */
+#define PTE_CACHEABLE       (1 << 3)    /* Bit  3:     1=cacheable */
+                                        /* Bits 31:4:  Depend on type */
+
+/* Large page -- 64Kb */
+                                         /* Bits: 1:0:  Type of mapping */
+                                         /* Bits: 3:2:  Bufferable/cacheable */
+#define PTE_LARGE_AP_MASK    (0xff << 4) /* Bits 11:4   Access permissions */
+#define PTE_LARGE_AP_UNO_SRO (0x00 << 4)
+#define PTE_LARGE_AP_UNO_SRW (0x55 << 4)
+#define PTE_LARGE_AP_URO_SRW (0xaa << 4)
+#define PTE_LARGE_AP_URW_SRW (0xff << 4)
+                                         /* Bits 15:12: Should be zero */
+#define PTE_LARGE_TEX_MASK   0xffff0000  /* Bits 31:16: v5, Physical page */
+
+/* Small page -- 4Kb */
+
+                                         /* Bits: 1:0:  Type of mapping */
+                                         /* Bits: 3:2:  Bufferable/cacheable */
+#define PTE_SMALL_AP_MASK    (0xff << 4) /* Bits: 11:4: Access permissions */
+#define PTE_SMALL_AP_UNO_SRO (0x00 << 4)
+#define PTE_SMALL_AP_UNO_SRW (0x55 << 4)
+#define PTE_SMALL_AP_URO_SRW (0xaa << 4)
+#define PTE_SMALL_AP_URW_SRW (0xff << 4)
+#define PTE_SMALL_TEX_MASK   0xfffff000  /* Bits: 31:12: Physical page */
+
+/* Tiny page -- 1Kb */
+
+                                        /* Bits: 1:0:  Type of mapping */
+                                        /* Bits: 3:2:  Bufferable/cacheable */
+#define PTE_EXT_AP_MASK      (3 << 4)   /* Bits: 5:4:  Access persions */
+#define PTE_EXT_AP_UNO_SRO   (0 << 4)
+#define PTE_EXT_AP_UNO_SRW   (1 << 4)
+#define PTE_EXT_AP_URO_SRW   (2 << 4)
+#define PTE_EXT_AP_URW_SRW   (3 << 4)
+                                        /* Bits: 9:6:  Should be zero */
+#define PTE_TINY_TEX_MASK    0xfffffc00 /* Bits: 31:10: Physical page */
+
+/* Default MMU flags for memory and IO */
+
+#define MMU_MEMFLAGS \
+  (PMD_TYPE_SECT|PMD_SECT_WB|PMD_BIT4|PMD_SECT_AP_WRITE|PMD_SECT_AP_READ)
+
+#define MMU_IOFLAGS \
+  (PMD_TYPE_SECT|PMD_BIT4|PMD_SECT_AP_WRITE|PMD_SECT_AP_READ)
+
+#define MMU_L1_VECTORFLAGS   (PMD_TYPE_COARSE|PMD_BIT4)
+#define MMU_L2_VECTORFLAGS   (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW)
+
+/* Mapped section size */
+
+#define SECTION_SIZE          (1 << 20)   /* 1Mb */
+
+/* We place the page tables 16K below the beginning of .text.  The
+ * following value is assume to be the (virtual) start address of
+ * .text.
+ */
+
+#define PGTABLE_SIZE          0x00004000
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#endif
+
+#endif  /* __ARM_H */

arch/arm/src/common/up_allocateheap.c

@@ -0,0 +1,79 @@
+/************************************************************
+ * common/up_allocateheap.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include "up_arch.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Private Definitions
+ ************************************************************/
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/************************************************************
+ * Private Functions
+ ************************************************************/
+
+/************************************************************
+ * Public Functions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_allocate_heap
+ *
+ * Description:
+ *   The heap may be statically allocated by
+ *   defining CONFIG_HEAP_BASE and CONFIG_HEAP_SIZE.  If these
+ *   are not defined, then this function will be called to
+ *   dynamically set aside the heap region.
+ *
+ ************************************************************/
+
+void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
+{
+  up_ledon(LED_HEAPALLOCATE);
+  *heap_start = (FAR void*)g_heapbase;
+  *heap_size = CONFIG_DRAM_END - g_heapbase;
+}

arch/arm/src/common/up_arch.h

@@ -0,0 +1,92 @@
+/************************************************************************************
+ * common/up_arch.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __UP_ARCH_H
+#define __UP_ARCH_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#ifndef __ASSEMBLY__
+# include <sys/types.h>
+#endif
+
+#include "arm.h"
+#include <arch/board/board.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+# define getreg8(a)           (*(volatile ubyte *)(a))
+# define putreg8(v,a)         (*(volatile ubyte *)(a) = (v))
+# define getreg32(a)          (*(volatile uint32 *)(a))
+# define putreg32(v,a)        (*(volatile uint32 *)(a) = (v))
+
+/* Some compiler options will convert short loads and stores into byte loads
+ * and stores.  We don't want this to happen for IO reads and writes!
+ */
+
+/* # define getreg16(a)       (*(volatile uint16 *)(a)) */
+static inline uint16 getreg16(unsigned int addr)
+{
+  uint16 retval;
+ __asm__ __volatile__("\tldrh %0, [%1]\n\t" : "=r"(retval) : "r"(addr));
+  return retval;
+}
+
+/* define putreg16(v,a)       (*(volatile uint16 *)(a) = (v)) */
+static inline void putreg16(uint16 val, unsigned int addr)
+{
+ __asm__ __volatile__("\tstrh %0, [%1]\n\t": : "r"(val), "r"(addr));
+}
+
+/* Most DM320 registers are 16-bits wide */
+
+#define getreg(a)   getreg16(1)
+#define putreg(v,a) putreg16(v,a)
+
+#endif
+
+#endif  /* __UP_ARCH_H */

arch/arm/src/common/up_assert.c

@@ -0,0 +1,224 @@
+/************************************************************
+ * common/up_assert.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdlib.h>
+#include <assert.h>
+#include <debug.h>
+#include <nuttx/irq.h>
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/* Output debug info if stack dump is selected -- even if 
+ * debug is not selected.
+ */
+
+#ifdef CONFIG_ARCH_STACKDUMP
+# undef  lldbg
+# define lldbg lib_lowprintf
+#endif
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/************************************************************
+ * Private Functions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_getsp
+ ************************************************************/
+
+/* I don't know if the builtin to get SP is enabled */
+
+static inline uint32 up_getsp(void)
+{
+  uint32 sp;
+  __asm__
+  (
+    "\tmov %0, sp\n\t"
+    : "=r"(sp)
+  );
+  return sp;
+}
+
+/************************************************************
+ * Name: up_stackdump
+ ************************************************************/
+
+#ifdef CONFIG_ARCH_STACKDUMP
+static void up_stackdump(void)
+{
+  _TCB *rtcb        = (_TCB*)g_readytorun.head;
+  uint32 sp         = up_getsp();
+  uint32 stack_base;
+  uint32 stack_size;
+
+  if (rtcb->pid == 0)
+    {
+      stack_base = g_heapbase - 4;
+      stack_size = CONFIG_PROC_STACK_SIZE;
+    }
+  else
+    {
+      stack_base = (uint32)rtcb->adj_stack_ptr;
+      stack_size = (uint32)rtcb->adj_stack_size;
+    }
+
+  lldbg("stack_base: %08x\n", stack_base);
+  lldbg("stack_size: %08x\n", stack_size);
+  lldbg("sp:         %08x\n", sp);
+
+  if (sp >= stack_base || sp < stack_base - stack_size)
+    {
+      lldbg("ERROR: Stack pointer is not within allocated stack\n");
+      return;
+    }
+  else
+    {
+      uint32 stack = sp & ~0x1f;
+
+      for (stack = sp & ~0x1f; stack < stack_base; stack += 32)
+        {
+          uint32 *ptr = (uint32*)stack;
+          lldbg("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+                 stack, ptr[0], ptr[1], ptr[2], ptr[3],
+                 ptr[4], ptr[5], ptr[6], ptr[7]);
+        }
+    }
+
+  if (current_regs)
+    {
+      int regs;
+
+      for (regs = REG_R0; regs <= REG_R15; regs += 8)
+        {
+          uint32 *ptr = (uint32*)&current_regs[regs];
+          lldbg("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+                 regs, ptr[0], ptr[1], ptr[2], ptr[3],
+                 ptr[4], ptr[5], ptr[6], ptr[7]);
+        }
+      lldbg("CPSR: %08x\n", current_regs[REG_CPSR]);
+    }
+}
+#else
+# define up_stackdump()
+#endif
+
+/************************************************************
+ * Name: _up_assert
+ ************************************************************/
+
+static void _up_assert(int errorcode) /* __attribute__ ((noreturn)) */
+{
+  /* Are we in an interrupt handler or the idle task? */
+
+  if (current_regs || ((_TCB*)g_readytorun.head)->pid == 0)
+    {
+       (void)irqsave();
+        for(;;)
+          {
+#ifdef CONFIG_ARCH_LEDS
+            up_ledon(LED_PANIC);
+            up_delay(250);
+            up_ledoff(LED_PANIC);
+            up_delay(250);
+#endif
+          }
+    }
+  else
+    {
+      exit(errorcode);
+    }
+}
+
+/************************************************************
+ * Public Funtions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_assert
+ ************************************************************/
+
+void up_assert(const ubyte *filename, int lineno)
+{
+#if CONFIG_TASK_NAME_SIZE > 0
+  _TCB *rtcb = (_TCB*)g_readytorun.head;
+#endif
+
+  up_ledon(LED_ASSERTION);
+#if CONFIG_TASK_NAME_SIZE > 0
+  lldbg("Assertion failed at file:%s line: %d task: %s\n",
+        filename, lineno, rtcb->name);
+#else
+  lldbg("Assertion failed at file:%s line: %d\n",
+        filename, lineno);
+#endif
+  up_stackdump();
+  _up_assert(EXIT_FAILURE);
+}
+
+/************************************************************
+ * Name: up_assert_code
+ ************************************************************/
+
+void up_assert_code(const ubyte *filename, int lineno, int errorcode)
+{
+#if CONFIG_TASK_NAME_SIZE > 0
+  _TCB *rtcb = (_TCB*)g_readytorun.head;
+#endif
+
+  up_ledon(LED_ASSERTION);
+#if CONFIG_TASK_NAME_SIZE > 0
+  lldbg("Assertion failed at file:%s line: %d task: %s error code: %d\n",
+        filename, lineno, rtcb->name, errorcode);
+#else
+  lldbg("Assertion failed at file:%s line: %d error code: %d\n",
+        filename, lineno, errorcode);
+#endif
+  up_stackdump();
+  _up_assert(errorcode);
+}

arch/arm/src/common/up_blocktask.c

@@ -0,0 +1,168 @@
+/************************************************************
+ * common/up_blocktask.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <sched.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include "os_internal.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Private Definitions
+ ************************************************************/
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/************************************************************
+ * Private Funtions
+ ************************************************************/
+
+/************************************************************
+ * Public Funtions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_block_task
+ *
+ * Description:
+ *   The currently executing task at the head of
+ *   the ready to run list must be stopped.  Save its context
+ *   and move it to the inactive list specified by task_state.
+ *
+ * Inputs:
+ *   tcb: Refers to a task in the ready-to-run list (normally
+ *     the task at the the head of the list).  It most be
+ *     stopped, its context saved and moved into one of the
+ *     waiting task lists.  It it was the task at the head
+ *     of the ready-to-run list, then a context to the new
+ *     ready to run task must be performed.
+ *   task_state: Specifies which waiting task list should be
+ *     hold the blocked task TCB.
+ *
+ ************************************************************/
+
+void up_block_task(_TCB *tcb, tstate_t task_state)
+{
+  /* Verify that the context switch can be performed */
+
+  if ((tcb->task_state < FIRST_READY_TO_RUN_STATE) ||
+      (tcb->task_state > LAST_READY_TO_RUN_STATE))
+    {
+      PANIC(OSERR_BADBLOCKSTATE);
+    }
+  else
+    {
+      _TCB *rtcb = (_TCB*)g_readytorun.head;
+      boolean switch_needed;
+
+      lldbg("Blocking TCB=%p\n", tcb);
+
+      /* Remove the tcb task from the ready-to-run list.  If we
+       * are blocking the task at the head of the task list (the
+       * most likely case), then a context switch to the next
+       * ready-to-run task is needed. In this case, it should
+       * also be true that rtcb == tcb.
+       */
+
+      switch_needed = sched_removereadytorun(tcb);
+
+      /* Add the task to the specified blocked task list */
+
+      sched_addblocked(tcb, (tstate_t)task_state);
+
+      /* If there are any pending tasks, then add them to the g_readytorun
+       * task list now
+       */
+
+      if (g_pendingtasks.head)
+        {
+          switch_needed |= sched_mergepending();
+        }
+
+      /* Now, perform the context switch if one is needed */
+
+      if (switch_needed)
+        {
+          /* Are we in an interrupt handler? */
+
+          if (current_regs)
+            {
+              /* Yes, then we have to do things differently.
+               * Just copy the current_regs into the OLD rtcb.
+               */
+
+               up_copystate(rtcb->xcp.regs, current_regs);
+
+              /* Restore the exception context of the rtcb at the (new) head 
+               * of the g_readytorun task list.
+               */
+
+              rtcb = (_TCB*)g_readytorun.head;
+              lldbg("New Active Task TCB=%p\n", rtcb);
+
+              /* Then switch contexts */
+
+              up_copystate(current_regs, rtcb->xcp.regs);
+            }
+
+          /* Copy the user C context into the TCB at the (old) head of the
+           * g_readytorun Task list. if up_saveusercontext returns a non-zero
+           * value, then this is really the previously running task restarting!
+           */
+
+          else if (!up_saveusercontext(rtcb->xcp.regs))
+            {
+              /* Restore the exception context of the rtcb at the (new) head 
+               * of the g_readytorun task list.
+               */
+
+              rtcb = (_TCB*)g_readytorun.head;
+              lldbg("New Active Task TCB=%p\n", rtcb);
+
+              /* Then switch contexts */
+
+              up_fullcontextrestore(rtcb->xcp.regs);
+            }
+        }
+    }
+}

arch/arm/src/common/up_cache.S

@@ -0,0 +1,74 @@
+/********************************************************************
+ * common/up_cache.S
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************/
+
+/********************************************************************
+ * Included Files
+ ********************************************************************/
+
+#include <nuttx/config.h>
+#include "up_internal.h"
+#include "up_arch.h"
+
+/********************************************************************
+ * Definitions
+ ********************************************************************/
+
+#define CACHE_DLINESIZE    32
+
+/********************************************************************
+ * Assembly Macros
+ ********************************************************************/
+
+/**************************************************************************
+ * Name: up_flushicache
+ **************************************************************************/
+
+/* Esure coherency between the Icache and the Dcache in the region described 
+ * by r0=start and r1=end.
+ */
+	.globl	up_flushicache
+	.type	up_flushicache,%function
+up_flushicache:
+	bic	r0, r0, #CACHE_DLINESIZE - 1
+1:	mcr	p15, 0, r0, c7, c10, 1		/* Clean D entry */
+	mcr	p15, 0, r0, c7, c5, 1		/* Invalidate I entry */
+	add	r0, r0, #CACHE_DLINESIZE
+	cmp	r0, r1
+	blo	1b
+	mcr	p15, 0, r0, c7, c10, 4		/* Drain WB */
+	mov	pc, lr
+	.size	up_flushicache, .-up_flushicache
+	.end
+

arch/arm/src/common/up_copystate.c

@@ -0,0 +1,75 @@
+/************************************************************
+ * common/up_copystate.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "os_internal.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/************************************************************
+ * Private Functions
+ ************************************************************/
+
+/************************************************************
+ * Public Funtions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_undefinedinsn
+ ************************************************************/
+
+/* A little faster than most memcpy's */
+
+void up_copystate(uint32 *dest, uint32 *src)
+{
+  int i;
+  for (i = 0; i < XCPTCONTEXT_REGS; i++)
+    {
+      *dest++ = *src++;
+    }
+}
+

arch/arm/src/common/up_createstack.c

@@ -0,0 +1,128 @@
+/************************************************************
+ * common/up_createstack.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <sched.h>
+#include <debug.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/arch.h>
+#include "up_arch.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Private Types
+ ************************************************************/
+
+/************************************************************
+ * Private Function Prototypes
+ ************************************************************/
+
+/************************************************************
+ * Global Functions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_create_stack
+ *
+ * Description:
+ *   Allocate a stack for a new thread and setup
+ *   up stack-related information in the TCB.
+ *
+ *   The following TCB fields must be initialized:
+ *   adj_stack_size: Stack size after adjustment for hardware,
+ *     processor, etc.  This value is retained only for debug
+ *     purposes.
+ *   stack_alloc_ptr: Pointer to allocated stack
+ *   adj_stack_ptr: Adjusted stack_alloc_ptr for HW.  The
+ *     initial value of the stack pointer.
+ *
+ * Inputs:
+ *   tcb: The TCB of new task
+ *   stack_size:  The requested stack size.  At least this much
+ *     must be allocated.
+ ************************************************************/
+
+STATUS up_create_stack(_TCB *tcb, size_t stack_size)
+{
+  if (tcb->stack_alloc_ptr &&
+      tcb->adj_stack_size != stack_size)
+    {
+      sched_free(tcb->stack_alloc_ptr);
+      tcb->stack_alloc_ptr = NULL;
+    }
+
+   if (!tcb->stack_alloc_ptr)
+     {
+       tcb->stack_alloc_ptr = (uint32 *)kzmalloc(stack_size);
+     }
+
+   if (tcb->stack_alloc_ptr)
+     {
+       size_t top_of_stack;
+       size_t size_of_stack;
+
+       /* The Arm7Tdmi uses a push-down stack:  the stack grows
+	* toward loweraddresses in memory.  The stack pointer
+	* register, points to the lowest, valid work address
+	* (the "top" of the stack).  Items on the stack are
+	* referenced as positive word offsets from sp.
+	*/
+
+       top_of_stack = (uint32)tcb->stack_alloc_ptr + stack_size - 4;
+
+       /* The Arm7Tdmi stack must be aligned at word (4 byte)
+	* boundaries. If necessary top_of_stack must be rounded
+	* down to the next boundary
+	*/
+
+       top_of_stack &= ~3;
+       size_of_stack = top_of_stack - (uint32)tcb->stack_alloc_ptr + 4;
+
+       /* Save the adjusted stack values in the _TCB */
+
+       tcb->adj_stack_ptr  = (uint32*)top_of_stack;
+       tcb->adj_stack_size = size_of_stack;
+
+       up_ledon(LED_STACKCREATED);
+       return OK;
+     }
+
+   return ERROR;
+}

arch/arm/src/common/up_dataabort.c

@@ -0,0 +1,81 @@
+/************************************************************
+ * common/up_dataabort.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <debug.h>
+#include <nuttx/irq.h>
+#include "os_internal.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/* Output debug info if stack dump is selected -- even if 
+ * debug is not selected.
+ */
+
+#ifdef CONFIG_ARCH_STACKDUMP
+# undef  lldbg
+# define lldbg lib_lowprintf
+#endif
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/************************************************************
+ * Private Functions
+ ************************************************************/
+
+/************************************************************
+ * Public Funtions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_dataabort
+ ************************************************************/
+
+void up_dataabort(uint32 *regs)
+{
+  lldbg("Data abort at 0x%x\n", regs[REG_PC]);
+  current_regs = regs;
+  PANIC(OSERR_ERREXCEPTION);
+}

arch/arm/src/common/up_delay.c

@@ -0,0 +1,100 @@
+/************************************************************
+ * common/up_delay.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <unistd.h>
+#include <semaphore.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/fs.h>
+#include <arch/serial.h>
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/************************************************************
+ * Private Types
+ ************************************************************/
+
+/************************************************************
+ * Private Function Prototypes
+ ************************************************************/
+
+/************************************************************
+ * Private Variables
+ ************************************************************/
+
+/************************************************************
+ * Private Functions
+ ************************************************************/
+
+
+/************************************************************
+ * Public Funtions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_delay
+ *
+ * Description:
+ *   Delay inline for the requested number of milliseconds.
+ *   NOT multi-tasking friendly.
+ *
+ ************************************************************/
+
+void up_delay(int milliseconds)
+{
+  volatile int i;
+  volatile int j;
+
+  for (i = 0; i < milliseconds; i++)
+    {
+        for (j = 0; j < CONFIG_BOARD_LOOPSPERMSEC; j++)
+          {
+          }
+    }
+}

arch/arm/src/common/up_doirq.c

@@ -0,0 +1,104 @@
+/************************************************************
+ * common/up_doirq.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <assert.h>
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/************************************************************
+ * Public Data
+ ************************************************************/
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/************************************************************
+ * Private Functions
+ ************************************************************/
+
+/************************************************************
+ * Public Funtions
+ ************************************************************/
+
+void up_doirq(int irq, uint32* regs)
+{
+  up_ledon(LED_INIRQ);
+#ifdef CONFIG_SUPPRESS_INTERRUPTS
+  PANIC(OSERR_ERREXCEPTION);
+#else
+  if ((unsigned)irq < NR_IRQS)
+    {
+       /* Current regs non-zero indicates that we are processing
+        * an interrupt; current_regs is also used to manage
+        * interrupt level context switches.
+        */
+
+       current_regs = regs;
+
+       /* Mask and acknowledge the interrupt */
+
+       up_maskack_irq(irq);
+
+       /* Deliver the IRQ */
+
+       irq_dispatch(irq, regs);
+
+       /* Indicate that we are no long in an interrupt handler */
+
+       current_regs = NULL;
+
+       /* Unmask the last interrupt (global interrupts are still
+        * disabled.
+        */
+
+       up_enable_irq(irq);
+    }
+  up_ledoff(LED_INIRQ);
+#endif
+}

arch/arm/src/common/up_exit.c

@@ -0,0 +1,188 @@
+/************************************************************
+ * common/up_exit.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <sched.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include "os_internal.h"
+#include "up_internal.h"
+
+#ifdef CONFIG_DUMP_ON_EXIT
+#include <nuttx/fs.h>
+#endif
+
+/************************************************************
+ * Private Definitions
+ ************************************************************/
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/************************************************************
+ * Private Funtions
+ ************************************************************/
+
+/************************************************************
+ * Name: _up_dumponexit
+ *
+ * Description:
+ *   Dump the state of all tasks whenever on task exits.  This
+ *   is debug instrumentation that was added to check file-
+ *   related reference counting but could be useful again
+ *   sometime in the future.
+ *
+ ************************************************************/
+
+#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG)
+static void _up_dumponexit(FAR _TCB *tcb, FAR void *arg)
+{
+  int i;
+  dbg("  TCB=%p name=%s\n", tcb, tcb->argv[0]);
+  if (tcb->filelist)
+    {
+      dbg("    filelist refcount=%d\n",
+          tcb->filelist->fl_crefs);
+
+      for (i = 0; i < CONFIG_NFILE_DESCRIPTORS; i++)
+        {
+          struct inode *inode = tcb->filelist->fl_files[i].f_inode;
+          if (inode)
+            {
+              dbg("      fd=%d refcount=%d\n",
+                  i, inode->i_crefs);
+            }
+        }
+    }
+
+  if (tcb->streams)
+    {
+      dbg("    streamlist refcount=%d\n",
+          tcb->streams->sl_crefs);
+
+      for (i = 0; i < CONFIG_NFILE_STREAMS; i++)
+        {
+          struct file_struct *filep = &tcb->streams->sl_streams[i];
+          if (filep->fs_filedes >= 0)
+            {
+              dbg("      fd=%d nbytes=%d\n",
+                  filep->fs_filedes,
+                  filep->fs_bufpos - filep->fs_bufstart);
+            }
+        }
+    }
+}
+#endif
+
+/************************************************************
+ * Public Funtions
+ ************************************************************/
+
+/************************************************************
+ * Name: _exit
+ *
+ * Description:
+ *   This function causes the currently executing task to cease
+ *   to exist.  This is a special case of task_delete().
+ *
+ ************************************************************/
+
+void _exit(int status)
+{
+  _TCB* tcb = (_TCB*)g_readytorun.head;
+
+  /* Disable interrupts.  They will be restored when the next
+   * task is started.
+   */
+
+  (void)irqsave();
+
+  lldbg("TCB=%p exitting\n", tcb);
+
+#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG)
+  dbg("Other tasks:\n");
+  sched_foreach(_up_dumponexit, NULL);
+#endif
+
+  /* Remove the tcb task from the ready-to-run list.  We can
+   * ignore the return value because we know that a context
+   * switch is needed.
+   */
+
+  (void)sched_removereadytorun(tcb);
+
+  /* We are not in a bad stack-- the head of the ready to run task list
+   * does not correspond to the thread that is running.  Disabling pre-
+   * emption on this TCB should be enough to keep things stable.
+   */
+
+  sched_lock();
+
+  /* Move the TCB to the specified blocked task list and delete it */
+
+  sched_addblocked(tcb, TSTATE_TASK_INACTIVE);
+  task_delete(tcb->pid);
+
+  /* If there are any pending tasks, then add them to the g_readytorun
+   * task list now
+   */
+
+  if (g_pendingtasks.head)
+    {
+      (void)sched_mergepending();
+    }
+
+  /* Now calling sched_unlock() should have no effect */
+
+  sched_unlock();
+
+  /* Now, perform the context switch to the new ready-to-run task at the
+   * head of the list.
+   */
+
+  tcb = (_TCB*)g_readytorun.head;
+  lldbg("New Active Task TCB=%p\n", tcb);
+
+  /* Then switch contexts */
+
+  up_fullcontextrestore(tcb->xcp.regs);
+}
+

arch/arm/src/common/up_fullcontextrestore.S

@@ -0,0 +1,117 @@
+/**************************************************************************
+ * common/up_fullcontextrestore.S
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ **************************************************************************/
+
+/**************************************************************************
+ * Included Files
+ **************************************************************************/
+
+#include <nuttx/irq.h>
+#include "up_internal.h"
+
+/**************************************************************************
+ * Private Definitions
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Types
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Function Prototypes
+ **************************************************************************/
+
+/**************************************************************************
+ * Global Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Public Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Name: up_fullcontextrestore
+ **************************************************************************/
+
+	.globl	up_fullcontextrestore
+	.type	up_fullcontextrestore, function
+up_fullcontextrestore:
+
+	/* On entry, a1 (r0) holds address of the register save area */
+
+	/* Recover all registers except for r0, r1, R15, and CPSR */
+
+	add	r1, r0, #(4*REG_R2)	/* Offset to REG_R2 storage */
+	ldmia	r1, {r2-r14}		/* Recover registers */
+
+	/* Create a stack frame to hold the PC */
+
+	sub	sp, sp, #(3*4)		/* Frame for three registers */
+	ldr	r1, [r0, #(4*REG_R0)]	/* Fetch the stored r0 value */
+	str	r1, [sp]		/* Save it at the top of the stack */
+	ldr	r1, [r0, #(4*REG_R1)]	/* Fetch the stored r1 value */
+	str	r1, [sp, #4]		/* Save it in the stack */
+	ldr	r1, [r0, #(4*REG_PC)]	/* Fetch the stored pc value */
+	str	r1, [sp, #8]		/* Save it at the bottom of the frame */
+
+	/* Now we can restore the CPSR.  We wait until we are completely
+	 * finished with the context save data to do this. Restore the CPSR
+	 * may re-enable and interrupts and we couldt be in a context
+	 * where save structure is only protected by interrupts being disabled.
+         */
+
+	ldr	r1, [r0, #(4*REG_CPSR)]	/* Fetch the stored CPSR value */
+	msr	cpsr, r1		/* Set the CPSR */
+
+	/* Now recover r0 and r1 */
+
+	ldr	r0, [sp]
+	ldr	r1, [sp, #4]
+	add	sp, sp, #(2*4)
+
+	/* Then return to the address at the stop of the stack,
+	 * destroying the stack frame
+	 */
+
+	ldr	pc, [sp], #4
+	.size up_fullcontextrestore, . - up_fullcontextrestore
+

arch/arm/src/common/up_head.S

@@ -0,0 +1,324 @@
+/********************************************************************
+ * common/up_head.S
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************/
+
+/********************************************************************
+ * Included Files
+ ********************************************************************/
+
+#include <nuttx/config.h>
+#include "up_internal.h"
+#include "up_arch.h"
+
+/**************************************************************************
+ * Conditional Compilation
+ **************************************************************************/
+
+#undef ALIGNMENT_TRAP
+#undef CPU_DCACHE_WRITETHROUGH
+#undef CPU_CACHE_ROUND_ROBIN
+#undef CPU_DCACHE_DISABLE
+#undef CPU_ICACHE_DISABLE
+
+/********************************************************************
+ * Definitions
+ ********************************************************************/
+
+/* The physical address of the beginning of SDRAM is provided by
+ * CONFIG_DRAM_START.  The size of installed SDRAM is provided by
+ * CONFIG_DRAM_SIZE.  The virtual address of SDRAM is provided by
+ * CONFIG_DRAM_VSTART.
+ */
+
+#define NSDRAM_SECTIONS (CONFIG_DRAM_SIZE >> 20)
+
+/********************************************************************
+ * Assembly Macros
+ ********************************************************************/
+
+/* Since the page table is closely related to the NuttX base
+ * address, we can convert the page table base address to the
+ * base address of the section containing both.
+ */
+
+	.macro	mksection, section, pgtable
+	bic	\section, \pgtable, #0x000ff000
+	.endm
+
+/* This macro will modify r0, r1, r2 and r14 */
+
+#ifdef CONFIG_DEBUG
+	.macro	showprogress, code
+	mov	r0, #\code
+	bl	up_lowputc
+	.endm
+#else
+	.macro	showprogress, code
+	.endm
+#endif
+
+/********************************************************************
+ * Name: __start
+ ********************************************************************/
+
+/* We assume the bootloader has already initialized most of the h/w for
+ * us and that only leaves us having to do some os specific things
+ * below.
+ */
+	.text
+        .global __start
+	.type	__start, #function
+__start:
+	/* Make sure that we are in SVC mode with all IRQs disabled */
+
+	mov	r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT)
+	msr	cpsr_c, r0
+
+	/* Clear the 16K level 1 page table */
+
+	ldr	r4, .LCppgtable		/* r4=phys. page table */
+	mov	r0, r4
+	mov	r1, #0
+	add	r2, r0, #PGTABLE_SIZE
+.Lpgtableclear:
+	str	r1, [r0], #4
+	str	r1, [r0], #4
+	str	r1, [r0], #4
+	str	r1, [r0], #4
+	teq	r0, r2
+	bne	.Lpgtableclear
+
+	/* Create identity mapping for first MB section to support
+	 * this startup logic executing out of the physical address
+	 * space.  This identity mapping will be removed by .Lvstart
+	 * (see below).
+	 */
+
+	mksection r0, r4			/* r0=phys. base section */
+	ldr	r1, .LCmmuflags		/* FLGS=MMU_MEMFLAGS */
+	add	r3, r1, r0		/* r3=flags + base */
+	str	r3, [r4, r0, lsr #18]	/* identity mapping */
+
+	/* Create a "normal" single section mapping for the first
+	 * MB of memory.  Now, we have the first 1MB mapping to
+	 * both phyical and virtual addresses.  The reset of the
+	 * SDRAM mapping will be completed in .Lvstart once we have
+	 * moved the physical mapping out of the way.
+	 */
+
+	ldr	r2, .LCvpgtable		/* r2=virt. page table */
+	mksection r0, r2			/* r0=virt. base section */
+	str	r3, [r4, r0, lsr #18]	/* identity mapping */
+
+	/* The following logic will set up the ARM926 for normal operation */
+
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7		/* Invalidate I,D caches */
+	mcr	p15, 0, r0, c7, c10, 4	/* Drain write buffer */
+	mcr	p15, 0, r0, c8, c7		/* Invalidate I,D TLBs */
+	mcr	p15, 0, r4, c2, c0		/* Load page table pointer */
+
+#ifdef CPU_DCACHE_WRITETHROUGH
+	mov	r0, #4			/* Disable write-back on caches explicitly */
+	mcr	p15, 7, r0, c15, c0, 0
+#endif 
+
+	/* Enable the MMU and caches
+	 * lr = Resume at .Lvstart with the MMU enabled
+	 */
+
+	ldr	lr, .LCvstart			/* Abs. virtual address */
+
+	mov	r0, #0x1f			/* Domains 0, 1 = client */
+	mcr	p15, 0, r0, c3, c0		/* Load domain access register */
+	mrc	p15, 0, r0, c1, c0		/* Get control register */
+	
+	/* Clear bits (see start.h) */
+
+	bic	r0, r0, #(CR_R|CR_F|CR_Z)
+	bic	r0, r0, #(CR_A|CR_C|CR_W)
+	bic	r0, r0, #(CR_I)
+
+	/* Set bits (see start.h) */
+
+	orr	r0, r0, #(CR_M|CR_P|CR_D)
+	orr	r0, r0, #(CR_S|CR_V)
+
+#ifdef CPU_CACHE_ROUND_ROBIN
+	orr	r0, r0, #(CR_RR)
+#endif
+#ifndef CPU_DCACHE_DISABLE
+	orr	r0, r0, #(CR_C)
+#endif
+#ifndef CPU_ICACHE_DISABLE
+	orr	r0, r0, #(CR_I)
+#endif
+#ifdef ALIGNMENT_TRAP
+	orr	r0, r0, #(CR_A)
+#endif
+	mcr	p15, 0, r0, c1, c0, 0		/* write control reg */
+
+	/* Get TMP=2 Processor ID register */
+
+	mrc	p15, 0, r1, c0, c0, 0		/* read id reg */
+	mov	r1, r1
+	mov	r1, r1
+
+	mov	pc, lr
+
+/**************************************************************************
+ * PC_Relative Data
+ **************************************************************************/
+
+	/* These addresses are all virtual address */
+	
+	.type	.LCvstart, %object
+.LCvstart:
+	.long	.Lvstart
+	.type	.LCmmuflags, %object
+.LCmmuflags:
+	.long	MMU_MEMFLAGS
+	.type	.LCppagetable, %object
+.LCppgtable:
+	.long	CONFIG_DRAM_START  /* Physical start of DRAM */
+	.type	.LCvpagetable, %object
+.LCvpgtable:
+	.long	CONFIG_DRAM_VSTART /* Virtual start of DRAM */
+	.size	_start, .-_start
+
+/**************************************************************************
+ * Name: .Lvstart
+ **************************************************************************/
+
+/* The following is executed after the MMU has been enabled. This uses
+ * absolute addresses; this is not position independent.
+ */
+	.align	5
+	.local	.Lvstart
+	.type	.Lvstart, %function
+.Lvstart:
+
+	/* Remove the temporary null mapping */
+
+	ldr	r4, .LCvpgtable		/* r4=virtual page table */
+	ldr	r1, .LCppgtable		/* r1=phys. page table */
+	mksection r3, r1			/* r2=phys. base addr */
+	mov	r0, #0			/* flags + base = 0 */
+	str	r0, [r4, r3, lsr #18]	/* Undo identity mapping */
+
+	/* Now setup the pagetables for our normal SDRAM mappings
+	 * mapped region.  We round NUTTX_START_VADDR down to the
+	 * nearest megabyte boundary.
+	 */
+
+	ldr	r1, .LCmmuflags		/* FLGS=MMU_MEMFLAGS */
+	add	r3, r3, r1		/* r3=flags + base */
+
+	add	r0, r4, #(NUTTX_START_VADDR & 0xff000000) >> 18
+	bic	r2, r3, #0x00f00000
+	str	r2, [r0]
+
+	add	r0, r0, #(NUTTX_START_VADDR & 0x00f00000) >> 18
+	str	r3, [r0], #4
+
+	/* Now map the remaining NSDRAM_SECTIONS-1 SDRAM sections */
+
+	.rept	NSDRAM_SECTIONS-1
+	add	r3, r3, #SECTION_SIZE
+	str	r3, [r0], #4
+	.endr
+
+	/* Zero BSS and set up the stack pointer */
+
+	adr	r0, .Linitparms
+	ldmia	r0, {r0, r1, sp}
+
+	/* Clear the frame pointer and .bss */
+
+	mov     fp, #0
+
+.Lbssinit:	
+	cmp     r0, r1		       /* Clear up to _bss_end_ */
+	strcc	fp, [r0],#4
+	bcc	.Lbssinit
+
+	/* Perform early C-level initialization */
+
+	bl	up_boot
+
+	/* Set up the LEDs */
+
+#ifdef CONFIG_ARCH_LEDS
+	bl	up_ledinit
+#endif
+	/* Perform early serial initialization */
+
+#ifdef CONFIG_DEV_CONSOLE
+	bl      up_earlyserialinit
+#endif
+
+	/* Finally branch to the OS entry point */
+
+	mov	lr, #0
+	b	os_start
+
+	/* Variables:
+	 * _sbss is the start of the BSS region (see ld.script)
+	 * _ebss is the end of the BSS regsion (see ld.script)
+	 * The idle task stack starts at the end of BSS and is
+	 * of size CONFIG_PROC_STACK_SIZE.  The heap continues
+	 * from there until the end of memory.  See g_heapbase
+	 * below.
+	 */
+
+.Linitparms:
+	.long	_sbss
+	.long	_ebss
+	.long	_ebss+CONFIG_PROC_STACK_SIZE-4
+	.size	.Lvstart, .-.Lvstart
+
+	/* This global variable is unsigned long g_heapbase and is
+	 * exported from here only because of its coupling to .Linitparms
+	 * above.
+	 */
+
+	.data
+	.align	4
+	.globl	g_heapbase
+	.type	g_heapbase, object
+g_heapbase:
+	.long	_ebss+CONFIG_PROC_STACK_SIZE
+	.size	g_heapbase, .-g_heapbase
+	.end
+

arch/arm/src/common/up_idle.c

@@ -0,0 +1,87 @@
+/************************************************************
+ * common/up_idle.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <nuttx/arch.h>
+#include "up_internal.h"
+
+/************************************************************
+ * Private Definitions
+ ************************************************************/
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/************************************************************
+ * Private Funtions
+ ************************************************************/
+
+/************************************************************
+ * Public Funtions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_idle
+ *
+ * Description:
+ *   up_idle() is the logic that will be executed when their
+ *   is no other ready-to-run task.  This is processor idle
+ *   time and will continue until some interrupt occurs to
+ *   cause a context switch from the idle task.
+ *
+ *   Processing in this state may be processor-specific. e.g.,
+ *   this is where power management operations might be
+ *   performed.
+ *
+ ************************************************************/
+
+void up_idle(void)
+{
+#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
+  /* If the system is idle and there are no timer interrupts,
+   * then process "fake" timer interrupts. Hopefully, something
+   * will wake up.
+   */
+
+  sched_process_timer();
+#endif
+}
+

arch/arm/src/common/up_initialize.c

@@ -0,0 +1,104 @@
+/************************************************************
+ * common/up_initialize.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include <nuttx/fs.h>
+#include "up_arch.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Private Types
+ ************************************************************/
+
+/************************************************************
+ * Private Function Prototypes
+ ************************************************************/
+
+/************************************************************
+ * Global Functions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_initialize
+ *
+ * Description:
+ *   up_initialize will be called once during OS
+ *   initialization after the basic OS services have been
+ *   initialized.  The architecture specific details of
+ *   initializing the OS will be handled here.  Such things as
+ *   setting up interrupt service routines, starting the
+ *   clock, and registering device drivers are some of the
+ *   things that are different for each processor and hardware
+ *   platform.
+ *
+ *   up_initialize is called after the OS initialized but
+ *   before the init process has been started and before the
+ *   libraries have been initialized.  OS services and driver
+ *   services are available.
+ *
+ ************************************************************/
+
+void up_initialize(void)
+{
+  /* Initialize global variables */
+
+  current_regs = NULL;
+
+  /* Initialize the interrupt subsystem */
+
+  up_irqinitialize();
+
+  /* Initialize the system timer interrupt */
+
+#if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS)
+  up_timerinit();
+#endif
+
+  /* Register devices */
+
+  devnull_register();   /* Standard /dev/null */
+
+  /* Initialize the serial device driver */
+
+  up_serialinit();
+  up_ledon(LED_IRQSENABLED);
+}

arch/arm/src/common/up_initialstate.c

@@ -0,0 +1,91 @@
+/************************************************************
+ * common/up_initialstate.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <string.h>
+#include <nuttx/arch.h>
+#include "up_internal.h"
+#include "up_arch.h"
+
+/************************************************************
+ * Private Definitions
+ ************************************************************/
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/************************************************************
+ * Private Funtions
+ ************************************************************/
+
+/************************************************************
+ * Public Funtions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_initial_state
+ *
+ * Description:
+ *   A new thread is being started and a new TCB
+ *   has been created. This function is called to initialize
+ *   the processor specific portions of the new TCB.
+ *
+ *   This function must setup the intial architecture registers
+ *   and/or  stack so that execution will begin at tcb->start
+ *   on the next context switch.
+ *
+ ************************************************************/
+
+void up_initial_state(_TCB *tcb)
+{
+  struct xcptcontext *xcp = &tcb->xcp;
+
+  /* Initialize the initial exception register context structure */
+
+  memset(xcp, 0, sizeof(struct xcptcontext));
+  xcp->regs[REG_SP]   = (uint32)tcb->adj_stack_ptr;
+  xcp->regs[REG_PC]   = (uint32)tcb->start;
+#ifdef CONFIG_SUPPRESS_INTERRUPTS
+  xcp->regs[REG_CPSR] = SVC_MODE | PSR_I_BIT | PSR_F_BIT;
+#else
+  xcp->regs[REG_CPSR] = SVC_MODE | PSR_F_BIT;
+#endif
+}

arch/arm/src/common/up_internal.h

@@ -0,0 +1,162 @@
+/************************************************************
+ * common/up_internal.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+#ifndef __UP_INTERNAL_H
+#define __UP_INTERNAL_H
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/* Bring-up debug configurations.  These are here (vs defconfig)
+ * because these should only be controlled during low level
+ * board bring-up and not part of normal platform configuration.
+ */
+
+#undef  CONFIG_SUPPRESS_INTERRUPTS    /* Do not enable interrupts */
+#undef  CONFIG_SUPPRESS_TIMER_INTS    /* No timer */
+#undef  CONFIG_SUPPRESS_SERIAL_INTS   /* Console will poll */
+#undef  CONFIG_SUPPRESS_UART_CONFIG   /* Do not reconfig UART */
+#define CONFIG_DUMP_ON_EXIT         1 /* Dump task state on exit */
+
+/************************************************************
+ * Public Types
+ ************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/************************************************************
+ * Public Variables
+ ************************************************************/
+
+#ifndef __ASSEMBLY__
+/* This holds a references to the current interrupt level
+ * register storage structure.  If is non-NULL only during
+ * interrupt processing.
+ */
+
+extern uint32 *current_regs;
+
+/* This is the beginning of heap as provided from up_head.S.
+ * This is the first address in DRAM after the loaded
+ * program+bss+idle stack.  The end of the heap is
+ * CONFIG_DRAM_END
+ */
+
+extern uint32 g_heapbase;
+#endif
+
+/************************************************************
+ * Inline Functions
+ ************************************************************/
+
+
+/************************************************************
+ * Public Functions
+ ************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* Defined in files with the same name as the function */
+
+extern void up_boot(void);
+extern void up_copystate(uint32 *dest, uint32 *src);
+extern void up_dataabort(uint32 *regs);
+extern void up_delay(int milliseconds);
+extern void up_decodeirq(uint32 *regs);
+extern void up_doirq(int irq, uint32 *regs);
+extern void up_fullcontextrestore(uint32 *regs) __attribute__ ((noreturn));
+extern void up_irqinitialize(void);
+extern void up_prefetchabort(uint32 *regs);
+extern int  up_saveusercontext(uint32 *regs);
+extern void up_sigdeliver(void);
+extern void up_syscall(uint32 *regs);
+extern int  up_timerisr(int irq, uint32 *regs);
+extern void up_undefinedinsn(uint32 *regs);
+
+#ifdef CONFIG_DEBUG
+extern void up_lowputc(char ch);
+#else
+# define up_lowputc(ch)
+#endif
+
+/* Defined in up_vectors.S */
+
+extern void up_vectorundefinsn(void);
+extern void up_vectorswi(void);
+extern void up_vectorprefetch(void);
+extern void up_vectordata(void);
+extern void up_vectoraddrexcptn(void);
+extern void up_vectorirq(void);
+extern void up_vectorfiq(void);
+
+/* Defined in up_serial.c */
+
+extern void up_earlyserialinit(void);
+extern void up_serialinit(void);
+
+/* Defined in up_watchdog.c */
+
+extern void up_wdtinit(void);
+
+/* Defined in up_timerisr.c */
+
+extern void up_timerinit(void);
+
+/* Defined in up_irq.c */
+
+extern void up_maskack_irq(int irq);
+
+/* Defined in board/up_leds.c */
+
+#ifdef CONFIG_ARCH_LEDS
+extern void up_ledinit(void);
+extern void up_ledon(int led);
+extern void up_ledoff(int led);
+#else
+# define up_ledinit()
+# define up_ledon(led)
+# define up_ledoff(led)
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif  /* __UP_INTERNAL_H */

arch/arm/src/common/up_interruptcontext.c

@@ -0,0 +1,68 @@
+/************************************************************
+ * common/up_interruptcontext.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include "up_internal.h"
+
+/************************************************************
+ * Private Types
+ ************************************************************/
+
+/************************************************************
+ * Private Function Prototypes
+ ************************************************************/
+
+/************************************************************
+ * Global Functions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_interrupt_context
+ *
+ * Description: Return TRUE is we are currently executing in
+ * the interrupt handler context.
+ ************************************************************/
+
+boolean up_interrupt_context(void)
+{
+   return current_regs != NULL;
+}

arch/arm/src/common/up_nommuhead.S

@@ -0,0 +1,162 @@
+/********************************************************************
+ * common/up_nommuhead.S
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************/
+
+/********************************************************************
+ * Included Files
+ ********************************************************************/
+
+#include <nuttx/config.h>
+#include "up_internal.h"
+#include "up_arch.h"
+
+/********************************************************************
+ * Macros
+ ********************************************************************/
+
+	/* This macro will modify r0, r1, r2 and r14 */
+
+#ifdef CONFIG_DEBUG
+	.macro	showprogress, code
+	mov	r0, #\code
+	bl	up_lowputc
+	.endm
+#else
+	.macro	showprogress, code
+	.endm
+#endif
+
+/********************************************************************
+ * OS Entry Point
+ ********************************************************************/
+
+/* We assume the bootloader has already initialized most of the h/w for
+ * us and that only leaves us having to do some os specific things
+ * below.
+ */
+	.text
+        .global __start
+	.type	__start, #function
+__start:
+
+	/* First, setup initial processor mode */
+
+	mov	r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT )
+	msr	cpsr, r0
+
+	showprogress 'A'
+
+	/* Setup system stack (and get the BSS range) */
+
+	adr	r0, LC0
+	ldmia   r0, {r4, r5, sp}
+
+	/* Clear system BSS section */
+
+	mov	r0, #0
+1:	cmp	r4, r5
+	strcc	r0, [r4], #4
+	bcc	1b
+
+	showprogress 'B'
+
+	/* Copy system .data sections to new home in RAM. */
+
+#ifdef CONFIG_BOOT_FROM_FLASH
+
+	adr	r3, LC2
+	ldmia	r3, {r0, r1, r2}
+
+1:	ldmia	r0!, {r3 - r10}
+	stmia	r1!, {r3 - r10}
+	cmp	r1, r2
+	blt	1b
+
+#endif
+	/* Perform early serial initialization */
+
+	mov	fp, #0
+	bl	up_earlyserialinit
+
+#ifdef CONFIG_DEBUG
+	mov	r0, #'C'
+	bl	up_putc
+	mov	r0, #'\n'
+	bl	up_putc
+#endif
+	/* Initialize onboard LEDs */
+
+#ifdef CONFIG_ARCH_LEDS
+	bl	up_ledinit
+#endif
+
+	/* Then jump to OS entry */
+
+	b	os_start
+
+	/* Variables:
+	 * _sbss is the start of the BSS region (see ld.script)
+	 * _ebss is the end of the BSS regsion (see ld.script)
+	 * The idle task stack starts at the end of BSS and is
+	 * of size CONFIG_PROC_STACK_SIZE.  The heap continues
+	 * from there until the end of memory.  See g_heapbase
+	 * below.
+	 */
+
+LC0:	.long	_sbss
+	.long	_ebss
+	.long	_ebss+CONFIG_PROC_STACK_SIZE-4
+
+#ifdef CONFIG_BOOT_FROM_FLASH
+LC2:	.long	_eronly	/* Where .data defaults are stored in FLASH */
+	.long	_sdata	/* Where .data needs to reside in SDRAM */
+	.long	_edata
+#endif
+	.size	__start, .-__start
+
+	/* This global variable is unsigned long g_heapbase and is
+	 * exported from here only because of its coupling to LCO
+	 * above.
+	 */
+
+	.data
+	.align	4
+	.globl	g_heapbase
+	.type	g_heapbase, object
+g_heapbase:
+	.long	_ebss+CONFIG_PROC_STACK_SIZE
+	.size	g_heapbase, .-g_heapbase
+
+	.end
+

arch/arm/src/common/up_prefetchabort.c

@@ -0,0 +1,81 @@
+/************************************************************
+ * common/up_prefetchabort.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <debug.h>
+#include <nuttx/irq.h>
+#include "os_internal.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/* Output debug info if stack dump is selected -- even if 
+ * debug is not selected.
+ */
+
+#ifdef CONFIG_ARCH_STACKDUMP
+# undef  lldbg
+# define lldbg lib_lowprintf
+#endif
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/************************************************************
+ * Private Functions
+ ************************************************************/
+
+/************************************************************
+ * Public Funtions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_prefetchabort
+ ************************************************************/
+
+void up_prefetchabort(uint32 *regs)
+{
+  lldbg("Prefetch abort at 0x%x\n", regs[REG_PC]);
+  current_regs = regs;
+  PANIC(OSERR_ERREXCEPTION);
+}

arch/arm/src/common/up_releasepending.c

@@ -0,0 +1,131 @@
+/************************************************************
+ * common/up_releasepending.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <sched.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include "os_internal.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Private Definitions
+ ************************************************************/
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/************************************************************
+ * Private Funtions
+ ************************************************************/
+
+/************************************************************
+ * Public Funtions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_release_pending
+ *
+ * Description:
+ *   Release and ready-to-run tasks that have
+ *   collected in the pending task list.  This can call a
+ *   context switch if a new task is placed at the head of
+ *   the ready to run list.
+ *
+ ************************************************************/
+
+void up_release_pending(void)
+{
+  _TCB *rtcb = (_TCB*)g_readytorun.head;
+
+  lldbg("From TCB=%p\n", rtcb);
+
+  /* Merge the g_pendingtasks list into the g_readytorun task list */
+
+  /* sched_lock(); */
+  if (sched_mergepending())
+    {
+      /* The currently active task has changed!  We will need to
+       * switch contexts.  First check if we are operating in
+       * interrupt context:
+       */
+
+      if (current_regs)
+        {
+          /* Yes, then we have to do things differently.
+           * Just copy the current_regs into the OLD rtcb.
+           */
+
+           up_copystate(rtcb->xcp.regs, current_regs);
+
+          /* Restore the exception context of the rtcb at the (new) head 
+           * of the g_readytorun task list.
+           */
+
+          rtcb = (_TCB*)g_readytorun.head;
+          lldbg("New Active Task TCB=%p\n", rtcb);
+
+          /* Then switch contexts */
+
+          up_copystate(current_regs, rtcb->xcp.regs);
+        }
+
+      /* Copy the exception context into the TCB of the task that
+       * was currently active. if up_saveusercontext returns a non-zero
+       * value, then this is really the previously running task 
+       * restarting!
+       */
+
+      else if (!up_saveusercontext(rtcb->xcp.regs))
+        {
+          /* Restore the exception context of the rtcb at the (new) head 
+           * of the g_readytorun task list.
+           */
+
+          rtcb = (_TCB*)g_readytorun.head;
+          lldbg("New Active Task TCB=%p\n", rtcb);
+
+           /* Then switch contexts */
+
+          up_fullcontextrestore(rtcb->xcp.regs);
+        }
+    }
+}

arch/arm/src/common/up_releasestack.c

@@ -0,0 +1,78 @@
+/************************************************************
+ * common/up_releasestack.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <sched.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include "os_internal.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Private Types
+ ************************************************************/
+
+/************************************************************
+ * Private Function Prototypes
+ ************************************************************/
+
+/************************************************************
+ * Global Functions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_release_stack
+ *
+ * Description:
+ *   A task has been stopped. Free all stack
+ *   related resources retained int the defunct TCB.
+ *
+ ************************************************************/
+
+void up_release_stack(_TCB *dtcb)
+{
+  if (dtcb->stack_alloc_ptr)
+    {
+      sched_free(dtcb->stack_alloc_ptr);
+      dtcb->stack_alloc_ptr = NULL;
+    }
+
+  dtcb->adj_stack_size = 0;
+}

arch/arm/src/common/up_reprioritizertr.c

@@ -0,0 +1,179 @@
+/************************************************************
+ * common/up_reprioritizertr.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <sched.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include "os_internal.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Private Definitions
+ ************************************************************/
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/************************************************************
+ * Private Funtions
+ ************************************************************/
+
+/************************************************************
+ * Public Funtions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_reprioritize_rtr
+ *
+ * Description:
+ *   Called when the priority of a running or
+ *   ready-to-run task changes and the reprioritization will 
+ *   cause a context switch.  Two cases:
+ *
+ *   1) The priority of the currently running task drops and the next
+ *      task in the ready to run list has priority.
+ *   2) An idle, ready to run task's priority has been raised above the
+ *      the priority of the current, running task and it now has the
+ *      priority.
+ *
+ * Inputs:
+ *   tcb: The TCB of the task that has been reprioritized
+ *   priority: The new task priority
+ *
+ ************************************************************/
+
+void up_reprioritize_rtr(_TCB *tcb, ubyte priority)
+{
+  /* Verify that the caller is sane */
+
+  if (tcb->task_state < FIRST_READY_TO_RUN_STATE ||
+      tcb->task_state > LAST_READY_TO_RUN_STATE ||
+      priority < SCHED_PRIORITY_MIN || 
+      priority > SCHED_PRIORITY_MAX)
+    {
+       PANIC(OSERR_BADREPRIORITIZESTATE);
+    }
+  else
+    {
+      _TCB *rtcb = (_TCB*)g_readytorun.head;
+      boolean switch_needed;
+
+      lldbg("TCB=%p PRI=%d\n", tcb, priority);
+
+      /* Remove the tcb task from the ready-to-run list.
+       * sched_removereadytorun will return TRUE if we just
+       * remove the head of the ready to run list.
+       */
+
+      switch_needed = sched_removereadytorun(tcb);
+
+      /* Setup up the new task priority */
+
+      tcb->sched_priority = (ubyte)priority;
+
+      /* Return the task to the specified blocked task list.
+       * sched_addreadytorun will return TRUE if the task was
+       * added to the new list.  We will need to perform a context
+       * switch only if the EXCLUSIVE or of the two calls is non-zero
+       * (i.e., one and only one the calls changes the head of the
+       * ready-to-run list).
+       */
+
+      switch_needed ^= sched_addreadytorun(tcb);
+
+      /* Now, perform the context switch if one is needed */
+
+      if (switch_needed)
+        {
+          /* If we are going to do a context switch, then now is the right
+           * time to add any pending tasks back into the ready-to-run list.
+           * task list now
+           */
+
+          if (g_pendingtasks.head)
+            {
+              sched_mergepending();
+            }
+
+         /* Are we in an interrupt handler? */
+
+          if (current_regs)
+            {
+              /* Yes, then we have to do things differently.
+               * Just copy the current_regs into the OLD rtcb.
+               */
+
+               up_copystate(rtcb->xcp.regs, current_regs);
+
+              /* Restore the exception context of the rtcb at the (new) head 
+               * of the g_readytorun task list.
+               */
+
+              rtcb = (_TCB*)g_readytorun.head;
+              lldbg("New Active Task TCB=%p\n", rtcb);
+
+              /* Then switch contexts */
+
+              up_copystate(current_regs, rtcb->xcp.regs);
+            }
+
+          /* Copy the exception context into the TCB at the (old) head of the
+           * g_readytorun Task list. if up_saveusercontext returns a non-zero
+           * value, then this is really the previously running task restarting!
+           */
+
+          else if (!up_saveusercontext(rtcb->xcp.regs))
+            {
+              /* Restore the exception context of the rtcb at the (new) head 
+               * of the g_readytorun task list.
+               */
+
+              rtcb = (_TCB*)g_readytorun.head;
+              lldbg("New Active Task TCB=%p\n", rtcb);
+
+              /* Then switch contexts */
+
+              up_fullcontextrestore(rtcb->xcp.regs);
+            }
+        }
+    }
+}

arch/arm/src/common/up_saveusercontext.S

@@ -0,0 +1,119 @@
+/**************************************************************************
+ * common/up_saveusercontext.S
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ **************************************************************************/
+
+/**************************************************************************
+ * Included Files
+ **************************************************************************/
+
+#include <nuttx/irq.h>
+#include "up_internal.h"
+
+/**************************************************************************
+ * Private Definitions
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Types
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Function Prototypes
+ **************************************************************************/
+
+/**************************************************************************
+ * Global Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Public Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Name: up_saveusercontext
+ **************************************************************************/
+
+	.text
+	.globl	up_saveusercontext
+	.type	up_saveusercontext, function
+up_saveusercontext:
+	/* On entry, a1 (r0) holds address of struct xcptcontext.
+	 * Offset to the user region.
+	 */
+
+	/* Make sure that the return value will be non-zero (the
+	 * value of the other volatile registers don't matter --
+	 * r1-r3, ip).  This function is called throught the
+	 * noraml C calling conventions and the values of these
+	 * registers cannot be assumed at the point of setjmp
+	 * return.
+	 */
+
+        mov	ip, #1
+	str	ip, [r0, #(4*REG_R0)]
+
+	/* Save the volatile registers (plus r12 which really
+	 * doesn't need to be saved)
+	 */
+
+	add	r1, r0, #(4*REG_R4)
+	stmia	r1, {r4-r14}
+
+	/* Save the current cpsr */
+
+	mrs	r2, cpsr		/* R3 = CPSR value */
+	add	r1, r0, #(4*REG_CPSR)
+	str	r2, [r1]
+
+	/* Finally save the return address as the PC so that we
+	 * return to the exit from this function.
+	 */
+
+        add	r1, r0, #(4*REG_PC)
+	str	lr, [r1]
+
+	/* Return 0 */
+
+	mov	r0, #0		/* Return value == 0 */
+	mov	pc, lr		/* Return */
+	.size	up_saveusercontext, . - up_saveusercontext
+

arch/arm/src/common/up_schedulesigaction.c

@@ -0,0 +1,190 @@
+/************************************************************
+ * common/up_schedulesigaction.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <sched.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include "os_internal.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+/************************************************************
+ * Private Definitions
+ ************************************************************/
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/************************************************************
+ * Private Funtions
+ ************************************************************/
+
+/************************************************************
+ * Public Funtions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_schedule_sigaction
+ *
+ * Description:
+ *   This function is called by the OS when one or more
+ *   signal handling actions have been queued for execution.
+ *   The architecture specific code must configure things so
+ *   that the 'igdeliver' callback is executed on the thread
+ *   specified by 'tcb' as soon as possible.
+ *
+ *   This function may be called from interrupt handling logic.
+ *
+ *   This operation should not cause the task to be unblocked
+ *   nor should it cause any immediate execution of sigdeliver.
+ *   Typically, a few cases need to be considered:
+ *
+ *   (1) This function may be called from an interrupt handler
+ *       During interrupt processing, all xcptcontext structures
+ *       should be valid for all tasks.  That structure should
+ *       be modified to invoke sigdeliver() either on return
+ *       from (this) interrupt or on some subsequent context
+ *       switch to the recipient task.
+ *   (2) If not in an interrupt handler and the tcb is NOT
+ *       the currently executing task, then again just modify
+ *       the saved xcptcontext structure for the recipient
+ *       task so it will invoke sigdeliver when that task is
+ *       later resumed.
+ *   (3) If not in an interrupt handler and the tcb IS the
+ *       currently executing task -- just call the signal
+ *       handler now.
+ *
+ ************************************************************/
+
+void up_schedule_sigaction(_TCB *tcb, sig_deliver_t sigdeliver)
+{
+  /* Refuse to handle nested signal actions */
+
+  dbg("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
+
+  if (!tcb->xcp.sigdeliver)
+    {
+      irqstate_t flags;
+
+      /* Make sure that interrupts are disabled */
+
+      flags = irqsave();
+
+      /* First, handle some special cases when the signal is
+       * being delivered to the currently executing task.
+       */
+
+      dbg("rtcb=0x%p current_regs=0x%p\n", g_readytorun.head, current_regs);
+
+      if (tcb == (_TCB*)g_readytorun.head)
+        {
+          /* CASE 1:  We are not in an interrupt handler and
+           * a task is signalling itself for some reason.
+           */
+
+          if (!current_regs)
+            {
+              /* In this case just deliver the signal now. */
+
+              sigdeliver(tcb);
+            }
+
+          /* CASE 2:  We are in an interrupt handler AND the
+           * interrupted task is the same as the one that
+           * must receive the signal, then we will have to modify
+           * the return state as well as the state in the TCB.
+           */
+
+          else
+            {
+              /* Save the return lr and cpsr and one scratch register
+               * These will be restored by the signal trampoline after
+               * the signals have been delivered.
+               */
+
+              tcb->xcp.sigdeliver    = sigdeliver;
+              tcb->xcp.saved_pc      = current_regs[REG_PC];
+              tcb->xcp.saved_cpsr    = current_regs[REG_CPSR];
+
+              /* Then set up to vector to the trampoline with interrupts
+               * disabled
+               */
+
+              current_regs[REG_PC]    = (uint32)up_sigdeliver;
+              current_regs[REG_CPSR]  = SVC_MODE | PSR_I_BIT | PSR_F_BIT;
+
+              /* And make sure that the saved context in the TCB
+               * is the same as the interrupt return context.
+               */
+
+              up_copystate(tcb->xcp.regs, current_regs);
+            }
+        }
+
+      /* Otherwise, we are (1) signaling a task is not running
+       * from an interrupt handler or (2) we are not in an
+       * interrupt handler and the running task is signalling
+       * some non-running task.
+       */
+
+      else
+        {
+          /* Save the return lr and cpsr and one scratch register
+           * These will be restored by the signal trampoline after
+           * the signals have been delivered.
+           */
+
+          tcb->xcp.sigdeliver    = sigdeliver;
+          tcb->xcp.saved_pc      = tcb->xcp.regs[REG_PC];
+          tcb->xcp.saved_cpsr    = tcb->xcp.regs[REG_CPSR];
+
+          /* Then set up to vector to the trampoline with interrupts
+           * disabled
+           */
+
+          tcb->xcp.regs[REG_PC]   = (uint32)up_sigdeliver;
+          tcb->xcp.regs[REG_CPSR] = SVC_MODE | PSR_I_BIT | PSR_F_BIT;
+        }
+
+      irqrestore(flags);
+    }
+}

arch/arm/src/common/up_sigdeliver.c

@@ -0,0 +1,135 @@
+/************************************************************
+ * common/up_sigdeliver.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <sched.h>
+#include <debug.h>
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include "os_internal.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/************************************************************
+ * Private Functions
+ ************************************************************/
+
+/************************************************************
+ * Public Funtions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_sigdeliver
+ *
+ * Description:
+ *   This is the a signal handling trampoline.  When a
+ *   signal action was posted.  The task context was mucked
+ *   with and forced to branch to this location with interrupts
+ *   disabled.
+ *
+ ************************************************************/
+
+void up_sigdeliver(void)
+{
+  _TCB  *rtcb = (_TCB*)g_readytorun.head;
+  uint32 regs[XCPTCONTEXT_REGS];
+  sig_deliver_t sigdeliver;
+
+  /* Save the errno.  This must be preserved throughout the
+   * signal handling so that the the user code final gets
+   * the correct errno value (probably EINTR).
+   */
+
+  int saved_errno = rtcb->errno;
+
+  up_ledon(LED_SIGNAL);
+
+  dbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
+       rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
+  ASSERT(rtcb->xcp.sigdeliver != NULL);
+
+  /* Save the real return state on the stack. */
+
+  up_copystate(regs, rtcb->xcp.regs);
+  regs[REG_PC]   = rtcb->xcp.saved_pc;
+  regs[REG_CPSR] = rtcb->xcp.saved_cpsr;
+
+  /* Get a local copy of the sigdeliver function pointer.
+   * we do this so that we can nullify the sigdeliver
+   * function point in the TCB and accept more signal
+   * deliveries while processing the current pending
+   * signals.
+   */
+
+  sigdeliver           = rtcb->xcp.sigdeliver;
+  rtcb->xcp.sigdeliver = NULL;
+
+  /* Then restore the task interrupt statat. */
+
+  irqrestore(regs[REG_CPSR]);
+
+  /* Deliver the signals */
+
+  sigdeliver(rtcb);
+
+  /* Output any debug messaged BEFORE restoreing errno
+   * (becuase they may alter errno), then restore the
+   * original errno that is needed by the user logic
+   * (it is probably EINTR).
+   */
+
+  dbg("Resuming\n");
+  rtcb->errno = saved_errno;
+
+  /* Then restore the correct state for this thread of
+   * execution.
+   */
+
+  up_ledoff(LED_SIGNAL);
+  up_fullcontextrestore(regs);
+}

arch/arm/src/common/up_syscall.c

@@ -0,0 +1,94 @@
+/************************************************************
+ * common/up_syscall.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <debug.h>
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/* Output debug info if stack dump is selected -- even if 
+ * debug is not selected.
+ */
+
+#ifdef CONFIG_ARCH_STACKDUMP
+# undef  lldbg
+# define lldbg lib_lowprintf
+#endif
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/************************************************************
+ * vectors
+ ************************************************************/
+
+/************************************************************
+ * Private Functions
+ ************************************************************/
+
+/************************************************************
+ * Public Functions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_syscall
+ *
+ * Description:
+ *   SWI interrupts will vection here with insn=the SWI
+ *   instruction and xcp=the interrupt context
+ *
+ *   The handler may get the SWI number be de-referencing
+ *   the return address saved in the xcp and decoding
+ *   the SWI instruction
+ *
+ ************************************************************/
+
+void up_syscall(uint32 *regs)
+{
+  lldbg("Syscall from 0x%x\n", regs[REG_PC]);
+  current_regs = regs;
+  PANIC(OSERR_ERREXCEPTION);
+}

arch/arm/src/common/up_unblocktask.c

@@ -0,0 +1,162 @@
+/************************************************************
+ * common/up_unblocktask.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <sched.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include "os_internal.h"
+#include "clock_internal.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Private Definitions
+ ************************************************************/
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/************************************************************
+ * Private Funtions
+ ************************************************************/
+
+/************************************************************
+ * Public Funtions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_unblock_task
+ *
+ * Description:
+ *   A task is currently in an inactive task list
+ *   but has been prepped to execute.  Move the TCB to the
+ *   ready-to-run list, restore its context, and start execution.
+ *
+ * Inputs:
+ *   tcb: Refers to the tcb to be unblocked.  This tcb is
+ *     in one of the waiting tasks lists.  It must be moved to
+ *     the ready-to-run list and, if it is the highest priority
+ *     ready to run taks, executed.
+ *
+ ************************************************************/
+
+void up_unblock_task(_TCB *tcb)
+{
+  /* Verify that the context switch can be performed */
+
+  if ((tcb->task_state < FIRST_BLOCKED_STATE) ||
+      (tcb->task_state > LAST_BLOCKED_STATE))
+    {
+      PANIC(OSERR_BADUNBLOCKSTATE);
+    }
+  else
+    {
+      _TCB *rtcb = (_TCB*)g_readytorun.head;
+
+      lldbg("Unblocking TCB=%p\n", tcb);
+
+      /* Remove the task from the blocked task list */
+
+      sched_removeblocked(tcb);
+
+      /* Reset its timeslice.  This is only meaningful for round
+       * robin tasks but it doesn't here to do it for everything
+       */
+
+#if CONFIG_RR_INTERVAL > 0
+      tcb->timeslice = CONFIG_RR_INTERVAL / MSEC_PER_TICK;
+#endif
+
+      /* Add the task in the correct location in the prioritized
+       * g_readytorun task list
+       */
+
+      if (sched_addreadytorun(tcb))
+        {
+          /* The currently active task has changed! We need to do
+           * a context switch to the new task.
+           *
+           * Are we in an interrupt handler? 
+           */
+
+          if (current_regs)
+            {
+              /* Yes, then we have to do things differently.
+               * Just copy the current_regs into the OLD rtcb.
+               */
+
+               up_copystate(rtcb->xcp.regs, current_regs);
+
+              /* Restore the exception context of the rtcb at the (new) head 
+               * of the g_readytorun task list.
+               */
+
+              rtcb = (_TCB*)g_readytorun.head;
+              lldbg("New Active Task TCB=%p\n", rtcb);
+
+              /* Then switch contexts */
+
+              up_copystate(current_regs, rtcb->xcp.regs);
+            }
+
+          /* We are not in an interrupt handler.  Copy the user C context
+           * into the TCB of the task that was previously active.  if 
+           * up_saveusercontext returns a non-zero value, then this is really the
+           * previously running task restarting!
+           */
+
+          else if (!up_saveusercontext(rtcb->xcp.regs))
+            {
+              /* Restore the exception context of the new task that is ready to
+               * run (probably tcb).  This is the new rtcb at the head of the
+               * g_readytorun task list.
+               */
+
+              rtcb = (_TCB*)g_readytorun.head;
+              lldbg("New Active Task TCB=%p\n", rtcb);
+
+              /* Then switch contexts */
+
+              up_fullcontextrestore(rtcb->xcp.regs);
+            }
+        }
+    }
+}

arch/arm/src/common/up_undefinedinsn.c

@@ -0,0 +1,79 @@
+/************************************************************
+ * common/up_undefinedinsn.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "os_internal.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/* Output debug info if stack dump is selected -- even if 
+ * debug is not selected.
+ */
+
+#ifdef CONFIG_ARCH_STACKDUMP
+# undef  lldbg
+# define lldbg lib_lowprintf
+#endif
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/************************************************************
+ * Private Functions
+ ************************************************************/
+
+/************************************************************
+ * Public Functions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_undefinedinsn
+ ************************************************************/
+
+void up_undefinedinsn(uint32 *regs)
+{
+  lldbg("Undefined instruction at 0x%x\n", regs[REG_PC]);
+  current_regs = regs;
+  PANIC(OSERR_UNDEFINEDINSN);
+}

arch/arm/src/common/up_usestack.c

@@ -0,0 +1,118 @@
+/************************************************************
+ * common/up_usestack.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <sched.h>
+#include <debug.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/arch.h>
+#include "up_internal.h"
+
+/************************************************************
+ * Private Types
+ ************************************************************/
+
+/************************************************************
+ * Private Function Prototypes
+ ************************************************************/
+
+/************************************************************
+ * Global Functions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_use_stack
+ *
+ * Description:
+ *   Setup up stack-related information in the TCB
+ *   using pre-allocated stack memory
+ *
+ *   The following TCB fields must be initialized:
+ *   adj_stack_size: Stack size after adjustment for hardware,
+ *     processor, etc.  This value is retained only for debug
+ *     purposes.
+ *   stack_alloc_ptr: Pointer to allocated stack
+ *   adj_stack_ptr: Adjusted stack_alloc_ptr for HW.  The
+ *     initial value of the stack pointer.
+ *
+ * Inputs:
+ *   tcb: The TCB of new task
+ *   stack_size:  The allocated stack size.
+ *
+ ************************************************************/
+
+STATUS up_use_stack(_TCB *tcb, void *stack, size_t stack_size)
+{
+  size_t top_of_stack;
+  size_t size_of_stack;
+
+  if (tcb->stack_alloc_ptr)
+    {
+      sched_free(tcb->stack_alloc_ptr);
+    }
+
+  /* Save the stack allocation */
+
+  tcb->stack_alloc_ptr = stack;
+
+  /* The Arm7Tdmi uses a push-down stack:  the stack grows
+   * toward loweraddresses in memory.  The stack pointer
+   * register, points to the lowest, valid work address
+   * (the "top" of the stack).  Items on the stack are
+   * referenced as positive word offsets from sp.
+   */
+
+  top_of_stack = (uint32)tcb->stack_alloc_ptr + stack_size - 4;
+
+  /* The Arm7Tdmi stack must be aligned at word (4 byte)
+   * boundaries. If necessary top_of_stack must be rounded
+   * down to the next boundary
+   */
+
+  top_of_stack &= ~3;
+  size_of_stack = top_of_stack - (uint32)tcb->stack_alloc_ptr + 4;
+
+  /* Save the adjusted stack values in the _TCB */
+
+  tcb->adj_stack_size = top_of_stack;
+  tcb->adj_stack_size = size_of_stack;
+
+  return OK;
+}

arch/arm/src/common/up_vectors.S

@@ -0,0 +1,422 @@
+/********************************************************************
+ * common/up_vectors.S
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************/
+
+/********************************************************************
+ * Included Files
+ ********************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+#include "up_arch.h"
+
+/********************************************************************
+ * Definitions
+ ********************************************************************/
+
+/********************************************************************
+ * Global Data
+ ********************************************************************/
+
+	.data
+g_irqtmp:
+	.word	0		/* Saved lr */
+	.word	0		/* Saved spsr */
+g_undeftmp:
+	.word	0		/* Saved lr */
+	.word	0		/* Saved spsr */
+g_aborttmp:
+	.word	0		/* Saved lr */
+	.word	0		/* Saved spsr */
+
+/********************************************************************
+ * Assembly Macros
+ ********************************************************************/
+
+/********************************************************************
+ * Private Functions
+ ********************************************************************/
+
+	.text
+
+/********************************************************************
+ * Public Functions
+ ********************************************************************/
+
+	.text
+
+/********************************************************************
+ * Name: up_vectorirq
+ *
+ * Description:
+ *   Interrupt excetpion. Entered in IRQ mode with spsr = SVC
+ *   CPSR, lr = SVC PC
+ ********************************************************************/
+
+	.globl	up_vectorirq
+	.type	up_vectorirq, %function
+up_vectorirq:
+	/* On entry, we are in IRQ mode.  We are free to use
+	 * the IRQ mode r13 and r14.
+         *
+	 */
+
+	ldr	r13, .Lirqtmp
+	sub	lr, lr, #4
+	str	lr, [r13]			@ save lr_IRQ
+	mrs	lr, spsr
+	str	lr, [r13, #4]			@ save spsr_IRQ
+
+	/* Then switch back to SVC mode */
+
+	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
+	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
+	msr	cpsr_c, lr		/* Switch to SVC mode */
+
+	/* Create a context structure.  First set aside a stack frame
+	 * and store r0-r12 into the frame.
+	 */
+
+	sub	sp, sp, #XCPTCONTEXT_SIZE
+	stmia	sp, {r0-r12}		/* Save the SVC mode regs */
+
+	/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
+
+	add	r1, sp, #XCPTCONTEXT_SIZE
+	mov	r2, r14
+
+	/* Get the values for r15(pc) and CPSR in r3 and r4 */
+
+	ldr	r0, .Lirqtmp		/* Points to temp storage */
+	ldmia	r0, {r3, r4}		/* Recover r1=lr_IRQ, r2=spsr_IRQ */
+
+	add	r0, sp, #(4*REG_SP)	/* Offset to pc, cpsr storage */
+	stmia	r0, {r1-r4}
+
+	/* Then call the IRQ handler with interrupts disabled. */
+
+	mov	fp, #0			/* Init frame pointer */
+	mov	r0, sp			/* Get r0=xcp */
+	bl	up_decodeirq		/* Call the handler */
+
+	/* Restore the CPSR, SVC modr registers and return */
+.Lnoirqset:
+	ldr	r0, [sp, #(4*REG_CPSR)]	/* Setup the SVC mode SPSR */
+	msr	spsr, r0
+	ldmia	sp, {r0-r15}^		/* Return */
+
+.Lirqtmp:
+	.word	g_irqtmp
+	.size	up_vectorirq, . - up_vectorirq
+
+	.align	5
+
+/********************************************************************
+ * Function: up_vectorswi
+ * 
+ * Description:
+ *   SWI interrupt. We enter the SWI in SVC mode
+ ********************************************************************/
+
+	.globl	up_vectorswi
+	.type	up_vectorswi, %function
+up_vectorswi:
+
+	/* Create a context structure.  First set aside a stack frame
+	 * and store r0-r12 into the frame.
+	 */
+
+	sub	sp, sp, #XCPTCONTEXT_SIZE
+	stmia	sp, {r0-r12}		/* Save the SVC mode regs */
+
+	/* Get the correct values of r13(sp), r14(lr), r15(pc)
+	 * and CPSR in r1-r4 */
+
+	add	r1, sp, #XCPTCONTEXT_SIZE
+	mov	r2, r14			/* R14 is altered on return from SWI */
+	mov	r3, r14			/* Save r14 as the PC as well */
+	mrs	r4, spsr		/* Get the saved CPSR */
+
+	add	r0, sp, #(4*REG_SP)	/* Offset to pc, cpsr storage */
+	stmia	r0, {r1-r4}
+
+	/* Then call the SWI handler with interrupts disabled.
+	 * void up_syscall(struct xcptcontext *xcp)
+	 */
+
+	mov	fp, #0			/* Init frame pointer */
+	mov	r0, sp			/* Get r0=xcp */
+	bl	up_syscall		/* Call the handler */
+
+	/* Restore the CPSR, SVC modr registers and return */
+
+	ldr	r0, [sp, #(4*REG_CPSR)]	/* Setup the SVC mode SPSR */
+	msr	spsr, r0
+	ldmia	sp, {r0-r15}^		/* Return */
+	.size	up_vectorswi, . - up_vectorswi
+
+	.align	5
+
+/********************************************************************
+ * Name: up_vectordata
+ *
+ * Description:
+ *   Data abort Exception dispatcher. Give control to data
+ *   abort handler.  This function is entered in ABORT mode
+ *   with spsr = SVC CPSR, lr = SVC PC
+ *
+ ********************************************************************/
+	
+	.globl	up_vectordata
+	.type	up_vectordata, %function
+up_vectordata:
+	/* On entry we are free to use the ABORT mode registers
+	 * r13 and r14
+	 */
+
+	ldr	r13, .Ldaborttmp	/* Points to temp storage */
+	sub	lr, lr, #8		/* Fixup return */
+	str	lr, [r13]		/* Save in temp storage */
+	mrs	lr, spsr		/* Get SPSR */
+	str	lr, [r13, #4]		/* Save in temp storage */
+
+	/* Then switch back to SVC mode */
+
+	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
+	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
+	msr	cpsr_c, lr		/* Switch to SVC mode */
+
+	/* Create a context structure.  First set aside a stack frame
+	 * and store r0-r12 into the frame.
+	 */
+
+	sub	sp, sp, #XCPTCONTEXT_SIZE
+	stmia	sp, {r0-r12}		/* Save the SVC mode regs */
+
+	/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
+
+	add	r1, sp, #XCPTCONTEXT_SIZE
+	mov	r2, r14
+
+	/* Get the values for r15(pc) and CPSR in r3 and r4 */
+
+	ldr	r0, .Ldaborttmp		/* Points to temp storage */
+	ldmia	r0, {r3, r4}		/* Recover r1=lr_IRQ, r2=spsr_IRQ */
+
+	add	r0, sp, #(4*REG_SP)	/* Offset to pc, cpsr storage */
+	stmia	r0, {r1-r4}
+
+	/* Then call the data abort handler with interrupts disabled.
+	 * void up_dataabort(struct xcptcontext *xcp)
+	 */
+
+	mov	fp, #0			/* Init frame pointer */
+	mov	r0, sp			/* Get r0=xcp */
+	bl	up_dataabort		/* Call the handler */
+
+	/* Restore the CPSR, SVC modr registers and return */
+
+	ldr	r0, [sp, #(4*REG_CPSR)]	/* Setup the SVC mode SPSR */
+	msr	spsr_cxsf, r0
+	ldmia	sp, {r0-r15}^		/* Return */
+
+.Ldaborttmp:
+	.word	g_aborttmp
+	.size	up_vectordata, . - up_vectordata
+
+	.align	5
+
+/********************************************************************
+ * Name: up_vectorprefetch
+ *
+ * Description:
+ *    Prefetch abort exception.  Entered in ABT mode with
+ *    spsr = SVC CPSR, lr = SVC PC
+ ********************************************************************/
+	
+	.globl	up_vectorprefetch
+	.type	up_vectorprefetch, %function
+up_vectorprefetch:
+	/* On entry we are free to use the ABORT mode registers
+	 * r13 and r14
+	 */
+
+	ldr	r13, .Lpaborttmp	/* Points to temp storage */
+	sub	lr, lr, #4		/* Fixup return */
+	str	lr, [r13]		/* Save in temp storage */
+	mrs	lr, spsr		/* Get SPSR */
+	str	lr, [r13, #4]		/* Save in temp storage */
+
+	/* Then switch back to SVC mode */
+
+	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
+	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
+	msr	cpsr_c, lr		/* Switch to SVC mode */
+
+	/* Create a context structure.  First set aside a stack frame
+	 * and store r0-r12 into the frame.
+	 */
+
+	sub	sp, sp, #XCPTCONTEXT_SIZE
+	stmia	sp, {r0-r12}		/* Save the SVC mode regs */
+
+	/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
+
+	add	r1, sp, #XCPTCONTEXT_SIZE
+	mov	r2, r14
+
+	/* Get the values for r15(pc) and CPSR in r3 and r4 */
+
+	ldr	r0, .Lpaborttmp		/* Points to temp storage */
+	ldmia	r0, {r3, r4}		/* Recover r1=lr_IRQ, r2=spsr_IRQ */
+
+	add	r0, sp, #(4*REG_SP)	/* Offset to pc, cpsr storage */
+	stmia	r0, {r1-r4}
+
+	/* Then call the prefetch abort handler with interrupts disabled.
+	 * void up_prefetchabort(struct xcptcontext *xcp)
+	 */
+
+	mov	fp, #0			/* Init frame pointer */
+	mov	r0, sp			/* Get r0=xcp */
+	bl	up_prefetchabort	/* Call the handler */
+
+	/* Restore the CPSR, SVC modr registers and return */
+
+	ldr	r0, [sp, #(4*REG_CPSR)]	/* Setup the SVC mode SPSR */
+	msr	spsr_cxsf, r0
+	ldmia	sp, {r0-r15}^		/* Return */
+
+.Lpaborttmp:
+	.word	g_aborttmp
+	.size	up_vectorprefetch, . - up_vectorprefetch
+
+	.align	5
+
+/********************************************************************
+ * Name: up_vectorundefinsn
+ *
+ * Description:
+ *   Undefined instruction entry exception.  Entered in
+ *   UND mode, spsr = SVC  CPSR, lr = SVC PC
+ *
+ ********************************************************************/
+	
+	.globl	up_vectorundefinsn
+	.type	up_vectorundefinsn, %function
+up_vectorundefinsn:
+	/* On entry we are free to use the UND mode registers
+	 * r13 and r14
+	 */
+
+	ldr	r13, .Lundeftmp		/* Points to temp storage */
+	str	lr, [r13]		/* Save in temp storage */
+	mrs	lr, spsr		/* Get SPSR */
+	str	lr, [r13, #4]		/* Save in temp storage */
+
+	/* Then switch back to SVC mode */
+
+	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
+	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
+	msr	cpsr_c, lr		/* Switch to SVC mode */
+
+	/* Create a context structure.  First set aside a stack frame
+	 * and store r0-r12 into the frame.
+	 */
+
+	sub	sp, sp, #XCPTCONTEXT_SIZE
+	stmia	sp, {r0-r12}		/* Save the SVC mode regs */
+
+	/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
+
+	add	r1, sp, #XCPTCONTEXT_SIZE
+	mov	r2, r14
+
+	/* Get the values for r15(pc) and CPSR in r3 and r4 */
+
+	ldr	r0, .Lundeftmp		/* Points to temp storage */
+	ldmia	r0, {r3, r4}		/* Recover r1=lr_IRQ, r2=spsr_IRQ */
+
+	add	r0, sp, #(4*REG_SP)	/* Offset to pc, cpsr storage */
+	stmia	r0, {r1-r4}
+
+	/* Then call the undef insn handler with interrupts disabled.
+	 * void up_undefinedinsn(struct xcptcontext *xcp)
+	 */
+
+	mov	fp, #0			/* Init frame pointer */
+	mov	r0, sp			/* Get r0=xcp */
+	bl	up_undefinedinsn	/* Call the handler */
+
+	/* Restore the CPSR, SVC modr registers and return */
+
+	ldr	r0, [sp, #(4*REG_CPSR)]	/* Setup the SVC mode SPSR */
+	msr	spsr_cxsf, r0
+	ldmia	sp, {r0-r15}^		/* Return */
+
+.Lundeftmp:
+	.word	g_undeftmp
+	.size	up_vectorundefinsn, . - up_vectorundefinsn
+
+	.align	5
+
+/********************************************************************
+ * Name: up_vectorfiq
+ *
+ * Description:
+ *   Shouldn't happen
+ ********************************************************************/
+
+	.globl	up_vectorfiq
+	.type	up_vectorfiq, %function
+up_vectorfiq:
+	subs	pc, lr, #4
+	.size	up_vectofiq, . - up_vectorfiq
+
+	.align	5
+
+/********************************************************************
+ *  Name: up_vectoraddrexcption
+ *
+ * Description:
+ *   Shouldn't happen
+ *
+ ********************************************************************/
+
+	.globl	up_vectoraddrexcptn
+	.type	up_vectoraddrexcptn, %function
+up_vectoraddrexcptn:
+	b	up_vectoraddrexcptn
+	.size	up_vectoaddrexcptn, . - up_vectoraddrexcptn
+	.end

arch/arm/src/common/up_vectortab.S

@@ -0,0 +1,103 @@
+/********************************************************************
+ * common/up_vectortab.S
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************/
+
+/********************************************************************
+ * Included Files
+ ********************************************************************/
+
+#include <nuttx/config.h>
+
+/********************************************************************
+ * Definitions
+ ********************************************************************/
+
+/********************************************************************
+ * Global Data
+ ********************************************************************/
+
+/********************************************************************
+ * Assembly Macros
+ ********************************************************************/
+
+/********************************************************************
+ * Name: _vector_start
+ *
+ * Description:
+ *   Vector initialization block
+ ********************************************************************/
+
+	.globl	_vector_start
+
+/* These will be relocated to VECTOR_BASE. */
+
+_vector_start:
+	ldr	pc, .Lresethandler		/* 0x00: Reset */
+	ldr	pc, .Lundefinedhandler		/* 0x04: Undefined instruction */
+	ldr	pc, .Lswihandler		/* 0x08: Software interrupt */
+	ldr	pc, .Lprefetchaborthandler	/* 0x0c: Prefetch abort */
+	ldr	pc, .Ldataaborthandler		/* 0x10: Data abort */
+	ldr	pc, .Laddrexcptnhandler		/* 0x14: Address exception */
+	ldr	pc, .Lirqhandler		/* 0x18: IRQ */
+	ldr	pc, .Lfiqhandler		/* 0x1c: FIQ */
+
+	.globl   __start
+	.globl	up_vectorundefinsn
+	.globl	up_vectorswi
+	.globl	up_vectorprefetch
+	.globl	up_vectordata
+	.globl	up_vectoraddrexcptn
+	.globl	up_vectorirq
+	.globl	up_vectorfiq
+
+.Lresethandler:
+	.long   __start
+.Lundefinedhandler:
+	.long	up_vectorundefinsn
+.Lswihandler:
+	.long	up_vectorswi
+.Lprefetchaborthandler:
+	.long	up_vectorprefetch
+.Ldataaborthandler:
+	.long	up_vectordata
+.Laddrexcptnhandler:
+	.long	up_vectoraddrexcptn
+.Lirqhandler:
+	.long	up_vectorirq
+.Lfiqhandler:
+	.long	up_vectorfiq
+
+	.globl	_vector_end
+_vector_end:
+	.end

arch/arm/src/dm320/Make.defs

@@ -0,0 +1,51 @@
+############################################################################
+# dm320/Make.defs
+#
+#   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name Gregory Nutt nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+HEAD_ASRC	= up_head.S
+
+CMN_ASRCS	= up_cache.S up_fullcontextrestore.S up_saveusercontext.S \
+		  up_vectors.S up_vectortab.S
+CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
+		  up_dataabort.c up_delay.c up_exit.c up_idle.c \
+		  up_initialize.c up_initialstate.c up_interruptcontext.c \
+		  up_prefetchabort.c up_releasepending.c up_releasestack.c \
+		  up_reprioritizertr.c up_schedulesigaction.c \
+		  up_sigdeliver.c up_syscall.c up_unblocktask.c \
+		  up_undefinedinsn.c up_usestack.c
+
+CHIP_ASRCS	= dm320_lowputc.S dm320_restart.S
+CHIP_CSRCS	= dm320_allocateheap.c dm320_boot.c dm320_decodeirq.c \
+		  dm320_irq.c dm320_serial.c dm320_timerisr.c
+

arch/arm/src/dm320/chip.h

@@ -0,0 +1,57 @@
+/************************************************************************************
+ * dm320/chip.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __DM320_CHIP_H
+#define __DM320_CHIP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include "dm320_memorymap.h"
+#include "dm320_uart.h"
+#include "dm320_timer.h"
+#include "dm320_intc.h"
+#include "dm320_gio.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#endif  /* __DM320_CHIP_H */

arch/arm/src/dm320/dm320_allocateheap.c

@@ -0,0 +1,79 @@
+/************************************************************
+ * dm320/dm320_allocateheap.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include "up_arch.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Private Definitions
+ ************************************************************/
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/************************************************************
+ * Private Functions
+ ************************************************************/
+
+/************************************************************
+ * Public Functions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_allocate_heap
+ *
+ * Description:
+ *   The heap may be statically allocated by
+ *   defining CONFIG_HEAP_BASE and CONFIG_HEAP_SIZE.  If these
+ *   are not defined, then this function will be called to
+ *   dynamically set aside the heap region.
+ *
+ ************************************************************/
+
+void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
+{
+  up_ledon(LED_HEAPALLOCATE);
+  *heap_start = (FAR void*)g_heapbase;
+  *heap_size  = (DM320_SDRAM_VADDR + CONFIG_DRAM_SIZE) - g_heapbase;
+}

arch/arm/src/dm320/dm320_boot.c

@@ -0,0 +1,227 @@
+/************************************************************************************
+ * dm320/dm320_boot.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "up_internal.h"
+#include "up_arch.h"
+
+/************************************************************************************
+ * Private Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Private Types
+ ************************************************************************************/
+
+struct section_mapping_s
+{
+  uint32 physbase;   /* Physical address of the region to be mapped */
+  uint32 virtbase;   /* Virtual address of the region to be mapped */
+  uint32 mmuflags;   /* MMU settings for the region (e.g., cache-able) */
+  uint32 nsections;  /* Number of mappings in the region */
+};
+
+/************************************************************************************
+ * Public Variables
+ ************************************************************************************/
+
+extern uint32 _vector_start; /* Beginning of vector block */
+extern uint32 _vector_end;   /* End+1 of vector block */
+
+/************************************************************************************
+ * Private Variables
+ ************************************************************************************/
+
+static const struct section_mapping_s section_mapping[] =
+{
+  { DM320_PERIPHERALS_PSECTION, DM320_PERIPHERALS_VSECTION, 
+    DM320_PERIPHERALS_MMUFLAGS, DM320_PERIPHERALS_NSECTIONS},
+  { DM320_FLASH_PSECTION,       DM320_FLASH_VSECTION, 
+    DM320_FLASH_MMUFLAGS,       DM320_FLASH_NSECTIONS},
+  { DM320_CFI_PSECTION,         DM320_CFI_VSECTION, 
+    DM320_CFI_MMUFLAGS,         DM320_CFI_NSECTIONS},
+  { DM320_SSFDC_PSECTION,       DM320_SSFDC_VSECTION, 
+    DM320_SSFDC_MMUFLAGS,       DM320_SSFDC_NSECTIONS},
+  { DM320_CE1_PSECTION,         DM320_CE1_VSECTION, 
+    DM320_CE1_MMUFLAGS,         DM320_CE1_NSECTIONS},
+  { DM320_CE2_PSECTION,         DM320_CE2_VSECTION, 
+    DM320_CE2_MMUFLAGS,         DM320_CE2_NSECTIONS},
+  { DM320_VLYNQ_PSECTION,       DM320_VLYNQ_VSECTION, 
+    DM320_VLYNQ_MMUFLAGS,       DM320_VLYNQ_NSECTIONS},
+  { DM320_USBOTG_PSECTION,      DM320_USBOTG_VSECTION, 
+    DM320_USBOTG_MMUFLAGS,      DM320_USBOTG_NSECTIONS}
+};
+#define NMAPPINGS (sizeof(section_mapping) / sizeof(struct section_mapping_s))
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: up_setlevel1entry
+ ************************************************************************************/
+
+static inline void up_setlevel1entry(uint32 paddr, uint32 vaddr, uint32 mmuflags)
+{
+  uint32 *pgtable = (uint32*)PGTABLE_BASE_VADDR;
+  uint32  index   = vaddr >> 20;
+
+  /* Save the page table entry */
+
+  pgtable[index]  = (paddr | mmuflags);
+}
+
+/************************************************************************************
+ * Name: up_setlevel2coarseentry
+ ************************************************************************************/
+
+static inline void up_setlevel2coarseentry(uint32 ctabvaddr, uint32 paddr,
+                                           uint32 vaddr, uint32 mmuflags)
+{
+  uint32 *ctable  = (uint32*)ctabvaddr;
+  uint32  index;
+
+  /* The coarse table divides a 1Mb address space up into 256 entries, each
+   * corresponding to 4Kb of address space.  The coarse page table index is
+   * related to the offset from the beginning of 1Mb region.
+   */
+
+  index = (vaddr & 0x000ff000) >> 12;
+
+  /* Save the coarse table entry */
+
+  ctable[index] = (paddr | mmuflags);
+}
+
+/************************************************************************************
+ * Name: up_setupmappings
+ ************************************************************************************/
+
+static void up_setupmappings(void)
+{
+  int i, j;
+
+  for (i = 0; i < NMAPPINGS; i++)
+    {
+      uint32 sect_paddr = section_mapping[i].physbase;
+      uint32 sect_vaddr = section_mapping[i].virtbase;
+      uint32 mmuflags   = section_mapping[i].mmuflags;
+
+      for (j = 0; j < section_mapping[i].nsections; j++)
+        {
+          up_setlevel1entry(sect_paddr, sect_vaddr, mmuflags);
+          sect_paddr += SECTION_SIZE;
+          sect_vaddr += SECTION_SIZE;
+        }
+    }
+}
+
+/************************************************************************************
+ * Name: up_vectormapping
+ ************************************************************************************/
+
+static void up_vectormapping(void)
+{
+  uint32 vector_paddr = DM320_IRAM_PADDR;
+  uint32 vector_vaddr = DM320_VECTOR_VADDR;
+  uint32 end_paddr    = vector_paddr + DM320_IRAM_SIZE;
+
+  /* We want to keep our interrupt vectors and interrupt-related logic in zero-wait
+   * state internal RAM (IRAM).  The DM320 has 16Kb of IRAM positioned at physical
+   * address 0x0000:0000; we need to map this to 0xffff:0000.
+   */
+
+  while (vector_paddr < end_paddr)
+    {
+      up_setlevel2coarseentry(PGTABLE_COARSE_BASE_VADDR,
+                                  vector_paddr,
+                                  vector_vaddr,
+                                  MMU_L2_VECTORFLAGS);
+      vector_paddr += 4096;
+      vector_vaddr += 4096;
+    }
+
+  /* Now set the level 1 descriptor to refer to the level 2 coarse page table. */
+
+  up_setlevel1entry(PGTABLE_COARSE_BASE_PADDR,
+                        DM320_VECTOR_VCOARSE,
+                        MMU_L1_VECTORFLAGS);
+}
+
+/************************************************************************************
+ * Name: up_copyvectorblock
+ ************************************************************************************/
+
+static void up_copyvectorblock(void)
+{
+  uint32 *src  = (uint32*)&_vector_start;
+  uint32 *end  = (uint32*)&_vector_end;
+  uint32 *dest = (uint32*)VECTOR_BASE;
+
+  while (src < end)
+    {
+      *dest++ = *src++;
+    }
+}
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+void up_boot(void)
+{
+  /* __start provided the basic MMU mappings for SDRAM.  Now provide mappings for all
+   * IO regions (Including the vector region).
+   */
+
+  up_setupmappings();
+
+  /* Provide a special mapping for the IRAM interrupt vector positioned in high
+   * memory.
+   */
+
+  up_vectormapping();
+
+  /* Setup up vector block.  _vector_start and _vector_end are exported from
+   * up_vector.S
+   */
+
+  up_copyvectorblock();
+}

arch/arm/src/dm320/dm320_decodeirq.c

@@ -0,0 +1,119 @@
+/********************************************************************************
+ * dm320/dm320_decodeirq.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************/
+
+/********************************************************************************
+ * Included Files
+ ********************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <assert.h>
+#include <debug.h>
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+
+/********************************************************************************
+ * Definitions
+ ********************************************************************************/
+
+/********************************************************************************
+ * Public Data
+ ********************************************************************************/
+
+/********************************************************************************
+ * Private Data
+ ********************************************************************************/
+
+/********************************************************************************
+ * Private Functions
+ ********************************************************************************/
+
+/********************************************************************************
+ * Public Funtions
+ ********************************************************************************/
+
+void up_decodeirq(uint32* regs)
+{
+#ifdef CONFIG_SUPPRESS_INTERRUPTS
+  lib_lowprintf("Unexpected IRQ\n");
+  current_regs = regs;
+  PANIC(OSERR_ERREXCEPTION);
+#else
+  /* Decode the interrupt.  First, fetch the interrupt id register. */
+
+  uint16 irqentry = getreg16(DM320_INTC_IRQENTRY0);
+
+  /* The irqentry value is an offset into a table.  Zero means no interrupt. */
+
+  if (irqentry != 0)
+    {
+      /* If non-zero, then we can map the table offset into an IRQ number */
+
+      int irq = (irqentry >> 2) - 1;
+
+      /* Verify that the resulting IRQ number is valie */
+
+      if ((unsigned)irq < NR_IRQS)
+        {
+          /* Mask and acknowledge the interrupt */
+
+          up_maskack_irq(irq);
+
+          /* Current regs non-zero indicates that we are processing an interrupt;
+           * current_regs is also used to manage interrupt level context switches.
+           */
+
+          current_regs = regs;
+
+          /* Deliver the IRQ */
+
+          irq_dispatch(irq, regs);
+
+          /* Indicate that we are no long in an interrupt handler */
+
+          current_regs = NULL;
+
+          /* Unmask the last interrupt (global interrupts are still
+           * disabled.
+           */
+
+          up_enable_irq(irq);
+        }
+    }
+#endif
+}

arch/arm/src/dm320/dm320_gio.h

@@ -0,0 +1,175 @@
+/************************************************************************************
+ * dm320/dm320_gio.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __DM320_DM320GIO_H
+#define __DM320_DM320GIO_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+# include <sys/types.h>
+#endif
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* General I/O Registers */
+
+#define DM320_GIO_DIR0    (DM320_PERIPHERALS_VADDR + 0x0580) /* GIO Direction Register 0 */
+#define DM320_GIO_DIR1    (DM320_PERIPHERALS_VADDR + 0x0582) /* GIO Direction Register 1 */
+#define DM320_GIO_DIR2    (DM320_PERIPHERALS_VADDR + 0x0584) /* GIO Direction Register 2 */
+#define DM320_GIO_INV0    (DM320_PERIPHERALS_VADDR + 0x0586) /* GIO Inversion Register 0 */
+#define DM320_GIO_INV1    (DM320_PERIPHERALS_VADDR + 0x0588) /* GIO Inversion Register 1 */
+#define DM320_GIO_INV2    (DM320_PERIPHERALS_VADDR + 0x058A) /* GIO Inversion Register 2 */
+#define DM320_GIO_BITSET0 (DM320_PERIPHERALS_VADDR + 0x058C) /* GIO Bit Set Register 0 */
+#define DM320_GIO_BITSET1 (DM320_PERIPHERALS_VADDR + 0x058E) /* GIO Bit Set Register 1 */
+#define DM320_GIO_BITSET2 (DM320_PERIPHERALS_VADDR + 0x0590) /* GIO Bit Set Register 2 */
+#define DM320_GIO_BITCLR0 (DM320_PERIPHERALS_VADDR + 0x0592) /* GIO Bit Clear Register 0 */
+#define DM320_GIO_BITCLR1 (DM320_PERIPHERALS_VADDR + 0x0594) /* GIO Bit Clear Register 1 */
+#define DM320_GIO_BITCLR2 (DM320_PERIPHERALS_VADDR + 0x0596) /* GIO Bit Clear Register 2 */
+#define DM320_GIO_IRQPORT (DM320_PERIPHERALS_VADDR + 0x0598) /* GIO IRQ Port Setting Register */
+#define DM320_GIO_IRQEDGE (DM320_PERIPHERALS_VADDR + 0x059A) /* GIO IRQ Edge Setting Register */
+#define DM320_GIO_CHAT0   (DM320_PERIPHERALS_VADDR + 0x059C) /* GIO Chatter Setting Register 0 */
+#define DM320_GIO_CHAT1   (DM320_PERIPHERALS_VADDR + 0x059E) /* GIO Chatter Setting Register 1 */
+#define DM320_GIO_CHAT2   (DM320_PERIPHERALS_VADDR + 0x05A0) /* GIO Chatter Setting Register 2 */
+#define DM320_GIO_NCHAT   (DM320_PERIPHERALS_VADDR + 0x05A2) /* GIO Chatter Value Register */
+#define DM320_GIO_FSEL0   (DM320_PERIPHERALS_VADDR + 0x05A4) /* GIO Function Select Register 0 */
+#define DM320_GIO_FSEL1   (DM320_PERIPHERALS_VADDR + 0x05A6) /* GIO Function Select Register 1 */
+#define DM320_GIO_FSEL2   (DM320_PERIPHERALS_VADDR + 0x05A8) /* GIO Function Select Register 2 */
+#define DM320_GIO_FSEL3   (DM320_PERIPHERALS_VADDR + 0x05AA) /* GIO Function Select Register 3 */
+
+/* Macros for GIO access */
+
+#define _GIO_READ_REG(pin, reg0, reg1, reg2, bval) \
+  do { \
+    register uint32 _reg; register int _pin; \
+    if ((pin) < 16) { _reg = (reg0); _pin = (pin); } \
+    else if ((pin) < 32) { _reg = (reg1); _pin = ((pin) - 16); } \
+    else { _reg = (reg2); _pin = ((pin) - 32); } \
+    bval = ((getreg16(_reg) & (1<<_pin)) != 0); \
+  }
+
+#define _GIO_SET_REG(pin, reg0, reg1, reg2) \
+  do { \
+    register uint32 _reg; register int _pin; \
+    if ((pin) < 16) { _reg = (reg0); _pin = (pin); } \
+    else if ((pin) < 32) { _reg = (reg1); _pin = ((pin) - 16); } \
+    else { _reg = (reg2); _pin = ((pin) - 32); } \
+    putreg16((getreg16(_reg) | (1 << _pin)), _reg)); \
+  } while (0)
+
+#define _GIO_CLEAR_REG(pin, reg0, reg1, reg2) \
+  do { \
+    register uint32 _reg; register int _pin; \
+    if ((pin) < 16) { _reg = (reg0); _pin = (pin); } \
+    else if ((pin) < 32) { _reg = (reg1); _pin = ((pin) - 16); } \
+    else { _reg = (reg2); _pin = ((pin) - 32); } \
+    putreg16((getreg16(_reg) & ~(1 << _pin)), _reg)); \
+  } while (0)
+
+/* Select GIO input or output */
+
+#define GIO_INPUT(pin) \
+  _GIO_SET_REG((pin), DM320_GIO_DIR0, DM320_GIO_DIR1, DM320_GIO_DIR2)
+#define GIO_OUTPUT(pin) \
+  _GIO_CLEAR_REG((pin), DM320_GIO_DIR0, DM320_GIO_DIR1, DM320_GIO_DIR2)
+
+/* Select inverted or non-inverted GIO */
+
+#define GIO_INVERTED(pin) \
+  _GIO_SET_REG((pin), DM320_GIO_INV0, DM320_GIO_INV1, DM320_GIO_INV2)
+#define GIO_NONINVERTED(pin) \
+  _GIO_CLEAR_REG((pin), DM320_GIO_INV0, DM320_GIO_INV1, DM320_GIO_INV2)
+
+/* Set and clear outputs */
+
+#define GIO_SET_OUTPUT(pin) \
+  _GIO_SET_REG((pin), DM320_GIO_BITSET0, DM320_GIO_BITSET1, DM320_GIO_BITSET2)
+#define GIO_CLEAR_OUTPUT(pin) \
+ _GIO_SET_REG((pin), DM320_GIO_BITCLR0, DM320_GIO_BITCLR1, DM320_GIO_BITCLR2)
+
+/* Read input */
+
+#define GIO_READ_INPUT(pin, bval) \
+  _GIO_READ_REG((pin), DM320_GIO_BITSET0, DM320_GIO_BITSET1, DM320_GIO_BITSET2, (bval))
+
+/* Configure GIO pins */
+
+#define _GIO_SET_CONFIG(reg, sh, val) \
+    putreg16(((getreg16(reg) & ~(3 << sh)) | (val << sh)), (reg))
+
+#define GIO_CONFIGURE(pin, val) \
+  do {\
+    if ((pin) < 10) _GIO_SET_CONFIG(DM320_GIO_FSEL0, 0, (val)); \
+    else if ((pin) < 17) _GIO_SET_CONFIG(DM320_GIO_FSEL0, 2*((pin)-9), (val)); \
+    else if ((pin) < 25) _GIO_SET_CONFIG(DM320_GIO_FSEL1, 2*((pin)-17), (val)); \
+    else if ((pin) < 33) _GIO_SET_CONFIG(DM320_GIO_FSEL2, 2*((pin)-25), (val)); \
+    else _GIO_SET_CONFIG(DM320_GIO_FSEL3, 2*((pin)-33), (val)); \
+  }
+
+/* Configure GIO interrupts (pins 1-15) */
+
+#define GIO_INTERRUPT(pin) \
+  if (pin < 16) putreg16((getreg16(DM320_GIO_IRQPORT) | (1<<(pin))), DM320_GIO_IRQPORT)
+#define GIO_NONINTERRUPT(pin) \
+  if (pin < 16) putreg16((getreg16(DM320_GIO_IRQPORT) & ~(1<<(pin))), DM320_GIO_IRQPORT)
+#define GIO_FALLINGEDGE(pin) \
+  if (pin < 16) { \
+    putreg16((getreg16(DM320_GIO_IRQEDGE) & ~(1<<(pin))), DM320_GIO_IRQEDGE) \
+    putreg16((getreg16(DM320_GIO_INV0) & ~(1<<(pin))), DM320_GIO_INV0); \
+  }
+#define GIO_RISINGEDGE(pin) \
+  if (pin < 16) { \
+    putreg16((getreg16(DM320_GIO_IRQEDGE) & ~(1<<(pin))), DM320_GIO_IRQEDGE); \
+    putreg16((getreg16(DM320_GIO_INV0) | (1<<(pin))), DM320_GIO_INV0); \
+  }
+#define GIO_BOTHEDGES(pin) \
+  if (pin < 16) { \
+    putreg16((getreg16(DM320_GIO_IRQEDGE) | (1<<(pin))), DM320_GIO_IRQEDGE); \
+    putreg16((getreg16(DM320_GIO_INV0) & ~(1<<(pin))), DM320_GIO_INV0); \
+  }
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#endif
+
+#endif  /* __DM320_DM320_GIO_H */

arch/arm/src/dm320/dm320_intc.h

@@ -0,0 +1,105 @@
+/************************************************************************************
+ * dm320/dm320_intc.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __DM320_DM320_INTC_H
+#define __DM320_DM320_INTC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+# include <sys/types.h>
+#endif
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Interrupt Controller Registers */
+
+#define DM320_INTC_FIQ0       (DM320_PERIPHERALS_VADDR + 0x0500) /* FIQ Interrupt Flag Register #0 */
+#define DM320_INTC_FIQ1       (DM320_PERIPHERALS_VADDR + 0x0502) /* FIQ Interrupt Flag Register #1 */
+#define DM320_INTC_FIQ2       (DM320_PERIPHERALS_VADDR + 0x0504) /* FIQ Interrupt Flag Register #2 */
+#define DM320_INTC_IRQ0       (DM320_PERIPHERALS_VADDR + 0x0508) /* IRQ Interrupt Flag Register #0 */
+#define DM320_INTC_IRQ1       (DM320_PERIPHERALS_VADDR + 0x050A) /* IRQ Interrupt Flag Register #1 */
+#define DM320_INTC_IRQ2       (DM320_PERIPHERALS_VADDR + 0x050C) /* IRQ Interrupt Flag Register #2 */
+#define DM320_INTC_FIQENTRY0  (DM320_PERIPHERALS_VADDR + 0x0510) /* FIQ Entry Address Register #0 */
+#define DM320_INTC_FIQENTRY1  (DM320_PERIPHERALS_VADDR + 0x0512) /* FIQ Entry Address Register #1 */
+#define DM320_INTC_FIQENTLCK0 (DM320_PERIPHERALS_VADDR + 0x0514) /* FIQ Lock Entry Address Register #1 */
+#define DM320_INTC_FIQENTLCK1 (DM320_PERIPHERALS_VADDR + 0x0516) /* FIQ Lock Entry Address Register #1 */
+#define DM320_INTC_IRQENTRY0  (DM320_PERIPHERALS_VADDR + 0x0518) /* IRQ Entry Address Register #0 */
+#define DM320_INTC_IRQENTRY1  (DM320_PERIPHERALS_VADDR + 0x051A) /* IRQ Entry Address Register #1 */
+#define DM320_INTC_IRQENTLCK0 (DM320_PERIPHERALS_VADDR + 0x051C) /* IRQ Lock Entry Address Register #1 */
+#define DM320_INTC_IRQENTLCK1 (DM320_PERIPHERALS_VADDR + 0x051E) /* Lock Entry Address Register #1 */
+#define DM320_INTC_FISEL0     (DM320_PERIPHERALS_VADDR + 0x0520) /* FIQ select register #0 */
+#define DM320_INTC_FISEL1     (DM320_PERIPHERALS_VADDR + 0x0522) /* FIQ select register #1 */
+#define DM320_INTC_FISEL2     (DM320_PERIPHERALS_VADDR + 0x0524) /* FIQ select register #2 */
+#define DM320_INTC_EINT0      (DM320_PERIPHERALS_VADDR + 0x0528) /* Interrupt Enable Register #0 */
+#define DM320_INTC_EINT1      (DM320_PERIPHERALS_VADDR + 0x052A) /* Interrupt Enable Register #1 */
+#define DM320_INTC_EINT2      (DM320_PERIPHERALS_VADDR + 0x052C) /* Interrupt Enable Register #2 */
+#define DM320_INTC_INTRAW     (DM320_PERIPHERALS_VADDR + 0x0530) /* Interrupt Raw Register */
+#define DM320_INTC_EABASE0    (DM320_PERIPHERALS_VADDR + 0x0538) /* Entry Table Base Address Register #0 */
+#define DM320_INTC_EABASE1    (DM320_PERIPHERALS_VADDR + 0x053A) /* Entry Table Base Address Register #1 */
+#define DM320_INTC_INTPRI00   (DM320_PERIPHERALS_VADDR + 0x0540) /* Interrupt Priority Register #0 */
+#define DM320_INTC_INTPRI01   (DM320_PERIPHERALS_VADDR + 0x0542) /* Interrupt Priority Register #1 */
+#define DM320_INTC_INTPRI02   (DM320_PERIPHERALS_VADDR + 0x0544) /* Interrupt Priority Register #2 */
+#define DM320_INTC_INTPRI03   (DM320_PERIPHERALS_VADDR + 0x0546) /* Interrupt Priority Register #3 */
+#define DM320_INTC_INTPRI04   (DM320_PERIPHERALS_VADDR + 0x0548) /* Interrupt Priority Register #4 */
+#define DM320_INTC_INTPRI05   (DM320_PERIPHERALS_VADDR + 0x054A) /* Interrupt Priority Register #5 */
+#define DM320_INTC_INTPRI06   (DM320_PERIPHERALS_VADDR + 0x054C) /* Interrupt Priority Register #6 */
+#define DM320_INTC_INTPRI07   (DM320_PERIPHERALS_VADDR + 0x054E) /* Interrupt Priority Register #7 */
+#define DM320_INTC_INTPRI08   (DM320_PERIPHERALS_VADDR + 0x0550) /* Interrupt Priority Register #8 */
+#define DM320_INTC_INTPRI09   (DM320_PERIPHERALS_VADDR + 0x0552) /* Interrupt Priority Register #9 */
+#define DM320_INTC_INTPRI10   (DM320_PERIPHERALS_VADDR + 0x0554) /* Interrupt Priority Register #10 */
+#define DM320_INTC_INTPRI11   (DM320_PERIPHERALS_VADDR + 0x0556) /* Interrupt Priority Register #11 */
+#define DM320_INTC_INTPRI12   (DM320_PERIPHERALS_VADDR + 0x0558) /* Interrupt Priority Register #12 */
+#define DM320_INTC_INTPRI13   (DM320_PERIPHERALS_VADDR + 0x055A) /* Interrupt Priority Register #13 */
+#define DM320_INTC_INTPRI14   (DM320_PERIPHERALS_VADDR + 0x055C) /* Interrupt Priority Register #14 */
+#define DM320_INTC_INTPRI15   (DM320_PERIPHERALS_VADDR + 0x055E) /* Interrupt Priority Register #15 */
+#define DM320_INTC_INTPRI16   (DM320_PERIPHERALS_VADDR + 0x0560) /* Interrupt Priority Register #16 */
+#define DM320_INTC_INTPRI17   (DM320_PERIPHERALS_VADDR + 0x0562) /* Interrupt Priority Register #17 */
+#define DM320_INTC_INTPRI18   (DM320_PERIPHERALS_VADDR + 0x0564) /* Interrupt Priority Register #18 */
+#define DM320_INTC_INTPRI19   (DM320_PERIPHERALS_VADDR + 0x0566) /* Interrupt Priority Register #19 */
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#endif
+
+#endif  /* __DM320_DM320_INTC_H */

arch/arm/src/dm320/dm320_irq.c

@@ -0,0 +1,245 @@
+/************************************************************
+ * dm320/dm320_irq.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <nuttx/irq.h>
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/************************************************************
+ * Public Data
+ ************************************************************/
+
+uint32 *current_regs;
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/* The value of _vflashstart is defined in ld.script.  It
+ * could be hard-coded because we know that correct IRAM
+ * area is 0xffc00000.
+ */
+
+extern int _svectors; /* Type does not matter */
+
+/************************************************************
+ * Private Functions
+ ************************************************************/
+
+/************************************************************
+ * Public Funtions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_irqinitialize
+ ************************************************************/
+
+void up_irqinitialize(void)
+{
+  /* Clear, disable and configure all interrupts. */
+
+  putreg16(0, DM320_INTC_EINT0);      /* Mask all IRQs/FIQs */
+  putreg16(0, DM320_INTC_EINT1);
+  putreg16(0, DM320_INTC_EINT2);
+
+  putreg16(0, DM320_INTC_INTRAW);     /* No masked interrupts in status */
+
+  putreg16(0, DM320_INTC_FISEL0);     /* No FIQs */
+  putreg16(0, DM320_INTC_FISEL1);
+  putreg16(0, DM320_INTC_FISEL2);
+
+  putreg16(0xffff, DM320_INTC_FIQ0);  /* Clear all pending FIQs */
+  putreg16(0xffff, DM320_INTC_FIQ1);
+  putreg16(0xffff, DM320_INTC_FIQ2);
+
+  putreg16(0xffff, DM320_INTC_IRQ0);  /* Clear all pending IRQs */
+  putreg16(0xffff, DM320_INTC_IRQ1);
+  putreg16(0xffff, DM320_INTC_IRQ2);
+
+ /* Make sure that the base addresses are zero and that
+  * the table increment is 4 bytes.
+  */
+
+  putreg16(0, DM320_INTC_EABASE0);
+  putreg16(0, DM320_INTC_EABASE1);
+
+  /* currents_regs is non-NULL only while processing an interrupt */
+
+  current_regs = NULL;
+
+  /* And finally, enable interrupts */
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+  irqrestore(SVC_MODE | PSR_F_BIT);
+#endif
+}
+
+/************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ *   Disable the IRQ specified by 'irq'
+ *
+ ************************************************************/
+
+void up_disable_irq(int irq)
+{
+  /* Disable the interrupt by clearing the corresponding bit in
+   * the IRQ enable register.
+   */
+
+  if (irq < 16)
+    {
+      /* IRQs0-15 are controlled by the IRQ0 enable register
+       * Clear the associated bit to disable the interrupt
+       */
+
+      putreg16((getreg16(DM320_INTC_EINT0) & ~(1 << irq)), DM320_INTC_EINT0);
+    }
+  else if (irq < 32)
+    {
+      /* IRQs16-31 are controlled by the IRQ1 enable register
+       * Clear the associated bit to disable the interrupt
+       */
+
+      putreg16((getreg16(DM320_INTC_EINT1) & ~(1 << (irq-16))), DM320_INTC_EINT1);
+    }
+  else
+    {
+      /* IRQs32- are controlled by the IRQ2 enable register
+       * Clear the associated bit to disable the interrupt
+       */
+
+      putreg16((getreg16(DM320_INTC_EINT2) & ~(1 << (irq-32))), DM320_INTC_EINT2);
+    }
+}
+
+/************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ *   Enable the IRQ specified by 'irq'
+ *
+ ************************************************************/
+
+void up_enable_irq(int irq)
+{
+  /* Enable the interrupt by setting the corresponding bit in
+   * the IRQ enable register.
+   */
+
+  if (irq < 16)
+    {
+      /* IRQs0-15 are controlled by the IRQ0 enable register
+       * Set the associated bit to enable the interrupt
+       */
+
+      putreg16((getreg16(DM320_INTC_EINT0) | (1 << irq)), DM320_INTC_EINT0);
+    }
+  else if (irq < 32)
+    {
+      /* IRQs16-31 are controlled by the IRQ1 enable register
+       * Set the associated bit to enable the interrupt
+       */
+
+      putreg16((getreg16(DM320_INTC_EINT1) | (1 << (irq-16))), DM320_INTC_EINT1);
+    }
+  else
+    {
+      /* IRQs32- are controlled by the IRQ2 enable register
+       * Set the associated bit to enable the interrupt
+       */
+
+      putreg16((getreg16(DM320_INTC_EINT2) | (1 << (irq-32))), DM320_INTC_EINT2);
+    }
+}
+
+/************************************************************
+ * Name: up_maskack_irq
+ *
+ * Description:
+ *   Mask the IRQ and acknowledge it
+ *
+ ************************************************************/
+
+void up_maskack_irq(int irq)
+{
+  /* Disable the interrupt by clearing the corresponding bit in
+   * the IRQ enable register.  And acknowlege it by setting the
+   * corresponding bit in the IRQ status register.
+   */
+
+  if (irq < 16)
+    {
+      /* IRQs0-15 are controlled by the IRQ0 enable register
+       * Clear the associated enable bit to disable the interrupt
+       * Set the associated status bit to clear the interrupt
+       */
+
+      putreg16((getreg16(DM320_INTC_EINT0) & ~(1<< irq)), DM320_INTC_EINT0);
+      putreg16((1 << irq), DM320_INTC_IRQ0);
+    }
+  else if (irq < 32)
+    {
+      /* IRQs16-31 are controlled by the IRQ1 enable register
+       * Clear the associated enable bit to disable the interrupt
+       * Set the associated status bit to clear the interrupt
+       */
+
+      putreg16((getreg16(DM320_INTC_EINT1) & ~(1<< (irq-16))), DM320_INTC_EINT1);
+      putreg16((1 << (irq-16)), DM320_INTC_IRQ1);
+    }
+  else
+    {
+      /* IRQs32- are controlled by the IRQ2 enable register
+       * Clear the associated enable bit to disable the interrupt
+       * Set the associated status bit to clear the interrupt
+       */
+
+      putreg16((getreg16(DM320_INTC_EINT2) & ~(1<< (irq-32))), DM320_INTC_EINT2);
+      putreg16((1 << (irq-32)), DM320_INTC_IRQ2);
+    }
+}

arch/arm/src/dm320/dm320_lowputc.S

@@ -0,0 +1,127 @@
+/**************************************************************************
+ * dm320/dm320_lowputc.S
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ **************************************************************************/
+
+/**************************************************************************
+ * Included Files
+ **************************************************************************/
+
+#include <nuttx/config.h>
+#include "up_internal.h"
+#include "up_arch.h"
+
+/**************************************************************************
+ * Private Definitions
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Types
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Function Prototypes
+ **************************************************************************/
+
+/**************************************************************************
+ * Global Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Public Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Name: up_lowputc
+ **************************************************************************/
+
+/* This assembly language version has the advantage that it can does not
+ * require a C stack and uses only r0-r1.  Hence it can be used during
+ * early boot phases.
+ */
+
+	.text
+	.global	up_lowputc
+	.type	up_lowputc, function
+up_lowputc:
+	/* On entry, r0 holds the character to be printed */
+
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+	ldr	r2, =DM320_UART0_REGISTER_BASE	/* r2=UART0 base */
+#else
+	ldr	r2, =DM320_UART1_REGISTER_BASE	/* r2=UART1 base */
+#endif
+
+	/* Poll the TX fifo trigger level bit of the UART_SSR
+	 * register.  When the bit is non-zero, the TX FIFO is no
+	 * longer full
+	 */
+
+1:	ldrh	r1, [r2, #UART_SR]
+	tst	r1, #UART_SR_TFTI
+	beq	1b
+
+	/* Send the character by writing it into the UART_DTRR
+	 * register.
+	 */
+
+	strh	r0, [r2, #UART_DTRR]
+
+	/* Wait for the tranmsit regiser to be emptied. This is
+	 * detemined when TX register empty bit of the SR is zero.
+	 */
+
+2:	ldrh	r1, [r2, #UART_SR]
+	tst	r1, #UART_SR_TREF
+	bne	2b
+
+	/* If the character that we just sent was a linefeed,
+	 * then send a carriage return as well.
+	 */
+
+	teq     r0, #'\n'
+	moveq   r0, #'\r'
+	beq     1b
+
+	/* And return */
+
+	mov     pc, lr
+

arch/arm/src/dm320/dm320_memorymap.h

@@ -0,0 +1,238 @@
+/************************************************************************************
+ * dm320/dm320_memorymap.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __DM320_MEMORYMAP_H
+#define __DM320_MEMORYMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+# include <sys/types.h>
+#endif
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Mapped base of all registers *****************************************************/
+
+/* DM320 Physical Memory Map, where:
+ *
+ *   CW = cachable with write buffering
+ *   -W = Write buffering only
+ *   -- = Neither
+ *
+ * The DM320 only has a single control line for external peripherals.
+ * To support more than one peripheral, most hardware will use an 
+ * external memory decode logic, so that physical memory regions is
+ * in the hardware specific files dm320-*.h
+ */
+
+#if CONFIG_DRAM_START != 0x01000000
+# error "Invalid setting for CONFIG_DRAM_START
+#endif
+
+/* Section/Region Name             Phys Address    Size  TLB Enty        CW */
+#define DM320_PERIPHERALS_PSECTION   0x00000000 /*   1Mb   1 section     -- */
+#define   DM320_IRAM_PADDR           0x00000000 /*  16Kb   1 large page  CW */
+#define   DM320_PERIPHERALS_PADDR    0x00030000 /*   4Kb   1 small pages -- */
+#define   DM320_DSP_ONCHIP_RAM_PADDR 0x00040000 /* 128Kb   1 large page  -- */
+#define   DM320_AHB_PADDR            0x00060000 /*   4Kb   1 small page  -- */
+#define   DM320_COPRO_SUB_PADDR      0x00080000 /* 128Kb                 -- */
+#define DM320_FLASH_PSECTION         0x00100000 /*  16Mb  many sections  -- */
+#define   DM320_EXT_MEM_PADDR        0x00100000 /*  16Mb flash           -- */
+#define DM320_SDRAM_PSECTION         0x01000000 /* 496Mb  many section   -- */
+#define   DM320_SDRAM_PADDR          0x01000000 /* 496Mb  many sections  CW */
+#define DM320_CFI_PSECTION           0x40000000 /*  16Mb  16 sections    -- */
+#define   DM320_CFI_PADDR            0x40000000 /*  16Mb  16 sections    -- */
+#define DM320_SSFDC_PSECTION         0x48000000 /*  16Mb  16 sections    -- */
+#define   DM320_SSFDC_PADDR          0x48000000 /*  16Mb  16 sections    -- */
+#define DM320_CE1_PSECTION           0x50000000 /*  16Mb  16 sections    -- */
+#define   DM320_CE1_PADDR            0x50000000 /*  16Mb  16 sections    -- */
+#define DM320_CE2_PSECTION           0x60000000 /*  16Mb  16 sections    -- */
+#define   DM320_CE2_PADDR            0x60000000 /*  16Mb  16 sections    -- */
+#define DM320_VLYNQ_PSECTION         0x70000000 /*  64MB  64 sections    -- */
+#define   DM320_VLYNQ_PADDR          0x70000000 /*  64MB  64 sections    -- */
+#define DM320_USBOTG_PSECTION        0x80000000 /*   1Mb   1 section     -- */
+#define   DM320_USBOTG_PADDR         0x80000000 /*   1Kb   1 small page  -- */
+
+/* Sizes of sections/regions */
+
+/* Section / Region Name             Size */
+#define DM320_PERIPHERALS_NSECTIONS  1          /*   1Mb   1 section     -- */
+#define   DM320_IRAM_SIZE            (16*1024)
+#define   DM320_PERIPHERALS_SIZE     (4*1024)
+#define   DM320_DSP_ONCHIP_RAM_SIZE  (128*1024)
+#define   DM320_AHB_SIZE             (4*1024)
+#define   DM320_COPRO_SUB_SIZE       (128*1024)
+#define DM320_FLASH_NSECTIONS        16         /*  16Mb  16 sections    -- */
+#define   DM320_EXT_MEM_SIZE         (16*1024*1024)
+#define DM320_CFI_NSECTIONS          16         /*  16Mb  16 sections    -- */
+#define   DM320_CFI_SIZE             (16*1024*1024)
+#define DM320_SSFDC_NSECTIONS        16         /*  16Mb  16 sections    -- */
+#define   DM320_SSFDC_SIZE           (16*1024*1024) 
+#define DM320_CE1_NSECTIONS          16         /*  16Mb  16 sections    -- */
+#define   DM320_CE1_SIZE             (16*1024*1024)
+#define DM320_CE2_NSECTIONS          16         /*  16Mb  16 sections    -- */
+#define   DM320_CE2_SIZE             (16*1024*1024)
+#define DM320_VLYNQ_NSECTIONS        64         /*  64MB  64 sections    -- */
+#define   DM320_VLYNQ_SIZE           (64*1024*1024)
+#define DM320_USBOTG_NSECTIONS       1          /*   1Mb   1 section     -- */
+#define   DM320_USBOTG_SIZE          (1024)
+
+/* DM320 Virtual Memory Map */
+
+#if CONFIG_DRAM_VSTART != 0x00000000
+# error "Invalid setting for CONFIG_DRAM_VSTART
+#endif
+
+/* Section/Region Name               Virt Address  End        Size  CW */
+#define DM320_SDRAM_VSECTION         0x00000000 /* 0x1effffff 496Mb CW */
+#define   DM320_SDRAM_VADDR          0x00000000 /* 0x1effffff 496Mb CW */
+                                  /* 0x1f000000    0xdfffffff UNMAPPED */
+#define DM320_FLASH_VSECTION         0xc0000000 /* 0xc0ffffff  16Mb -- */
+#define   DM320_EXT_MEM_VADDR        0xc0000000 /* 0xc0ffffff  16Mb -- */
+#define DM320_CFI_VSECTION           0xc4000000 /* 0xc4ffffff  16Mb -- */
+#define   DM320_CFI_VADDR            0xc4000000 /* 0xc4ffffff  16Mb -- */
+#define DM320_SSFDC_VSECTION         0xc8000000 /* 0xc8ffffff  16Mb -- */
+#define   DM320_SSFDC_VADDR          0xc8000000 /* 0xc8ffffff  16Mb -- */
+#define DM320_CE1_VSECTION           0xcc000000 /* 0xccffffff  16Mb -- */
+#define   DM320_CE1_VADDR            0xcc000000 /* 0xccffffff  16Mb -- */
+#define DM320_CE2_VSECTION           0xd0000000 /* 0xd0ffffff  16Mb -- */
+#define   DM320_CE2_VADDR            0xd0000000 /* 0xd0ffffff  16Mb -- */
+#define DM320_USBOTG_VSECTION        0xd4000000 /* 0xd40fffff   1Mb -- */
+#define   DM320_USBOTG_VADDR         0xd4000000 /* 0xd40003ff   1Kb -- */
+#define DM320_VLYNQ_VSECTION         0xe0000000 /* 0xefffffff  64Mb -- */
+#define   DM320_VLYNQ_VADDR          0xe0000000 /* 0xefffffff  64Mb -- */
+#define DM320_PERIPHERALS_VSECTION   0xf0000000 /* 0xf00fffff   1Mb -- */
+#define   DM320_IRAM_VADDR           0xf0000000 /* 0xf0003fff  16Kb -- */
+#define   DM320_PERIPHERALS_VADDR    0xf0030000 /* 0xf0030fff   4Kb -- */
+#define   DM320_DSP_ONCHIP_RAM_VADDR 0xf0040000 /* 0xf005ffff 128Kb -- */
+#define   DM320_AHB_VADDR            0xf0060000 /* 0xf0060fff   4Kb -- */
+#define   DM320_COPRO_SUB_VADDR      0xf0080000 /* 0xf009ffff 128Kb -- */
+                                  /* 0xf0100000    0xffefffff UNMAPPED */
+#define DM320_VECTOR_VCOARSE         0xfff00000 /* 0xffffffff   1Mb -- */
+                                  /* 0xfff00000    0xfffeffff UNMAPPED */
+#define   DM320_VECTOR_VADDR         0xffff0000 /* 0xffff3fff  16Kb -- */
+                                  /* 0xffff4000    0xffffffff UNMAPPED */
+
+/* The NuttX entry point starts at an offset from the virtual beginning of DRAM.
+ * This offset reserves space for the MMU page cache.
+ */
+
+#define NUTTX_START_VADDR            (DM320_SDRAM_VADDR+PGTABLE_SIZE)
+
+/* Section MMU Flags                 Flags              CW */
+#define DM320_FLASH_MMUFLAGS         MMU_IOFLAGS     /* -- */
+#define DM320_CFI_MMUFLAGS           MMU_IOFLAGS     /* -- */
+#define DM320_SSFDC_MMUFLAGS         MMU_IOFLAGS     /* -- */
+#define DM320_CE1_MMUFLAGS           MMU_IOFLAGS     /* -- */
+#define DM320_CE2_MMUFLAGS           MMU_IOFLAGS     /* -- */
+#define DM320_VLYNQ_MMUFLAGS         MMU_IOFLAGS     /* -- */
+#define DM320_USBOTG_MMUFLAGS        MMU_IOFLAGS     /* -- */
+#define DM320_PERIPHERALS_MMUFLAGS   MMU_IOFLAGS     /* -- */
+
+/* 16Kb of memory is reserved at the beginning of SDRAM to hold the
+ * page table for the virtual mappings.  A portion of this table is
+ * not accessible in the virtual address space (for normal operation).
+ * We will reuse this memory for coarse page tables as follows:
+ */
+
+#define PGTABLE_BASE_PADDR          DM320_SDRAM_PADDR
+#define PGTABLE_SDRAM_PADDR         PGTABLE_BASE_PADDR
+#define PGTABLE_COARSE_BASE_PADDR   (PGTABLE_BASE_PADDR+0x00000800)
+#define PGTABLE_COARSE_END_PADDR    (PGTABLE_BASE_PADDR+0x00003000)
+#define PTTABLE_PERIPHERALS_PADDR   (PGTABLE_BASE_PADDR+0x00003000)
+#define PGTABLE_END_PADDR           (PGTABLE_BASE_PADDR+0x00004000)
+
+#define PGTABLE_BASE_VADDR          DM320_SDRAM_VADDR
+#define PGTABLE_SDRAM_VADDR         PGTABLE_BASE_VADDR
+#define PGTABLE_COARSE_BASE_VADDR   (PGTABLE_BASE_VADDR+0x00000800)
+#define PGTABLE_COARSE_END_VADDR    (PGTABLE_BASE_VADDR+0x00003000)
+#define PTTABLE_PERIPHERALS_VADDR   (PGTABLE_BASE_VADDR+0x00003000)
+#define PGTABLE_END_VADDR           (PGTABLE_BASE_VADDR+0x00004000)
+
+#define PGTBALE_COARSE_TABLE_SIZE   (4*256)
+#define PGTABLE_COARSE_ALLOC        (PGTABLE_COARSE_END_VADDR-PGTABLE_COARSE_BASE_VADDR)
+#define PGTABLE_NCOARSE_TABLES      (PGTABLE_COARSE_SIZE / PGTBALE_COARSE_TABLE_ALLOC)
+
+/* This is the base address of the interrupt vectors on the ARM926 */
+
+#define VECTOR_BASE                 DM320_VECTOR_VADDR
+
+/* DM320 Peripheral Registers */
+
+#define DM320_TIMER0_REGISTER_BASE  (DM320_PERIPHERALS_VADDR + 0x0000) /* Timer 0 */
+#define DM320_TIMER1_REGISTER_BASE  (DM320_PERIPHERALS_VADDR + 0x0080) /* Timer 1 */
+#define DM320_TIMER2_REGISTER_BASE  (DM320_PERIPHERALS_VADDR + 0x0100) /* Timer 2 */
+#define DM320_TIMER3_REGISTER_BASE  (DM320_PERIPHERALS_VADDR + 0x0180) /* Timer 3 */
+#define DM320_SERIAL0_REGISTER_BASE (DM320_PERIPHERALS_VADDR + 0x0200) /* Serial port 0 */
+#define DM320_SERIAL1_REGISTER_BASE (DM320_PERIPHERALS_VADDR + 0x0280) /* Serial port 1 */
+#define DM320_UART0_REGISTER_BASE   (DM320_PERIPHERALS_VADDR + 0x0300) /* UART 0 */
+#define DM320_UART1_REGISTER_BASE   (DM320_PERIPHERALS_VADDR + 0x0380) /* UART 1 */
+#define DM320_WDT_REGISTER_BASE     (DM320_PERIPHERALS_VADDR + 0x0400) /* Watchdog timer */
+#define DM320_MMCSD_REGISTER_BASE   (DM320_PERIPHERALS_VADDR + 0x0480) /* MMC/SD */
+#define DM320_INTC_REGISTER_BASE    (DM320_PERIPHERALS_VADDR + 0x0500) /* Interrupt controller */
+#define DM320_GIO_REGISTER_BASE     (DM320_PERIPHERALS_VADDR + 0x0580) /* GIO */
+#define DM320_DSPC_REGISTER_BASE    (DM320_PERIPHERALS_VADDR + 0x0600) /* DSP controller */
+#define DM320_OSD_REGISTER_BASE     (DM320_PERIPHERALS_VADDR + 0x0680) /* OSD */
+#define DM320_CCDC_REGISTER_BASE    (DM320_PERIPHERALS_VADDR + 0x0700) /* CCD controller */
+#define DM320_VENC_REGISTER_BASE    (DM320_PERIPHERALS_VADDR + 0x0800) /* Video encoder */
+#define DM320_CLKC_REGISTER_BASE    (DM320_PERIPHERALS_VADDR + 0x0880) /* Clock controller */
+#define DM320_BUSC_REGISTER_BASE    (DM320_PERIPHERALS_VADDR + 0x0900) /* Bus controller */
+#define DM320_SDRAMC_REGISTER_BASE  (DM320_PERIPHERALS_VADDR + 0x0980) /* SDRAM controller */
+#define DM320_EMIF_REGISTER_BASE    (DM320_PERIPHERALS_VADDR + 0x0A00) /* External memory interface */
+#define DM320_PREV_REGISTER_BASE    (DM320_PERIPHERALS_VADDR + 0x0A80) /* Preview engine */
+#define DM320_AF_REGISTER_BASE      (DM320_PERIPHERALS_VADDR + 0x0B80) /* Hardware 3A (AF/AE/AWB) */
+#define DM320_MSTICK_REGISTER_BASE  (DM320_PERIPHERALS_VADDR + 0x0C80) /* Memory stick */
+#define DM320_I2C_REGISTER_BASE     (DM320_PERIPHERALS_VADDR + 0x0D80) /* I2C */
+#define DM320_USB_REGISTER_BASE     (DM320_USBOTG_VADDR + 0x0000)      /* USB full speed OTG */
+#define DM320_USBDMA_REGISTER_BASE  (DM320_USBOTG_VADDR + 0x0200)      /* USB DMA */
+#define DM320_VLYNQ_REGISTER_BASE   (DM320_AHB_VADDR + 0x0300)         /* VLYNQ */
+#define DM320_AHBBUSC_REGISTER_BASE (DM320_AHB_VADDR + 0x0F00)         /* AHBBUSC */
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#endif
+
+#endif  /* __DM320_MEMORYMAP_H */

arch/arm/src/dm320/dm320_restart.S

@@ -0,0 +1,136 @@
+/********************************************************************
+ * dm320/dm320_restart.S
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************/
+
+/********************************************************************
+ * Included Files
+ ********************************************************************/
+
+#include <nuttx/config.h>
+#include "up_internal.h"
+#include "up_arch.h"
+
+/********************************************************************
+ * Definitions
+ ********************************************************************/
+
+/********************************************************************
+ * Assembly Macros
+ ********************************************************************/
+
+/* Since the page table is closely related to the NuttX base
+ * address, we can convert the page table base address to the
+ * base address of the section containing both.
+ */
+
+	.macro	mksection, section, pgtable
+	bic	\section, \pgtable, #0x000ff000
+	.endm
+
+/**************************************************************************
+ * Name: up_restart
+ **************************************************************************/
+
+	.text
+	.globl	up_restart
+	.type	up_restart, %function
+up_restart:
+	/* Make sure that we are in SVC mode with all IRQs disabled */
+
+	mov	r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT)
+	msr	cpsr_c, r0
+
+	/* Create identity mapping for first MB section to support
+	 * this re-start logic executing out of the physical address
+	 * space.
+	 */
+
+	mksection r0, r4			/* r0=phys. base section */
+	ldr	r1, .LCmmuflags		/* FLGS=MMU_MEMFLAGS */
+	add	r3, r1, r0		/* r3=flags + base */
+	str	r3, [r4, r0, lsr #18]	/* identity mapping */
+
+	/* Jump into the physical address space */
+
+	ldr	pc, .LCphysrestart
+	nop
+	nop
+
+	/* We are now executing at our physical address, with the
+	 * MMU disabled.
+	 */
+
+up_phyrestart:
+
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7		/* Invalidate I,D caches */
+	mcr	p15, 0, r0, c7, c10, 4	/* Drain write buffer */
+	mcr	p15, 0, r0, c8, c7		/* Invalidate I,D TLBs */
+
+	/* Clear bits in control register (see start.h): Disable,
+	 * MMU, Data cache, alignment traps, write buffer, Instruction
+	 * cache, exceptions at 0xffff0000, round robin)
+	 */
+
+	mrc	p15, 0, r0, c1, c0		/* Get control register */
+	bic	r0, r0, #(CR_M|CR_C|CR_A|CR_W)
+	bic	r0, r0, #(CR_S|CR_I|CR_V|CR_RR)
+	mcr	p15, 0, r0, c1, c0, 0		/* Write control reg */
+
+	/* We know that the the bootloader entry point is at the
+	 * beginning of flash.
+	 */
+#if 1
+	ldr	pc, .LCbtldrentry		/* Restart bootloader */
+#else
+	b	__start				/* Restart Nuttx */
+#endif
+
+	.type	.LCphysrestart, %object
+.LCphysrestart:
+	.long	(up_phyrestart - CONFIG_DRAM_VSTART - CONFIG_DRAM_START)
+.LCbtldrentry:
+	.long	DM320_EXT_MEM_PADDR
+
+/**************************************************************************
+ * PC_Relative Data
+ **************************************************************************/
+
+	.type	.LCmmuflags, %object
+.LCmmuflags:
+	.long	MMU_MEMFLAGS
+	.size	up_restart, .-up_restart
+
+	.end
+

arch/arm/src/dm320/dm320_serial.c

@@ -0,0 +1,725 @@
+/************************************************************
+ * dm320/dm320_serial.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <unistd.h>
+#include <semaphore.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/serial.h>
+#include <arch/serial.h>
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+#define BASE_BAUD 115200
+
+/************************************************************
+ * Private Types
+ ************************************************************/
+
+struct up_dev_s
+{
+  uint32               uartbase;	/* Base address of UART
+					 * registers */
+  uint32               baud;		/* Configured baud */
+  uint16               msr;		/* Saved MSR value */
+  ubyte                irq;		/* IRQ associated with
+					 * this UART */
+  ubyte                parity;		/* 0=none, 1=odd, 2=even */
+  ubyte                bits;		/* Number of bits (7 or 8) */
+  boolean              stopbits2;	/* TRUE: Configure with 2
+					 * stop bits instead of 1 */
+};
+
+/************************************************************
+ * Private Function Prototypes
+ ************************************************************/
+
+static int     up_setup(struct uart_dev_s *dev);
+static void    up_shutdown(struct uart_dev_s *dev);
+static int     up_interrupt(int irq, void *context);
+static int     up_ioctl(struct file *filep, int cmd, unsigned long arg);
+static int     up_receive(struct uart_dev_s *dev, uint32 *status);
+static void    up_rxint(struct uart_dev_s *dev, boolean enable);
+static boolean up_rxfifonotempty(struct uart_dev_s *dev);
+static void    up_send(struct uart_dev_s *dev, int ch);
+static void    up_txint(struct uart_dev_s *dev, boolean enable);
+static boolean up_txfifonotfull(struct uart_dev_s *dev);
+static boolean up_txfifoempty(struct uart_dev_s *dev);
+
+/************************************************************
+ * Private Variables
+ ************************************************************/
+
+struct uart_ops_s g_uart_ops =
+{
+  .setup          = up_setup,
+  .shutdown       = up_shutdown,
+  .handler        = up_interrupt,
+  .ioctl          = up_ioctl,
+  .receive        = up_receive,
+  .rxint          = up_rxint,
+  .rxfifonotempty = up_rxfifonotempty,
+  .send           = up_send,
+  .txint          = up_txint,
+  .txfifonotfull  = up_txfifonotfull,
+  .txfifoempty    = up_txfifoempty,
+};
+
+/* I/O buffers */
+
+static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE];
+static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+/* This describes the state of the DM320 uart0 port. */
+
+static struct up_dev_s g_uart0priv =
+{
+  .uartbase       = DM320_UART0_REGISTER_BASE,
+  .baud           = CONFIG_UART0_BAUD,
+  .parity         = CONFIG_UART0_PARITY,
+  .bits           = CONFIG_UART0_BITS,
+  .stopbits2      = CONFIG_UART0_2STOP,
+};
+
+static uart_dev_t g_uart0port =
+{
+  .irq      = DM320_IRQ_UART0,
+  .recv     =
+  {
+    .size   = CONFIG_UART0_RXBUFSIZE,
+    .buffer = g_uart0rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART0_TXBUFSIZE,
+    .buffer = g_uart0txbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart0priv,
+};
+
+/* This describes the state of the DM320 uart1 port. */
+
+static struct up_dev_s g_uart1priv =
+{
+  .uartbase       = DM320_UART1_REGISTER_BASE,
+  .baud           = CONFIG_UART1_BAUD,
+  .parity         = CONFIG_UART1_PARITY,
+  .bits           = CONFIG_UART1_BITS,
+  .stopbits2      = CONFIG_UART1_2STOP,
+};
+
+static uart_dev_t g_uart1port =
+{
+  .irq      = DM320_IRQ_UART1,
+  .recv     =
+  {
+    .size   = CONFIG_UART1_RXBUFSIZE,
+    .buffer = g_uart1rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART1_TXBUFSIZE,
+    .buffer = g_uart1txbuffer,
+   },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart1priv,
+};
+
+/* Now, which one with be tty0/console and which tty1? */
+
+#ifdef CONFIG_SERIAL_IRDA_CONSOLE
+# define CONSOLE_DEV     g_uart1port
+# define TTYS0_DEV       g_uart1port
+# define TTYS1_DEV       g_uart0port
+#else
+# define CONSOLE_DEV     g_uart0port
+# define TTYS0_DEV       g_uart0port
+# define TTYS1_DEV       g_uart1port
+#endif
+
+/************************************************************
+ * Private Functions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_serialin
+ ************************************************************/
+
+static inline uint16 up_serialin(struct up_dev_s *priv, uint32 offset)
+{
+  return getreg16(priv->uartbase + offset);
+}
+
+/************************************************************
+ * Name: up_serialout
+ ************************************************************/
+
+static inline void up_serialout(struct up_dev_s *priv, uint32 offset, uint16 value)
+{
+  putreg16(value, priv->uartbase + offset);
+}
+
+/************************************************************
+ * Name: up_disableuartint
+ ************************************************************/
+
+static inline void up_disableuartint(struct up_dev_s *priv, uint16 *msr)
+{
+  if (msr)
+    {
+      *msr = priv->msr & UART_MSR_ALLIE;
+    }
+
+  priv->msr &= ~UART_MSR_ALLIE;
+  up_serialout(priv, UART_MSR, priv->msr);
+}
+
+/************************************************************
+ * Name: up_restoreuartint
+ ************************************************************/
+
+static inline void up_restoreuartint(struct up_dev_s *priv, uint16 msr)
+{
+  priv->msr |= msr & UART_MSR_ALLIE;
+  up_serialout(priv, UART_MSR, priv->msr);
+}
+
+/************************************************************
+ * Name: up_waittxfifonotfull
+ ************************************************************/
+
+static inline void up_waittxfifonotfull(struct up_dev_s *priv)
+{
+  int tmp;
+
+  for (tmp = 1000 ; tmp > 0 ; tmp--)
+    {
+      if ((up_serialin(priv, UART_SR) & UART_SR_TFTI) != 0)
+        {
+          break;
+        }
+    }
+}
+
+/************************************************************
+ * Name: up_enablebreaks
+ ************************************************************/
+
+static inline void up_enablebreaks(struct up_dev_s *priv, boolean enable)
+{
+  uint16 lcr = up_serialin(priv, UART_LCR);
+  if (enable)
+    {
+      lcr |= UART_LCR_BOC;
+    }
+  else
+    {
+      lcr &= ~UART_LCR_BOC;
+    }
+  up_serialout(priv, UART_LCR, lcr);
+}
+
+/************************************************************
+ * Name: up_setup
+ *
+ * Description:
+ *   Configure the UART baud, bits, parity, fifos, etc. This
+ *   method is called the first time that the serial port is
+ *   opened.
+ *
+ ************************************************************/
+
+static int up_setup(struct uart_dev_s *dev)
+{
+#ifdef CONFIG_SUPPRESS_UART_CONFIG
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  uint16 brsr;
+
+  /* Clear fifos */
+
+  up_serialout(priv, UART_DM320_RFCR, 0x8000);
+  up_serialout(priv, UART_DM320_TFCR, 0x8000);
+
+  /* Set rx and tx triggers */
+
+  up_serialout(priv, UART_DM320_RFCR, UART_RFCR_RTL_1);
+  up_serialout(priv, UART_DM320_TFCR, UART_TFCR_TTL_16);
+
+  /* Set up the MSR */
+
+  priv->msr = up_serialin(priv, UART_MSR);
+  if (priv->bits == 7)
+    {
+      priv->msr |= UART_DATABIT_7;
+    }
+  else
+    {
+      priv->msr &= ~UART_MSR_CLS;
+    }
+
+  if (priv->stopbits2)
+    {
+      priv->msr |= UART_STOPBIT_2;
+    }
+  else
+    {
+      priv->msr &= ~UART_MSR_SBLS;
+    }
+
+  if (priv->parity == 1)
+    {
+      priv->msr |= UART_ODDPARITY;
+    }
+  else if (priv->parity == 2)
+    {
+      priv->msr |= UART_EVENPARITY;
+    }
+  else
+    {
+      priv->msr &= ~(UART_MSR_PSB|UART_MSR_PEB);
+    }
+
+  /* Set up the BRSR */
+
+  switch (dev->baud)
+    {
+      case 2400:
+        brsr = UART_BAUD_2400;
+        break;
+      case 4800:
+        brsr = UART_BAUD_4800;
+        break;
+      default:
+      case 9600:
+        brsr = UART_BAUD_9600;
+        break;
+      case 14400:
+        brsr = UART_BAUD_14400;
+        break;
+      case 19200:
+        brsr = UART_BAUD_19200;
+        break;
+      case 28800:
+        brsr = UART_BAUD_28800;
+        break;
+      case 3840:
+        brsr = UART_BAUD_38400;
+        break;
+      case 57600:
+        brsr = UART_BAUD_57600;
+        break;
+      case 115200:
+        brsr = UART_BAUD_115200;
+        break;
+      case 230400:
+        brsr = UART_BAUD_230400;
+        break;
+      case 460800:
+        brsr = UART_BAUD_460800;
+        break;
+      case 921600:
+        brsr = UART_BAUD_921600;
+        break;
+    }
+
+  /* Setup the new UART configuration */
+
+  up_serialout(priv,UART_MSR, priv->msr);
+  up_serialout(priv, UART_DM320_BRSR, brsr);
+  up_enablebreaks(priv, FALSE);
+#endif
+  return OK;
+}
+
+/************************************************************
+ * Name: up_shutdown
+ *
+ * Description:
+ *   Disable the UART.  This method is called when the serial
+ *   port is closed
+ *
+ ************************************************************/
+
+static void up_shutdown(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_disableuartint(priv, NULL);
+}
+
+/************************************************************
+ * Name: up_interrupt
+ *
+ * Description:
+ *   This is the UART interrupt handler.  It will be invoked
+ *   when an interrupt received on the 'irq'  It should call
+ *   uart_transmitchars or uart_receivechar to perform the
+ *   appropriate data transfers.  The interrupt handling logic\
+ *   must be able to map the 'irq' number into the approprite
+ *   uart_dev_s structure in order to call these functions.
+ *
+ ************************************************************/
+
+static int up_interrupt(int irq, void *context)
+{
+  struct uart_dev_s *dev = NULL;
+  struct up_dev_s   *priv;
+  uint16             status;
+  int                passes = 0;
+
+  if (g_uart1port.irq == irq)
+    {
+      dev = &g_uart1port;
+    }
+  else if (g_uart0port.irq == irq)
+    {
+      dev = &g_uart0port;
+    }
+  else
+    {
+      PANIC(OSERR_INTERNAL);
+    }
+  priv = (struct up_dev_s*)dev->priv;
+
+  /* Loop until there are no characters to be transferred or,
+   * until we have been looping for a long time.
+   */
+
+  for(;;)
+    {
+      /* Get the current UART status and check for loop
+       * termination conditions
+       */
+
+      status  = up_serialin(priv, UART_SR);
+      status &= (UART_SR_RFTI | UART_SR_TFTI);
+
+      if (status == 0 || passes > 256) 
+        {
+          return OK;
+        }
+
+      /* Handline incoming, receive bytes */
+
+      if (status & UART_SR_RFTI)
+        {
+          uart_recvchars(dev);
+        }
+
+      /* Handle outgoing, transmit bytes */
+
+      if (status & UART_SR_TFTI)
+        {
+          uart_xmitchars(dev);
+        }
+
+      /* Keep track of how many times we do this in case there
+       * is some hardware failure condition.
+       */
+
+      passes++;
+    }
+}
+
+/************************************************************
+ * Name: up_ioctl
+ *
+ * Description:
+ *   All ioctl calls will be routed through this method
+ *
+ ************************************************************/
+
+static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+  struct inode      *inode = filep->f_inode;
+  struct uart_dev_s *dev   = inode->i_private;
+  struct up_dev_s   *priv  = (struct up_dev_s*)dev->priv;
+  int                ret    = OK;
+
+  switch (cmd)
+    {
+    case TIOCSERGSTRUCT:
+      {
+         struct up_dev_s *user = (struct up_dev_s*)arg;
+         if (!user)
+           {
+             *get_errno_ptr() = EINVAL;
+             ret = ERROR;
+           }
+         else
+           {
+             memcpy(user, dev, sizeof(struct up_dev_s));
+           }
+       }
+       break;
+
+    case TIOCSBRK:  /* BSD compatibility: Turn break on, unconditionally */
+      {
+        irqstate_t flags = irqsave();
+        up_enablebreaks(priv, TRUE);
+        irqrestore(flags);
+      }
+      break;
+
+    case TIOCCBRK:  /* BSD compatibility: Turn break off, unconditionally */
+      {
+        irqstate_t flags;
+        flags = irqsave();
+        up_enablebreaks(priv, FALSE);
+        irqrestore(flags);
+      }
+      break;
+
+    default:
+      *get_errno_ptr() = ENOTTY;
+      ret = ERROR;
+      break;
+    }
+
+  return ret;
+}
+
+/************************************************************
+ * Name: up_receive
+ *
+ * Description:
+ *   Called (usually) from the interrupt level to receive one
+ *   character from the UART.  Error bits associated with the
+ *   receipt are provided in the the return 'status'.
+ *
+ ************************************************************/
+
+static int up_receive(struct uart_dev_s *dev, uint32 *status)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  uint16 dtrr;
+
+  dtrr    = up_serialin(priv, UART_DTRR);
+  *status = dtrr;
+  return dtrr & UART_DTRR_DTR_MASK;
+}
+
+/************************************************************
+ * Name: up_rxint
+ *
+ * Description:
+ *   Call to enable or disable RX interrupts
+ *
+ ************************************************************/
+
+static void up_rxint(struct uart_dev_s *dev, boolean enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  if (enable)
+    {
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      priv->msr |= UART_MSR_RFTIE;
+#endif
+    }
+  else
+    {
+      priv->msr &= ~UART_MSR_RFTIE;
+    }
+  up_serialout(priv, UART_MSR, priv->msr);
+}
+
+/************************************************************
+ * Name: up_rxfifonotempty
+ *
+ * Description:
+ *   Return TRUE if the receive fifo is not empty
+ *
+ ************************************************************/
+
+static boolean up_rxfifonotempty(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, UART_SR) & UART_SR_RFNEF) != 0);
+}
+
+/************************************************************
+ * Name: up_send
+ *
+ * Description:
+ *   This method will send one byte on the UART
+ *
+ ************************************************************/
+
+static void up_send(struct uart_dev_s *dev, int ch)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_serialout(priv, UART_DTRR, (uint16)ch);
+}
+
+/************************************************************
+ * Name: up_txint
+ *
+ * Description:
+ *   Call to enable or disable TX interrupts
+ *
+ ************************************************************/
+
+static void up_txint(struct uart_dev_s *dev, boolean enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  if (enable)
+    {
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      priv->msr |= UART_MSR_TFTIE;
+#endif
+    }
+  else
+    {
+      priv->msr &= ~UART_MSR_TFTIE;
+    }
+  up_serialout(priv, UART_MSR, priv->msr);
+}
+
+/************************************************************
+ * Name: up_txfifonotfull
+ *
+ * Description:
+ *   Return TRUE if the tranmsit fifo is not full
+ *
+ ************************************************************/
+
+static boolean up_txfifonotfull(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, UART_SR) & UART_SR_TFTI) != 0);
+}
+
+/************************************************************
+ * Name: up_txfifoempty
+ *
+ * Description:
+ *   Return TRUE if the transmit fifo is empty
+ *
+ ************************************************************/
+
+static boolean up_txfifoempty(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, UART_SR) & UART_SR_TREF) == 0);
+}
+
+/************************************************************
+ * Public Funtions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Performs the low level UART initialization early in 
+ *   debug so that the serial console will be available
+ *   during bootup.  This must be called before up_serialinit.
+ *
+ ************************************************************/
+
+void up_earlyserialinit(void)
+{
+  up_disableuartint(TTYS0_DEV.priv, NULL);
+  up_disableuartint(TTYS1_DEV.priv, NULL);
+
+  CONSOLE_DEV.isconsole = TRUE;
+  up_setup(&CONSOLE_DEV);
+}
+
+/************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Register serial console and serial ports.  This assumes
+ *   that up_earlyserialinit was called previously.
+ *
+ ************************************************************/
+
+void up_serialinit(void)
+{
+  (void)uart_register("/dev/console", &CONSOLE_DEV);
+  (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+  (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+}
+
+/************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug
+ *   writes
+ *
+ ************************************************************/
+
+int up_putc(int ch)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
+  uint16  ier;
+
+  up_disableuartint(priv, &ier);
+  up_waittxfifonotfull(priv);
+  up_serialout(priv, UART_DTRR, (uint16)ch);
+
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      up_waittxfifonotfull(priv);
+      up_serialout(priv, UART_DTRR, '\r');
+    }
+
+  up_waittxfifonotfull(priv);
+  up_restoreuartint(priv, ier);
+  return ch;
+}
+

arch/arm/src/dm320/dm320_timer.h

@@ -0,0 +1,112 @@
+/************************************************************************************
+ * dm320/dm320_timer.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __DM320_TIMER_H
+#define __DM320_TIMER_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+# include <sys/types.h>
+#endif
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Timer Registers */
+
+#define DM320_TIMER0_TMMD         (DM320_PERIPHERALS_VADDR + 0x0000) /* Timer 0 Mode */
+#define DM320_TIMER0_TMPRSCL      (DM320_PERIPHERALS_VADDR + 0x0004) /* Timer 0 Prescalar */
+#define DM320_TIMER0_TMDIV        (DM320_PERIPHERALS_VADDR + 0x0006) /* Timer 0 Divisor (count) */
+#define DM320_TIMER0_TMTRG        (DM320_PERIPHERALS_VADDR + 0x0008) /* Timer 0 One-Shot Trigger */
+#define DM320_TIMER0_TMCNT        (DM320_PERIPHERALS_VADDR + 0x000A) /* Timer 0 Count */
+
+#define DM320_TIMER1_TMMD         (DM320_PERIPHERALS_VADDR + 0x0080) /* Timer 1 Mode */
+#define DM320_TIMER1_TMPRSCL      (DM320_PERIPHERALS_VADDR + 0x0084) /* Timer 1 Prescalar */
+#define DM320_TIMER1_TMDIV        (DM320_PERIPHERALS_VADDR + 0x0086) /* Timer 1 Divisor (count) */
+#define DM320_TIMER1_TMTRG        (DM320_PERIPHERALS_VADDR + 0x0088) /* Timer 1 One-Shot Trigger */
+#define DM320_TIMER1_TMCNT        (DM320_PERIPHERALS_VADDR + 0x008A) /* Timer 1 Count */
+
+#define DM320_TIMER2_TMMD         (DM320_PERIPHERALS_VADDR + 0x0100) /* Timer 2 Mode */
+#define DM320_TIMER2_TMPRSCL      (DM320_PERIPHERALS_VADDR + 0x0104) /* Timer 2 Prescalar */
+#define DM320_TIMER2_TMDIV        (DM320_PERIPHERALS_VADDR + 0x0106) /* Timer 2 Divisor (count) */
+#define DM320_TIMER2_TMTRG        (DM320_PERIPHERALS_VADDR + 0x0108) /* Timer 2 One-Shot Trigger */
+#define DM320_TIMER2_TMCNT        (DM320_PERIPHERALS_VADDR + 0x010A) /* Timer 2 Count */
+
+#define DM320_TIMER3_TMMD         (DM320_PERIPHERALS_VADDR + 0x0180) /* Timer 2 Mode */
+#define DM320_TIMER3_TMPRSCL      (DM320_PERIPHERALS_VADDR + 0x0184) /* Timer 2 Prescalar */
+#define DM320_TIMER3_TMDIV        (DM320_PERIPHERALS_VADDR + 0x0186) /* Timer 2 Divisor (count) */
+#define DM320_TIMER3_TMTRG        (DM320_PERIPHERALS_VADDR + 0x0188) /* Timer 2 One-Shot Trigger */
+#define DM320_TIMER3_TMCNT        (DM320_PERIPHERALS_VADDR + 0x018A) /* Timer 2 Count */
+
+/* Timer 0,1,2,3 Mode Register Bits: */
+
+#define  DM320_TMR_MODE_TEST_MASK 0x00fc /* Bits 7:2=Test */
+#define  DM320_TMR_MODE_MODE_MASK 0x0003 /* Bits 1:0=timer mode */
+
+# define DM320_TMR_MODE_STOP      0x0000 /* Stop Timer */
+# define DM320_TMR_MODE_ONESHOT   0x0001 /* Start one-shot timer */
+# define DM320_TMR_MODE_FREERUN   0x0002 /* Start free-running timer */
+
+/* Timer 0,1,2,3 Clock Select Register Bits: */
+
+#define  DM320_TMR_PRSCL_MASK     0x03ff /* Bits 0:9=Timer prescale value */
+
+/* Timer 0,1,2,3 Clock Divisor (Count) Register Bits: */
+
+#define  DM320_TMR_DIV_MASK       0xffff /* Bits 0:15=Timer divisor value */
+
+/* Timer 0,1,2,3 Timer One-Short Trigger Register Bits: */
+
+#define  DM320_TMR_TMTRG_MASK     0x0001 /* Bit 0=One short trigger */
+
+# define DM320_TMR_TMTRG_START    0x0001 /* 1 starts one shot timer */
+
+/* Timer 0,1,2,3 Timer Counter Register Bits: */
+
+#define DM320_TMR_COUNT_MASK      0xffff /* Bits 0:15=Current counter value */
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#endif
+
+#endif  /* __DM320_TIMER_H */

arch/arm/src/dm320/dm320_timerisr.c

@@ -0,0 +1,153 @@
+/************************************************************
+ * dm320/dm320_timerisr.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include "clock_internal.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/* DM320 Timers
+ *
+ * Each of the general-purpose timers can run in one of two modes:  one-
+ * shot mode and free-run mode.  In one-shot mode, an interrupt only 
+ * occurs once and then the timer must be explicitly reset to begin the 
+ * timing operation again.  In free-run mode, when the timer generates an 
+ * interrupt, the timer counter is automatically reloaded to start the count 
+ * operation again.  Use the bit field MODE in TMMDx to configure the 
+ * timer for one-shot more or free-run mode. The bit field MODE in TMMDx
+ * also allows you to stop the timer.
+ * 
+ * Either the ARM clock divided by 2 (CLK_ARM/2) or an external clock 
+ * connected to the M27XI pin can be selected as the clock source of the 
+ * timer.
+ *
+ * The actual clock frequency used in the timer count operation is the input 
+ * clock divided by: 1 plus the value set in the bit field PRSCL of the 
+ * register TMPRSCLx (10 bits).  The timer expires when it reaches the 
+ * value set in the bit field DIV of the register TMDIVx (16 bits) plus 1. 
+ * PRSCL+1 is the source clock frequency divide factor and DIV+1 is the 
+ * timer count value.  The frequency of a timer interrupt is given by the 
+ * following equation:
+ *
+ * Interrupt Frequency = (Source Clock Frequency) / (PRSCL+1) / (DIV+1)
+ */
+
+/* System Timer
+ *
+ * Timer0 is dedicated as the system timer.  The rate of system timer
+ * interrupts is assumed to to 10MS per tick / 100Hz. The following
+ * register settings are used for timer 0
+ *
+ * System clock formula:
+ *   Interrupt Frequency = (Source Clock Frequency) / (PRSCL+1) / (DIV+1)
+ *   Source Clock Frequency = 27MHz  (PLL clock)
+ *   DIV                    = 26,999 (Yields 1Khz timer clock)
+ *   PRSCL                  = 9      (Produces 100Hz interrupts)
+ */
+
+#define DM320_TMR0_MODE  DM320_TMR_MODE_FREERUN /* Free running */
+#define DM320_TMR0_DIV   26999                  /* (see above) */
+#define DM320_TMR0_PRSCL 9                      /* (see above) */
+
+/************************************************************
+ * Private Types
+ ************************************************************/
+
+/************************************************************
+ * Private Function Prototypes
+ ************************************************************/
+
+/************************************************************
+ * Global Functions
+ ************************************************************/
+
+/************************************************************
+ * Function:  up_timerisr
+ *
+ * Description:
+ *   The timer ISR will perform a variety of services for
+ *   various portions of the systems.
+ *
+ ************************************************************/
+
+int up_timerisr(int irq, uint32 *regs)
+{
+   /* Process timer interrupt */
+
+   sched_process_timer();
+   return 0;
+}
+
+/************************************************************
+ * Function:  up_timerinit
+ *
+ * Description:
+ *   This function is called during start-up to initialize
+ *   the timer interrupt.
+ *
+ ************************************************************/
+
+void up_timerinit(void)
+{
+  up_disable_irq(DM320_IRQ_SYSTIMER);
+
+  /* Start timer0 running so that an interrupt is generated at
+   * the rate MSEC_PER_TICK.
+   */
+
+  putreg16(DM320_TMR0_PRSCL, DM320_TIMER0_TMPRSCL); /* Timer 0 Prescalar */
+  putreg16(DM320_TMR0_DIV, DM320_TIMER0_TMDIV);     /* Timer 0 Divisor (count) */
+
+  /* Start the timer */
+
+  putreg16(DM320_TMR0_MODE, DM320_TIMER0_TMMD); /* Timer 0 Mode */
+
+  /* Attach and enable the timer interrupt */
+
+  irq_attach(DM320_IRQ_SYSTIMER, (xcpt_t)up_timerisr);
+  up_enable_irq(DM320_IRQ_SYSTIMER);
+}
+

arch/arm/src/dm320/dm320_uart.h

@@ -0,0 +1,172 @@
+/************************************************************************************
+ * dm320/dm320_uart.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __DM320_UART_H
+#define __DM320_UART_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+# include <sys/types.h>
+#endif
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* UART definitions *****************************************************************/
+
+/* UART Registers (offsets from the register base) */
+
+#define UART_DTRR              0    /* Data Transmission/Reception Register */
+#define UART_BRSR              2    /* Bit Rate Set Register */
+#define UART_MSR               4    /* Mode Set Register */
+#define UART_RFCR              6    /* Reception FIFO Control Register */
+#define UART_TFCR              8    /* Transmission FIFO Control Register */
+#define UART_LCR              10    /* Line Control Register */
+#define UART_SR               12    /* Status Register */
+
+/* UART DTRR register bit definitions */
+
+#define UART_DTRR_RVF         0x1000 /* Receive word valid flag */
+#define UART_DTRR_BF          0x0800 /* Break flag */
+#define UART_DTRR_FE          0x0400 /* Framing error */
+#define UART_DTRR_ORF         0x0200 /* Overrun flag */
+#define UART_DTRR_PEF         0x0100 /* Parity error */
+#define UART_DTRR_DTR_MASK    0x00ff /* Data transmit/receive */
+
+/* UART BRSR register bit definitions */
+/* The UART clock is half of the ARM clock */
+
+#define UART_CLK (DM320_ARM_CLOCK / 2)
+
+/* And baud rate = UART_CLK / 16 / (VALUE+1) */
+
+#define UART_BAUD_2400        ((uint16)(((UART_CLK / 16) / 2400  ) - 1))
+#define UART_BAUD_4800        ((uint16)(((UART_CLK / 16) / 4800  ) - 1))
+#define UART_BAUD_9600        ((uint16)(((UART_CLK / 16) / 9600  ) - 1))
+#define UART_BAUD_14400       ((uint16)(((UART_CLK / 16) / 14400 ) - 1))
+#define UART_BAUD_19200       ((uint16)(((UART_CLK / 16) / 19200 ) - 1))
+#define UART_BAUD_28800       ((uint16)(((UART_CLK / 16) / 28800 ) - 1))
+#define UART_BAUD_38400       ((uint16)(((UART_CLK / 16) / 38400 ) - 1))
+#define UART_BAUD_57600       ((uint16)(((UART_CLK / 16) / 57600 ) - 1))
+#define UART_BAUD_115200      ((uint16)(((UART_CLK / 16) / 115200) - 1))
+#define UART_BAUD_230400      ((uint16)(((UART_CLK / 16) / 230400) - 1))
+#define UART_BAUD_460800      ((uint16)(((UART_CLK / 16) / 460800) - 1))
+#define UART_BAUD_921600      ((uint16)(((UART_CLK / 16) / 921600) - 1))
+
+/* UART MSR register bit definitions */
+
+#define UART_MSR_MODE_BITS    0x001f /* Aata length, stop, & parity */
+#define UART_MSR_CLS          0x0001 /* Char length (1=7bit, 0=8bit) */
+#define UART_DATABIT_7        0x0001 /*  Data bit = 7bit */
+#define UART_DATABIT_8        0x0000 /*  Data bit = 8bit */
+#define UART_MSR_SBLS         0x0004 /* Stop bit length selection */
+#define UART_STOPBIT_1        0x0000 /*  Stop bit = 1bit */
+#define UART_STOPBIT_2        0x0004 /*  Stop bit = 2bit */
+#define UART_MSR_PSB          0x0008 /* Parity selection bit */
+#define UART_MSR_PEB          0x0010 /* Parity enable bit */
+#define UART_NOPARITY         0x0000 /*   No-parity */
+#define UART_ODDPARITY        0x0018 /*   Odd parity */
+#define UART_EVENPARITY       0x0010 /*   Even parity */
+#define UART_MSR_RTSC         0x0020 /* RTS receive FIFO control */
+#define UART_MSR_CSTC         0x0040 /* CTS send control */
+#define UART_MSR_TOIC_MASK    0x0c00 /* Timeout interrupt control */
+#define UART_MSR_TOIC_DIS     0x0000 /*   Disabled */
+#define UART_MSR_TOIC_3       0x0400 /*   3 bytes */
+#define UART_MSR_TOIC_7       0x0800 /*   7 bytes */
+#define UART_MSR_TOIC_15      0x0c00 /*  15 bytes */
+#define UART_MSR_ALLIE        0xfc00 /* All interrupt bits */
+#define UART_MSR_LSIE         0x1000 /*  Line status change int. enable */
+#define UART_MSR_REIE         0x2000 /*  Receive error interrupt enable */
+#define UART_MSR_TFTIE        0x4000 /*  Transmit FIFO trigger int. enable */
+#define UART_MSR_RFTIE        0x8000 /*  Receive FIFO trigger int. enable */
+
+#define  UART_MSR_INIT (UART_NOPARITY | UART_STOPBIT_1 | UART_DATABIT_8)
+
+/* UART RFCR register bit definitions */
+
+#define UART_RFCR_RWC_MASK    0x003f /* Receive byte count */
+#define UART_RFCR_RTL_MASK    0x0700 /* Receive trigger level */
+#define UART_RFCR_RTL_1       0x0000 /*   1 byte */
+#define UART_RFCR_RTL_4       0x0100 /*   4 bytes */
+#define UART_RFCR_RTL_8       0x0200 /*   8 bytes */
+#define UART_RFCR_RTL_16      0x0300 /*  16 bytes */
+#define UART_RFCR_RTL_24      0x0400 /*  24 bytes */
+#define UART_RFCR_RTL_32      0x0500 /*  32 bytes */
+#define UART_RFCR_RDEF        0x4000 /* Receive data error flag */
+#define UART_RFCR_RFCB        0x8000 /* Receive FIFO clear bit */
+
+/* UART TFCR register bit definitions */
+
+#define UART_TFCR_TWC_MASK    0x003f /* Transmit byte count */
+#define UART_TFCR_TTL_MASK    0x0700 /* Transmit trigger level */
+#define UART_TFCR_TTL_1       0x0000 /*   1 byte */
+#define UART_TFCR_TTL_4       0x0100 /*   4 bytes */
+#define UART_TFCR_TTL_8       0x0200 /*   8 bytes */
+#define UART_TFCR_TTL_16      0x0300 /*  16 bytes */
+#define UART_TFCR_TTL_24      0x0400 /*  24 bytes */
+#define UART_TFCR_TTL_32      0x0500 /*  32 bytes */
+#define UART_TFCR_TFCB        0x8000 /* Transmit FIFO clear bit */
+
+/* UART LCR register bit definitions */
+
+#define UART_LCR_RTS          0x0004 /* Current RTS value */
+#define UART_LCR_CTS          0x0010 /* Current CTS value */
+#define UART_LCR_DSR          0x0080 /* Current DSR value */
+#define UART_LCR_BOC          0x0100 /* Break output control */
+#define UART_LCR_UTST         0x4000 /* Test mode setting */
+
+#define UART_LCR_INIT         0x0000
+
+/* UART SR register bit definitions */
+
+#define UART_SR_TREF          0x0001 /* Transmit register empty flag */
+#define UART_SR_TFEF          0x0002 /* Transmit FIFO empty flag */
+#define UART_SR_RFNEF         0x0004 /* Receive FIFO not empty flag */
+#define UART_SR_TOIF          0x0100 /* Timeout Interrupt flag */
+#define UART_SR_RFER          0x0200 /* Receive data error flag */
+#define UART_SR_TFTI          0x0400 /* Transmit FIFO trigger level */
+#define UART_SR_RFTI          0x0800 /* Receive FIFO trigger level */
+#define UART_SR_CTSS          0x1000 /* CTS status */
+#define UART_SR_DSRS          0x8000 /* DSR status */
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#endif  /* __DM320_UART_H */

arch/arm/src/lpc214x/Make.defs

@@ -0,0 +1,50 @@
+############################################################################
+# lpc214x/Make.defs
+#
+#   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name Gregory Nutt nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+HEAD_ASRC	= lpc214x_head.S
+
+CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_vectors.S
+CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
+		  up_createstack.c up_dataabort.c up_delay.c up_exit.c \
+		  up_idle.c up_initialize.c up_initialstate.c \
+		  up_interruptcontext.c up_prefetchabort.c up_releasepending.c \
+		  up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \
+		  up_sigdeliver.c up_syscall.c up_unblocktask.c \
+		  up_undefinedinsn.c up_usestack.c
+
+CHIP_ASRCS	= lpc214x_lowputc.S
+CHIP_CSRCS	= lpc214x_decodeirq.c lpc214x_irq.c lpc214x_timerisr.c \
+		  lpc214x_serial.c
+	

arch/arm/src/lpc214x/README.txt

@@ -0,0 +1,61 @@
+General Description
+^^^^^^^^^^^^^^^^^^^
+
+http://www.nxp.com/pip/LPC2141FBD64.html:
+
+The LPC2141/42/44/46/48 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S
+CPU with real-time emulation and embedded trace support, that combine
+microcontroller with embedded high-speed flash memory ranging from 32 kB to
+512 kB. A 128-bit wide memory interface and a unique accelerator architecture
+enable 32-bit code execution at the maximum clock rate. For critical code size
+applications, the alternative 16-bit Thumb mode reduces code by more than 30 pct
+with minimal performance penalty. 
+
+Due to their tiny size and low power consumption, LPC2141/42/44/46/48 are ideal
+for applications where miniaturization is a key requirement, such as access
+control and point-of-sale. Serial communications interfaces ranging from a USB 2.0
+Full-speed device, multiple UARTs, SPI, SSP to I2C-bus and on-chip SRAM of 8 kB
+up to 40 kB, make these devices very well suited for communication gateways and
+protocol converters, soft modems, voice recognition and low end imaging, providing
+both large buffer size and high processing power. Various 32-bit timers, single
+or dual 10-bit ADC(s), 10-bit DAC, PWM channels and 45 fast GPIO lines with up
+to nine edge or level sensitive external interrupt pins make these microcontrollers
+suitable for industrial control and medical systems. 
+
+
+Features
+^^^^^^^^
+
+o 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package. 
+o 8 kB to 40 kB of on-chip static RAM and 32 kB to 512 kB of on-chip flash memory.
+  128-bit wide interface/accelerator enables high-speed 60 MHz operation. 
+o In-System Programming/In-Application Programming (ISP/IAP) via on-chip boot
+  loader software. Single flash sector or full chip erase in 400 ms and programming
+  of 256 B in 1 ms. 
+o EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with the
+  on-chip RealMonitor software and high-speed tracing of instruction execution. 
+o USB 2.0 Full-speed compliant device controller with 2 kB of endpoint RAM. In addition,
+  the LPC2146/48 provides 8 kB of on-chip RAM accessible to USB by DMA. 
+o One or two (LPC2141/42 vs. LPC2144/46/48) 10-bit ADCs provide a total of 6/14 analog
+  inputs, with conversion times as low as 2.44 us per channel. 
+o Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only). 
+o Two 32-bit timers/external event counters (with four capture and four compare
+  channels each), PWM unit (six outputs) and watchdog. 
+o Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input. 
+o Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400
+  kbit/s), SPI and SSP with buffering and variable data length capabilities. 
+o Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses. 
+o Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package. 
+o Up to 21 external interrupt pins available. 
+o 60 MHz maximum CPU clock available from programmable on-chip PLL with settling
+  time of 100 us. 
+o On-chip integrated oscillator operates with an external crystal from 1 MHz to 25 MHz. 
+o Power saving modes include Idle and Power-down. 
+o Individual enable/disable of peripheral functions as well as peripheral clock scaling
+  for additional power optimization. 
+o Processor wake-up from Power-down mode via external interrupt or BOD. 
+o Single power supply chip with POR and BOD circuits: 
+o CPU operating voltage range of 3.0 V to 3.6 V (3.3 V +- 10 pct) with 5 V tolerant
+  I/O pads. 
+
+ 

arch/arm/src/lpc214x/Startup.s

@@ -0,0 +1,80 @@
+/*
+ *  The STARTUP.S code is executed after CPU Reset. This file may be 
+ *  translated with the following SET symbols. In uVision these SET 
+ *  symbols are entered under Options - ASM - Set.
+ *
+ *  REMAP: when set the startup code initializes the register MEMMAP 
+ *  which overwrites the settings of the CPU configuration pins. The 
+ *  startup and interrupt vectors are remapped from:
+ *     0x00000000  default setting (not remapped)
+ *     0x80000000  when EXTMEM_MODE is used
+ *     0x40000000  when RAM_MODE is used
+ *
+ *  EXTMEM_MODE: when set the device is configured for code execution
+ *  from external memory starting at address 0x80000000. The startup
+ *  vectors are located to 0x80000000.
+ *
+ *  RAM_MODE: when set the device is configured for code execution
+ *  from on-chip RAM starting at address 0x40000000. The startup
+ *  vectors are located to 0x40000000.
+ */
+
+Reset_Handler:  
+
+
+
+/* Memory Mapping */
+
+
+/* Setup Stack for each mode */
+	ldr	r0, =Top_Stack
+
+/* Enter Undefined Instruction Mode and set its Stack Pointer */
+	msr     CPSR_c, #UND_MODE | PSR_I_BIT | PSR_F_BIT
+	mov     SP, r0
+	sub	r0, r0, #UND_Stack_Size
+
+/* Enter Abort Mode and set its Stack Pointer */
+	msr     CPSR_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT
+	mov     SP, r0
+	sub	r0, r0, #ABT_Stack_Size
+
+/* Enter FIQ Mode and set its Stack Pointer */
+	msr     CPSR_c, #FIQ_MODE | PSR_I_BIT | PSR_F_BIT
+	mov     SP, r0
+	sub	r0, r0, #FIQ_Stack_Size
+
+/* Enter IRQ Mode and set its Stack Pointer */
+	msr     CPSR_c, #IRQ_MODE | PSR_I_BIT | PSR_F_BIT
+	mov     SP, r0
+	sub	r0, r0, #IRQ_Stack_Size
+
+/* Enter Supervisor Mode and set its Stack Pointer */
+	msr     CPSR_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT
+	mov     SP, r0
+	sub	r0, r0, #SVC_Stack_Size
+
+/* Enter User Mode and set its Stack Pointer */
+	msr     CPSR_c, #USR_MODE
+	mov     SP, r0
+
+/* Enter the C code */
+	ldr	r0,=?C?INIT
+	tst	r0,#1	; Bit-0 set: INIT is Thumb
+	ldreq   LR,=exit?A  ; ARM Mode
+	ldrne   LR,=exit?T  ; Thumb Mode
+	bx	r0
+	ENDP
+
+PUBLIC exit?A
+exit?A	   PROC    CODE32
+	B	exit?A
+	ENDP
+
+PUBLIC exit?T
+exit?T	   PROC    CODE16
+exit:	    B	exit?T
+	ENDP
+
+
+	END

arch/arm/src/lpc214x/chip.h

@@ -0,0 +1,337 @@
+/****************************************************************************************************
+ * lpc214x/chip.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __LPC214X_CHIP_H
+#define __LPC214X_CHIP_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Definitions
+ ****************************************************************************************************/
+
+/* Memory Map ***************************************************************************************/
+
+#define LPC214X_FLASH_BASE              0x00000000
+#define LPC214X_ONCHIP_RAM_BASE         0x40000000
+#define LPC214X_USBDMA_RAM_BASE         0x7fd00000
+#define LPC214X_BOOT_BLOCK              0x7fffd000
+#define LPC214X_EXTMEM_BASE             0x80000000
+#define LPC214X_APB_BASE                0xe0000000
+#define LPC214X_AHB_BASE                0xf0000000
+
+/* Peripheral Registers ****************************************************************************/
+
+/* Register block base addresses */
+
+#define LPC214X_WD_BASE                 0xe0000000  /* Watchdog base address */
+#define LPC214X_TMR0_BASE               0xe0004000  /* Timer 0 base address*/
+#define LPC214X_TMR1_BASE               0xe0008000  /* Timer 1 base address */
+#define LPC214X_UART0_BASE              0xe000c000  /* UART0 base address */
+#define LPC214X_UART1_BASE              0xe0010000  /* UART1 base address */
+#define LPC214X_PWM_BASE                0xe0014000  /* Pulse width modulator (PWM) base address */
+#define LPC214X_I2C_BASE                0xe001C000  /* I2C base address */
+#define LPC214X_SPI0_BASE               0xe0020000  /* Serial Peripheral Interface 0 (SPI0) base */
+#define LPC214X_RTC_BASE                0xe0024000  /* Real Time Clock (RTC) base address */
+#define LPC214X_GPIO0_BASE              0xe0028000  /* General Purpose I/O (GPIO) 0 base address */
+#define LPC214X_GPIO1_BASE              0xe0028010  /* General Purpose I/O (GPIO) 0 base address */
+#define LPC214X_PINSEL_BASE             0xe002c000  /* Pin function select registers */
+#define LPC214X_SPI1_BASE               0xe0030000  /* Serial Peripheral Interface 1 (SPI1) base */
+#define LPC214X_AD0_BASE                0xe0034000  /* Analog to Digital Converter 0 base address*/
+#define LPC214X_AD1_BASE                0xe0060000  /* Analog to Digital Converter 1 base address */
+
+#define LPC214X_SCB_BASE                0xe01fc000  /* System Control Block (SBC) base address */
+#define   LPC214X_MAM_BASE              0xe01fc000  /* Memory Accelerator Module (MAM) base address */
+#define   LPC214X_MEMMAP                0xe01fc040  /* Memory Mapping Control */
+#define   LPC214X_PLL_BASE              0xe01fc080  /* Phase Locked Loop (PLL) base address */
+#define   LPC214X_PCON_BASE             0xe01fc0c0  /* Power Control (PCON) base address */
+#define   LPC214X_VPBDIV                0xe01fc100  /* VPBDIV Address */
+#define   LPC214X_EXT_BASE              0xe01fc140  /* External Interrupt base address */       
+
+#define LPC214X_EMC_BASE                0xffe00000  /* External Memory Controller (EMC) base address */
+#define LPC214X_VIC_BASE                0xfffff000  /* Vectored Interrupt Controller (VIC) Base */
+
+/* Watchdog Register Offsets */
+
+#define LPC214X_WD_MOD_OFFSET           0x00 /* Watchdog Mode Register */
+#define LPC214X_WD_TC_OFFSET            0x04 /* Watchdog Time Constant Register */
+#define LPC214X_WD_FEED_OFFSET          0x08 /* Watchdog Feed Register */
+#define LPC214X_WD_TV_OFFSET            0x0C /* Watchdog Time Value Register */
+
+/* Timer 0/1 register offsets */
+
+#define LPC214X_TMR_IR_OFFSET           0x00   /* RW:Interrupt Register */
+#define LPC214X_TMR_TCR_OFFSET          0x04   /* RW: Timer Control Register */
+#define LPC214X_TMR_TC_OFFSET           0x08   /* RW: Timer Counter */
+#define LPC214X_TMR_PR_OFFSET           0x0c   /* RW: Prescale Register */
+#define LPC214X_TMR_PC_OFFSET           0x10   /* RW: Prescale Counter Register */
+#define LPC214X_TMR_MCR_OFFSET          0x14   /* RW: Match Control Register */
+#define LPC214X_TMR_MR0_OFFSET          0x18   /* RW: Match Register 0 */
+#define LPC214X_TMR_MR1_OFFSET          0x1c   /* RW: Match Register 1 */
+#define LPC214X_TMR_MR2_OFFSET          0x20   /* RW: Match Register 2 */
+#define LPC214X_TMR_MR3_OFFSET          0x24   /* RW: Match Register 3 */
+#define LPC214X_TMR_CCR_OFFSET          0x28   /* RW: Capture Control Register */
+#define LPC214X_TMR_CR0_OFFSET          0x2c   /* R: Capture Register 0 */
+#define LPC214X_TMR_CR1_OFFSET          0x30   /* R: Capture Register 1 */
+#define LPC214X_TMR_CR2_OFFSET          0x34   /* R: Capture Register 2 */
+#define LPC214X_TMR_CR3_OFFSET          0x38   /* RW: Capture Register 3 */
+#define LPC214X_TMR_EMR_OFFSET          0x3c   /* RW: External Match Register */
+
+#define LPC214X_TMR_CTCR_OFFSET         0x70   /* RW: Count Control Register */
+
+/* UART0/1 Register Offsets */
+
+#define LPC214X_UART_RBR_OFFSET         0x00   /* R: Receive Buffer Register (DLAB=0) */
+#define LPC214X_UART_THR_OFFSET         0x00   /* W: Transmit Holding Register (DLAB=0) */
+#define LPC214X_UART_DLL_OFFSET         0x00   /* W: Divisor Latch Register (LSB, DLAB=1) */
+#define LPC214X_UART_IER_OFFSET         0x04   /* W: Interrupt Enable Register (DLAB=0) */
+#define LPC214X_UART_DLM_OFFSET         0x04   /* RW: Divisor Latch Register (MSB, DLAB=1) */
+#define LPC214X_UART_IIR_OFFSET         0x08   /* R: Interrupt ID Register */
+#define LPC214X_UART_FCR_OFFSET         0x08   /* W: FIFO Control Register */
+#define LPC214X_UART_LCR_OFFSET         0x0c   /* RW: Line Control Register */
+#define LPC214X_UART_MCR_OFFSET         0x10   /* RW: Modem Control REgister (2146/6/8 UART1 Only) */
+#define LPC214X_UART_LSR_OFFSET         0x14   /* R: Scratch Pad Register */
+#define LPC214X_UART_MSR_OFFSET         0x18   /* RW: MODEM Status Register (2146/6/8 UART1 Only) */
+#define LPC214X_UART_SCR_OFFSET         0x1c   /* RW: Line Status Register */
+#define LPC214X_UART_ACR_OFFSET         0x20   /* RW: Autobaud Control Register */
+#define LPC214X_UART_FDR_OFFSET         0x28   /* RW: Fractional Divider Register */
+#define LPC214X_UART_TER_OFFSET         0x30   /* RW: Transmit Enable Register */
+
+/* PWM register offsets */
+
+#define LPC214X_PWM_IR_OFFSET           0x00   /* Interrupt Register */
+#define LPC214X_PWM_TCR_OFFSET          0x04   /* Timer Control Register */
+#define LPC214X_PWM_TC_OFFSET           0x08   /* Timer Counter */
+#define LPC214X_PWM_PR_OFFSET           0x0c   /* Prescale Register */
+#define LPC214X_PWM_PC_OFFSET           0x10   /* Prescale Counter Register */
+#define LPC214X_PWM_MCR_OFFSET          0x14   /* Match Control Register */
+#define LPC214X_PWM_MR0_OFFSET          0x18   /* Match Register 0 */
+#define LPC214X_PWM_MR1_OFFSET          0x1c   /* Match Register 1 */
+#define LPC214X_PWM_MR2_OFFSET          0x20   /* Match Register 2 */
+#define LPC214X_PWM_MR3_OFFSET          0x24   /* Match Register 3 */
+#define LPC214X_PWM_MR4_OFFSET          0x40   /* Match Register 4 */
+#define LPC214X_PWM_MR5_OFFSET          0x44   /* Match Register 5 */
+#define LPC214X_PWM_MR6_OFFSET          0x48   /* Match Register 6 */
+#define LPC214X_PWM_PCR_OFFSET          0x4c   /* Control Register */
+#define LPC214X_PWM_LER_OFFSET          0x50   /* Latch Enable Register */
+
+/* I2C register offsets */
+
+#define LPC214X_I2C_ONSET_OFFSET        0x00   /* Control Set Register */
+#define LPC214X_I2C_STAT_OFFSET         0x04   /* Status Register */
+#define LPC214X_I2C_DAT_OFFSET          0x08   /* Data Register */
+#define LPC214X_I2C_ADR_OFFSET          0x0c   /* Slave Address Register */
+#define LPC214X_I2C_SCLH_OFFSET         0x10   /* SCL Duty Cycle Register (high half word) */
+#define LPC214X_I2C_SCLL_OFFSET         0x14   /* SCL Duty Cycle Register (low half word) */
+#define LPC214X_I2C_ONCLR_OFFSET        0x18   /* Control Clear Register */
+
+/* Pin function select register offsets */
+
+#define LPC214X_PINSEL0_OFFSET          0x00   /* Pin function select register 0 */
+#define LPC214X_PINSEL1_OFFSET          0x04   /* Pin function select register 1 */
+#define LPC214X_PINSEL2_OFFSET          0x14   /* Pin function select register 2 */
+
+/* Analog to Digital (AD) Converter registger offsets */
+#define LPC214X_AD_ADCR_OFFSET          0x00   /* A/D Control Register */
+#define LPC214X_AD_ADGDR_OFFSET         0x04   /* A/D Global Data Register (only one common register!) */
+#define LPC214X_AD_ADGSR_OFFSET         0x08   /* A/D Global Start Register */
+#define LPC214X_AD_ADINTEN_OFFSET       0x0c   /* A/D Interrupt Enable Register */
+#define LPC214X_AD_ADDR0_OFFSET         0x10   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADDR1_OFFSET         0x14   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADDR2_OFFSET         0x18   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADDR3_OFFSET         0x1c   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADDR4_OFFSET         0x20   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADDR5_OFFSET         0x24   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADDR6_OFFSET         0x28   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADDR7_OFFSET         0x2c   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADSTAT_OFFSET        0x30   /* A/D Status Register */
+
+/* Pin function select registers (these are normally referenced as offsets) */
+
+#define LPC214X_PINSEL0                 (LPC214X_PINSEL_BASE + LPC214X_PINSEL0_OFFSET)
+#define LPC214X_PINSEL1                 (LPC214X_PINSEL_BASE + LPC214X_PINSEL1_OFFSET)
+#define LPC214X_PINSEL2                 (LPC214X_PINSEL_BASE + LPC214X_PINSEL2_OFFSET)
+
+/* SPI register offsets */
+
+#define LPC214X_SPI_CR0_OFFSET          0x00   /* Control Register 0 */
+#define LPC214X_SPI_CR1_OFFSET          0x04   /* Control Register 1 */
+#define LPC214X_SPI_DR_OFFSET           0x08   /* Data Register */
+#define LPC214X_SPI_SR_OFFSET           0x0c   /* Status Register */
+#define LPC214X_SPI_CPSR_OFFSET         0x10   /* Clock Pre-Scale Regisrer */
+#define LPC214X_SPI_IMSC_OFFSET         0x14   /* Interrupt Mask Set and Clear Register */
+#define LPC214X_SPI_RIS_OFFSET          0x18   /* Raw Interrupt Status Register */
+#define LPC214X_SPI_MIS_OFFSET          0x1c   /* Masked Interrupt Status Register */
+#define LPC214X_SPI_ICR_OFFSET          0x20   /* Interrupt Clear Register */
+
+/* RTC register offsets */
+
+#define LPC214X_RTC_ILR_OFFSET          0x00   /* Interrupt Location Register */
+#define LPC214X_RTC_CTC_OFFSET          0x04   /* Clock Tick Counter */
+#define LPC214X_RTC_CCR_OFFSET          0x08   /* Clock Control Register */
+#define LPC214X_RTC_CIIR_OFFSET         0x0c   /* Counter Increment Interrupt Register */
+#define LPC214X_RTC_AMR_OFFSET          0x10   /* Alarm Mask Register */
+#define LPC214X_RTC_CTIME0_OFFSET       0x14   /* Consolidated Time Register 0 */
+#define LPC214X_RTC_CTIME1_OFFSET       0x18   /* Consolidated Time Register 1 */
+#define LPC214X_RTC_CTIME2_OFFSET       0x1c   /* Consolidated Time Register 2 */
+#define LPC214X_RTC_SEC_OFFSET          0x20   /* Seconds Register */
+#define LPC214X_RTC_MIN_OFFSET          0x24   /* Minutes Register */
+#define LPC214X_RTC_HOUR_OFFSET         0x28   /* Hours Register */
+#define LPC214X_RTC_DOM_OFFSET          0x2c   /* Day Of Month Register */
+#define LPC214X_RTC_DOW_OFFSET          0x30   /* Day Of Week Register */
+#define LPC214X_RTC_DOY_OFFSET          0x34   /* Day Of Year Register */
+#define LPC214X_RTC_MONTH_OFFSET        0x38   /* Months Register */
+#define LPC214X_RTC_YEAR_OFFSET         0x3c   /* Years Register */
+
+#define LPC214X_RTC_ALSEC_OFFSET        0x60   /* Alarm Seconds Register */
+#define LPC214X_RTC_ALMIN_OFFSET        0x64   /* Alarm Minutes Register */
+#define LPC214X_RTC_ALHOUR_OFFSET       0x68   /* Alarm Hours Register */
+#define LPC214X_RTC_ALDOM_OFFSET        0x6c   /* Alarm Day Of Month Register */
+#define LPC214X_RTC_ALDOW_OFFSET        0x70   /* Alarm Day Of Week Register */
+#define LPC214X_RTC_ALDOY_OFFSET        0x74   /* Alarm Day Of Year Register */
+#define LPC214X_RTC_ALMON_OFFSET        0x78   /* Alarm Months Register */
+#define LPC214X_RTC_ALYEAR_OFFSET       0x7c   /* Alarm Years Register */
+#define LPC214X_RTC_PREINT_OFFSET       0x80   /* Prescale Value Register (integer) */
+#define LPC214X_RTC_PREFRAC_OFFSET      0x84   /* Prescale Value Register (fraction) */
+
+/* GPIO register offsets */
+
+#define LPC214X_GPIO_PIN_OFFSET         0x00   /* Pin Value Register */
+#define LPC214X_GPIO_SET_OFFSET         0x04   /* Pin Output Set Register */
+#define LPC214X_GPIO_DIR_OFFSET         0x08   /* Pin Direction Register */
+#define LPC214X_GPIO_CLR_OFFSET         0x0c   /* Pin Output Clear Register */
+
+/* Memory Accelerator Module (MAM) Regiser Offsets */
+
+#define LPC214X_MAM_CR_OFFSET           0x00   /* MAM Control Offset*/
+#define LPC214x_MAM_TIM_OFFSET          0x04   /* MAM Timing Offset */
+
+/* Phase Locked Loop (PLL) Register Offsets */
+
+#define LPC214X_PLL_CON_OFFSET          0x00   /* PLL Control Offset*/
+#define LPC214X_PLL_CFG_OFFSET          0x04   /* PLL Configuration Offset */
+#define LPC214X_PLL_STAT_OFFSET         0x08   /* PLL Status Offset */
+#define LPC214X_PLL_FEED_OFFSET         0x0c   /* PLL Feed Offset */
+
+/* PLL Control Register Bit Settings */
+
+#define LPC214X_PLL_CON_PLLE            (1 << 0) /* PLL Enable */
+#define LPC214X_PLL_CON_PLLC            (1 << 1) /* PLL Connect */
+
+/* PLL Configuration Register Bit Settings */
+
+#define LPC214X_PLL_CFG_MSEL            (0x1f << 0) /* PLL Multiplier */
+#define LPC214X_PLL_CFG_PSEL            (0x03 << 5) /* PLL Divider */
+#define LPC214X_PLL_STAT_PLOCK          (1 << 10)   /* PLL Lock Status */
+
+/* Power Control register offsets */
+
+#define LPC214X_PCON_OFFSET             0x00   /* Control Register */
+#define LPC214X_PCONP_OFFSET            0x04   /* Peripherals Register */
+
+/* External Interrupt register offsets */
+
+#define LPC214X_EXT_INT_OFFSET          0x00   /* Flag Register */
+#define LPC214X_EXT_WAKE_OFFSET         0x04   /* Wakeup Register */
+#define LPC214X_EXT_MODE_OFFSET         0x08   /* Mode Register */
+#define LPC214X_EXT_POLAR_OFFSET        0x0c   /* Polarity Register */
+
+/* External Memory Controller (EMC) definitions */
+
+#define LPC214X_BCFG0_OFFSET            0x00   /* BCFG0 Offset */
+#define LPC214X_BCFG1_OFFSET            0x04   /* BCFG1 Offset */
+#define LPC214X_BCFG2_OFFSET            0x08   /* BCFG2 Offset */
+#define LPC214X_BCFG3_OFFSET            0x0c   /* BCFG3 Offset */
+
+/* Vectored Interrupt Controller (VIC) register offsets */
+
+#define LPC214X_VIC_IRQSTATUS_OFFSET    0x00   /* R: IRQ Status Register */
+#define LPC214X_VIC_FIQSTATUS_OFFSET    0x04   /* R: FIQ Status Register */
+#define LPC214X_VIC_RAWINTR_OFFSET      0x08   /* R: Raw Interrupt Status Register */
+#define LPC214X_VIC_INTSELECT_OFFSET    0x0c   /* RW: Interrupt Select Register */
+#define LPC214X_VIC_INTENABLE_OFFSET    0x10   /* RW: Interrupt Enable Register */
+#define LPC214X_VIC_INTENCLEAR_OFFSET   0x14   /* W: Interrupt Enable Clear Register */
+#define LPC214X_VIC_SOFTINT_OFFSET      0x18   /* RW: Software Interrupt Register */
+#define LPC214X_VIC_SOFTINTCLEAR_OFFSET 0x1c   /* W: Software Interrupt Clear Register */
+#define LPC214X_VIC_PROTECTION_OFFSET   0x20   /* Protection Enable Register */
+
+#define LPC214X_VIC_VECTADDR_OFFSET     0x30   /* RW: Vector Address Register */
+#define LPC214X_VIC_DEFVECTADDR_OFFSET  0x34   /* RW: Default Vector Address Register */
+
+#define LPC214X_VIC_VECTADDR0_OFFSET    0x100  /* RW: Vector Address 0 Register */
+#define LPC214X_VIC_VECTADDR1_OFFSET    0x104  /* RW: Vector Address 1 Register */
+#define LPC214X_VIC_VECTADDR2_OFFSET    0x108  /* RW: Vector Address 2 Register */
+#define LPC214X_VIC_VECTADDR3_OFFSET    0x10c  /* RW: Vector Address 3 Register */
+#define LPC214X_VIC_VECTADDR4_OFFSET    0x110  /* RW: Vector Address 4 Register */
+#define LPC214X_VIC_VECTADDR5_OFFSET    0x114  /* RW: Vector Address 5 Register */
+#define LPC214X_VIC_VECTADDR6_OFFSET    0x118  /* RW: Vector Address 6 Register */
+#define LPC214X_VIC_VECTADDR7_OFFSET    0x11c  /* RW: Vector Address 7 Register */
+#define LPC214X_VIC_VECTADDR8_OFFSET    0x120  /* RW: Vector Address 8 Register */
+#define LPC214X_VIC_VECTADDR9_OFFSET    0x124  /* RW: Vector Address 9 Register */
+#define LPC214X_VIC_VECTADDR10_OFFSET   0x128  /* RW: Vector Address 10 Register */
+#define LPC214X_VIC_VECTADDR11_OFFSET   0x12c  /* RW: Vector Address 11 Register */
+#define LPC214X_VIC_VECTADDR12_OFFSET   0x130  /* RW: Vector Address 12 Register */
+#define LPC214X_VIC_VECTADDR13_OFFSET   0x134  /* RW: Vector Address 13 Register */
+#define LPC214X_VIC_VECTADDR14_OFFSET   0x138  /* RW: Vector Address 14 Register */
+#define LPC214X_VIC_VECTADDR15_OFFSET   0x13c  /* RW: Vector Address 15 Register */
+
+#define LPC214X_VIC_VECTCNTL0_OFFSET    0x200  /* RW: Vector Control 0 Register */
+#define LPC214X_VIC_VECTCNTL1_OFFSET    0x204  /* RW: Vector Control 1 Register */
+#define LPC214X_VIC_VECTCNTL2_OFFSET    0x208  /* RW: Vector Control 2 Register */
+#define LPC214X_VIC_VECTCNTL3_OFFSET    0x20c  /* RW: Vector Control 3 Register */
+#define LPC214X_VIC_VECTCNTL4_OFFSET    0x210  /* RW: Vector Control 4 Register */
+#define LPC214X_VIC_VECTCNTL5_OFFSET    0x214  /* RW: Vector Control 5 Register */
+#define LPC214X_VIC_VECTCNTL6_OFFSET    0x218  /* RW: Vector Control 6 Register */
+#define LPC214X_VIC_VECTCNTL7_OFFSET    0x21c  /* RW: Vector Control 7 Register */
+#define LPC214X_VIC_VECTCNTL8_OFFSET    0x220  /* RW: Vector Control 8 Register */
+#define LPC214X_VIC_VECTCNTL9_OFFSET    0x224  /* RW: Vector Control 9 Register */
+#define LPC214X_VIC_VECTCNTL10_OFFSET   0x228  /* RW: Vector Control 10 Register */
+#define LPC214X_VIC_VECTCNTL11_OFFSET   0x22c  /* RW: Vector Control 11 Register */
+#define LPC214X_VIC_VECTCNTL12_OFFSET   0x230  /* RW: Vector Control 12 Register */
+#define LPC214X_VIC_VECTCNTL13_OFFSET   0x234  /* RW: Vector Control 13 Register */
+#define LPC214X_VIC_VECTCNTL14_OFFSET   0x238  /* RW: Vector Control 14 Register */
+#define LPC214X_VIC_VECTCNTL15_OFFSET   0x23c  /* RW: Vector Control 15 Register */
+
+/****************************************************************************************************
+ * Inline Functions
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Global Function Prototypes
+ ****************************************************************************************************/
+
+#endif  /* __LPC214X_CHIP_H */

arch/arm/src/lpc214x/lpc214x_decodeirq.c

@@ -0,0 +1,166 @@
+/********************************************************************************
+ * lpc214x/lpc214x_decodeirq.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************/
+
+/********************************************************************************
+ * Included Files
+ ********************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <assert.h>
+#include <debug.h>
+
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+#include "lpc214x_vic.h"
+
+/********************************************************************************
+ * Definitions
+ ********************************************************************************/
+
+/********************************************************************************
+ * Private Types
+ ********************************************************************************/
+
+/********************************************************************************
+ * Public Data
+ ********************************************************************************/
+
+/********************************************************************************
+ * Private Data
+ ********************************************************************************/
+
+/* This type arry maps 4 bits into the bit number of the lowest bit that it set */
+
+static uint8 g_nibblemap[16] = { 0, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0 };
+
+/********************************************************************************
+ * Private Functions
+ ********************************************************************************/
+
+/********************************************************************************
+ * Public Funstions
+ ********************************************************************************/
+
+/********************************************************************************
+ * up_decodeirq() and/or lpc214x_decodeirq()
+ *
+ * Description:
+ *   The vectored interrupt controller (VIC) takes 32 interrupt request inputs
+ *   and programmatically assigns them into 3 categories:  FIQ, vectored IRQ,
+ *   and non-vectored IRQ.
+ *
+ *   - FIQs have the highest priority.  There is a single FIQ vector, but multiple
+ *     interrupt sources can be ORed to this FIQ vector.
+ *
+ *   - Vectored IRQs have the middle priority.  Any 16 of the 32 interrupt sources
+ *     can be assigned to vectored IRQs.
+ *
+ *   - Non-vectored IRQs have the lowest priority.
+ *
+ *   The general flow of IRQ processing is to simply read the VIC vector address
+ *   and jump to the address of the vector provided in the register.  The VIC will
+ *   provide the address of the highest priority vectored IRQ.  If a non-vectored
+ *   IRQ is requesting, the address of a default handler is provided.
+ *
+ ********************************************************************************/
+
+#ifndef CONFIG_VECTORED_INTERRUPTS
+void up_decodeirq(uint32 *regs)
+#else
+static void lpc214x_decodeirq( uint32 *regs)
+#endif
+{
+#ifdef CONFIG_SUPPRESS_INTERRUPTS
+  lib_lowprintf("Unexpected IRQ\n");
+  current_regs = regs;
+  PANIC(OSERR_ERREXCEPTION);
+#else
+
+  /* Decode the interrupt. We have to do this by search for the lowest numbered
+   * non-zero bit in the interrupt status register.
+   */
+
+  uint32 pending = vic_getreg(LPC214X_VIC_IRQSTATUS_OFFSET) & 0x007fffff;
+  unsigned int nibble;
+  unsigned int irq_base;
+  unsigned int irq = NR_IRQS;
+
+  /* Search in groups of four bits.  For 22 sources, this is at most six
+   * times through the loop.
+   */
+
+  for (nibble = pending & 0xff, irq_base = 0;
+       pending && irq < NR_IRQS;
+       pending >>= 4, nibble = pending & 0xff, irq_base += 4)
+    {
+      if (nibble)
+        {
+          irq = irq_base + g_nibblemap[nibble];
+          break;
+        }
+    }
+
+  /* Verify that the resulting IRQ number is valid */
+
+  if (irq < NR_IRQS)
+    {
+      /* Current regs non-zero indicates that we are processing an interrupt;
+       * current_regs is also used to manage interrupt level context switches.
+       */
+
+      current_regs = regs;
+
+      /* Deliver the IRQ */
+
+      irq_dispatch(irq, regs);
+
+      /* Indicate that we are no long in an interrupt handler */
+
+      current_regs = NULL;
+    }
+#endif
+}
+
+#ifdef CONFIG_VECTORED_INTERRUPTS
+void up_decodeirq(uint32 *regs)
+{
+  vic_vector_t vector = (vic_vector)vic_getreg(LPC214X_VIC_VECTADDR_OFFSET);
+  vector(regs);
+}
+#endif

arch/arm/src/lpc214x/lpc214x_head.S

@@ -0,0 +1,527 @@
+/********************************************************************
+ * lpc214x/lpc214x_head.S
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************/
+
+/********************************************************************
+ * Included Files
+ ********************************************************************/
+
+#include <nuttx/config.h>
+#include "up_internal.h"
+#include "up_arch.h"
+
+/********************************************************************
+ * Definitions
+ ********************************************************************/
+
+/* This file holds the NuttX start logic that runs when the LPC2148
+ * is reset.  This logic must be located at address 0x0000:0000 in
+ * flash but may be linked to run at different locations based on
+ * the selected mode:
+ *
+ * default: Executes from 0x0000:0000.  In non-default modes, the
+ *   MEMAP register is set override the settings of the CPU configuration
+ *   pins.
+ *
+ *  CONFIG_EXTMEM_MODE: Code executes from external memory starting at
+ *    address 0x8000:0000.
+ *
+ *  CONFIG_RAM_MODE: Code executes from on-chip RAM at address
+ *     0x4000:0000.
+ *
+ * Starupt Code must be linked to run at the correct address
+ * corresponding to the selected mode.
+ */
+
+#if defined(CONFIG_EXTMEM_MODE)
+#  if CONFIG_CODE_BASE != LPC214X_EXTMEM_BASE
+#    error "CONFIG_CODE_BASE must be 0x80000000 in EXTMEM mode"
+#  endif
+#elif defined(CONFIG_RAM_MODE)
+#  if CONFIG_CODE_BASE != LPC214X_ONCHIP_RAM_BASE
+#    error "CONFIG_CODE_BASE must be 0x40000000 in EXTMEM mode"
+#  endif
+#else
+#  if CONFIG_CODE_BASE != LPC214X_FLASH_BASE
+#    error "CONFIG_CODE_BASE must be 0x00000000 in default mode"
+#  endif
+#endif
+
+/* Phase Locked Loop (PLL) initialization values
+ *
+ * BIT 0:4 MSEL: PLL Multiplier "M" Value
+ *               CCLK = M * Fosc
+ * BIT 5:6 PSEL: PLL Divider "P" Value 
+ *               Fcco = CCLK * 2 * P
+ *               156MHz <= Fcco <= 320MHz
+ */
+
+
+#ifndef CONFIG_PLLCFG_VALUE /* Can be selected from config file */
+#  define CONFIG_PLLCFG_VALUE 0x00000024
+#endif
+
+/* Memory Accelerator Module (MAM) initialization values
+ *
+ * MAM Control Register
+ *   BIT 0:1 Mode
+ *           0 = Disabled
+ *           1 = Partially Enabled
+ *           2 = Fully Enabled
+ * MAM Timing Register
+ *   BIT 0:2 Fetch Cycles
+ *           0 = Reserved
+ *           1 = 1
+ *           2 = 2
+ *           3 = 3
+ *           4 = 4
+ *           5 = 5
+ *           6 = 6
+ *           7 = 7
+ */
+
+#ifndef CONFIG_MAMCR_VALUE /* Can be selected from config file */
+#  define CONFIG_MAMCR_VALUE  0x00000002
+#endif
+
+#ifndef CONFIG_MAMTIM_VALUE /* Can be selected from config file */
+#  define CONFIG_MAMTIM_VALUE 0x00000004
+#endif
+
+/* VPBDIV initialization values
+ *
+ * BITS 0:1 VPB Peripheral Bus Clock Rate
+ *          0 = VPB Clock = CPU Clock / 4
+ *          1 = VPB Clock = CPU Clock
+ *          2 = VPB Clock = CPU Clock / 2
+ * BITS 4:5 XCLKDIV: XCLK Pin
+ *          0 = XCLK Pin = CPU Clock / 4
+ *          1 = XCLK Pin = CPU Clock
+ *          2 = XCLK Pin = CPU Clock / 2
+ */
+
+#ifndef CONFIG_VPBDIV_VALUE /* Can be selected from config file */
+#  define CONFIG_VPBDIV_VALUE 0x00000001
+#endif
+
+/* External Memory Controller (EMC) initialization values
+ *
+ * Bank Configuration n (BCFG0..3)
+ *    BIT 0:3   IDCY: Idle Cycles (0-15)
+ *    BIT 5:9   WST1: Wait States 1 (0-31)
+ *    BIT 11:15 WST2: Wait States 2 (0-31)
+ *    BIT 10    RBLE: Read Byte Lane Enable
+ *    BIT 26    WP: Write Protect
+ *    BIT 27    BM: Burst ROM
+ *    BIT 28:29 MW: Memory Width  (0=8-bit 1=16-bit 2=32-bit 3=Reserved)
+ */
+
+#ifndef CONFIG_BCFG0_VALUE /* Can be selected from config file */
+#  define CONFIG_BCFG0_VALUE   0x0000fbef
+#endif
+
+#ifndef CONFIG_BCFG1_VALUE /* Can be selected from config file */
+#  define CONFIG_BCFG1_VALUE   0x0000fbef
+#endif
+
+#ifndef CONFIG_BCFG2_VALUE /* Can be selected from config file */
+#  define CONFIG_BCFG2_VALUE   0x0000fbef
+#endif
+
+#ifndef CONFIG_BCFG3_VALUE /* Can be selected from config file */
+#  define CONFIG_BCFG3_VALUE   0x0000fbef
+#endif
+
+/* The following are used to configure the ADC/DAC */
+#ifndef CONFIG_AD0CR_VALUE
+#  define CONFIG_AD0CR_VALUE   0x00200402; /* Setup A/D: 10-bit AIN0 @ 3MHz */
+#endif
+
+/* GIO Pin Selection Register settings
+ *
+ * PINSEL0 configures GPIO 0.0 through 0.15
+ */
+
+#ifndef CONFIG_PINSEL0_VALUE /* Can be selected from config file */
+#  define CONFIG_PINSEL0_VALUE 0x00000000 /* Reset value */
+#endif
+
+/* PINSEL1 configures GPIO 0.16 through 0.30 and GPO */
+
+#ifndef CONFIG_PINSEL1_VALUE /* Can be selected from the config file */
+#  ifdef CONFIG_ADC_SETUP
+#    define CONFIG_PINSEL1_VALUE 0x01000000; /* Enable DAC */
+#  else
+#    define CONFIG_PINSEL1_VALUE 0x00000000; /* Reset value */
+#  endif
+#endif
+
+/* External Memory Pins definitions
+ * BIT 0:1  Reserved
+ * BIT 2    GPIO/DEBUG
+ * BIT 3    GPIO/TRACE
+ * BIT 31:4 Reserved
+ * CS0..3, OE, WE, BLS0..3,  D0..31, A2..23, JTAG Pins
+ */
+
+#ifndef CONFIG_PINSEL2_VALUE /* Can be selected from config file */
+#  define CONFIG_PINSEL2_VALUE 0x0e6149e4
+#endif
+
+/********************************************************************
+ * Macros
+ ********************************************************************/
+
+/* Print a character on the UART to show boot status. This macro will
+ * modify r0, r1, r2 and r14
+ */
+
+	.macro	showprogress, code
+#ifdef CONFIG_DEBUG
+	mov	r0, #\code
+	bl	up_lowputc
+#endif
+	.endm
+
+/* Configured the PINSEL2 register if EXTMEM mode is selected */
+
+	.macro	configpinsel2, base, val
+#ifdef CONFIG_EXTMEM_MODE
+	ldr	\base, =LPC214X_PINSEL2
+	ldr	\val, =CONFIG_PINSEL2_VALUE
+	str	\val, [\base]
+#endif
+	.endm
+
+/* Configure the external memory controller */
+
+	.macro	configemc, base, val
+#ifdef CONFIG_EMC_SETUP
+	ldr	\base, =LPC214X_EMC_BASE
+
+#ifdef CONFIG_BCFG0_SETUP
+	ldr	\val, =CONFIG_BCFG0_VALUE
+	str	\val, [\base, #LPC214X_BCFG0_OFFSET]
+#endif
+
+#ifdef CONFIG_BCFG1_SETUP
+	ldr	\val, =CONFIG_BCFG1_VALUE
+	str	\val, [\base, #LPC214X_BCFG1_OFFSET]
+#endif
+
+#ifdef CONFIG_BCFG2_SETUP
+	ldr	\val, =CONFIG_BCFG2_VALUE
+	str	\val, [\base, #LPC214X_BCFG2_OFFSET]
+#endif
+
+#ifdef CONFIG_BCFG3_SETUP
+	ldr	\val, =CONFIG_BCFG3_VALUE
+	str	\val, [\base, #LPC214X_BCFG3_OFFSET]
+#endif
+#endif
+	.endm
+
+/* Configure VPBDIV */
+
+	.macro	configvpbdiv, base, val
+#ifdef CONFIG_VPBDIV_SETUP
+	ldr	\base, =LPC214X_VPBDIV
+	ldr	\val, =CONFIG_VPBDIV_VALUE
+	str	\val, [\base]
+#endif
+	.endm
+
+/* Configure the PLL */
+
+	.macro	configpll, base, val1, val2, val3
+#ifdef LPC214X_PLL_SETUP
+	ldr	\base, =LPC214X_PLL_BASE
+	mov	\val1, #0xaa
+	mov	\val2, #0x55
+
+	/* Configure and Enable PLL */
+
+	mov	\val3, #CONFIG_PLLCFG_VALUE
+	str	\val3, [\base, #LPC214X_PLLCFG_OFFSET] 
+	mov	\val3, #LPC214X_PLLCON_PLLE
+	str	\val3, [\base, #LPC214X_PLLCON_OFFSET]
+	str	\val1, [\base, #LPC214X_PLLFEED_OFFSET]
+	str	\val2, [\base, #LPC214X_PLLFEED_OFFSET]
+
+	/* Wait until PLL Locked */
+1:
+	ldr	\val3, [\base, #LPC214X_PLLSTAT_OFFSET]
+	ands	\val3, \val3, #LPC214X_PLLSTAT_PLOCK
+	beq	1b
+
+	/* Switch to PLL Clock */
+
+	mov	\val3, #(LPC214X_PLLCON_PLLE | LPC214X_PLLCON_PLLC)
+	str	\val3, [\base, #LPC214X_PLLCON__OFFSET]
+	str	\val1, [\base, #LPC214X_PLLFEED_OFFSET]
+	str	\val2, [\base, #LPC214X_PLLFEED_OFFSET]
+#endif
+	.endm
+
+/* Configure the Memory Accelerator Module (MAM) */
+
+	.macro	configmam, base, val
+#ifdef CONFIG_MAM_SETUP
+	ldr	\base, =LPC214X_MAM_BASE
+	mov	\val, #CONFIG_MAMTIM_VALUE
+	str	\val, [\base, #LPC214x_MAM_TIM_OFFSET] 
+	mov	\val, #CONFIG_MAMCR_VALUE
+	str	\val, [\base, #LPC214X_MAM_CR_OFFSET] 
+#endif
+	.endm
+
+/* Setup MEMMAP for the selected mode of operation */
+
+	.macro	configmemmap, base, val
+	ldr	\base, =LPC214X_MEMMAP
+#if defined(CONFIG_EXTMEM_MODE)
+	mov	\val, #3
+#elif defined(CONFIG_RAM_MODE)
+	mov	\val, #2
+#else /* Setting the default should not be necessary */
+	mov	\val, #1
+#endif
+	str	\val, [\base]
+	.endm
+
+	.macro	configdac, base, tmp
+#ifdef CONFIG_ADC_SETUP
+	ldr	\base, =LPC214X_AD0_BASE
+	ldr	\tmp, =CONFIG_AD0CR_VALUE
+	str	\tmp, [\base, #LPC214X_AD_ADCR_OFFSET]
+
+	ldr	\base,=LPC214X_PINSEL1
+	ldr	\tmp, =CONFIG_PINSEL1_VALUE
+	str	\tmp, [\base]
+#endif
+	.endm
+
+/********************************************************************
+ * Text
+ ********************************************************************/
+
+	.text
+
+/********************************************************************
+ * Name: _vector_table
+ *
+ * Description:
+ *   Interrrupt vector table.  This must be located at the beginning
+ *   of the memory space (at CONFIG_CODE_BASE).  The first entry in
+ *   the vector table is the reset vector and this is the code that
+ *   will execute whn the processor is reset.
+ *
+ ********************************************************************/
+
+	.globl	_vector_table
+	.type	_vector_table, %function
+_vector_table:
+	ldr	pc, .Lresethandler		/* 0x00: Reset */
+	ldr	pc, .Lundefinedhandler		/* 0x04: Undefined instruction */
+	ldr	pc, .Lswihandler		/* 0x08: Software interrupt */
+	ldr	pc, .Lprefetchaborthandler	/* 0x0c: Prefetch abort */
+	ldr	pc, .Ldataaborthandler		/* 0x10: Data abort */
+	ldr	pc, .Laddrexcptnhandler		/* 0x14: Address exception */
+	ldr	pc, .Lirqhandler		/* 0x18: IRQ */
+	ldr	pc, .Lfiqhandler		/* 0x1c: FIQ */
+
+	.globl   __start
+	.globl	up_vectorundefinsn
+	.globl	up_vectorswi
+	.globl	up_vectorprefetch
+	.globl	up_vectordata
+	.globl	up_vectoraddrexcptn
+	.globl	up_vectorirq
+	.globl	up_vectorfiq
+
+.Lresethandler:
+	.long   __start
+.Lundefinedhandler:
+	.long	up_vectorundefinsn
+.Lswihandler:
+	.long	up_vectorswi
+.Lprefetchaborthandler:
+	.long	up_vectorprefetch
+.Ldataaborthandler:
+	.long	up_vectordata
+.Laddrexcptnhandler:
+	.long	up_vectoraddrexcptn
+.Lirqhandler:
+	.long	up_vectorirq
+.Lfiqhandler:
+	.long	up_vectorfiq
+	.size	_vector_table, . - _vector_table
+
+/********************************************************************
+ * Name: __start
+ *
+ * Description:
+ *   Reset entry point.  This is the first function to execute when
+ *   the processor is reset.  It initializes hardware and then gives
+ *   control to NuttX.
+ *
+ ********************************************************************/
+
+	.global __start
+	.type	__start, #function
+
+__start:
+	/* Setup the initial processor mode */
+
+	mov	r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT )
+	msr	cpsr, r0
+
+	/* Set up external memory mode (if so selected) */
+
+	configpinsel2	r0, r1
+
+	/* Setup the External Memory Controllor (EMC) as configured */
+
+	configemc	r0, r1
+
+	/* Configure VPBDIV */
+
+	configvpbdiv	r0, r1
+	
+	/* Configure the PLL */
+
+	configpll	r0, r1, r2, r3
+
+	/* Configure the Memory Accelerator Module (MAM) */
+
+	configmam	r0, r1
+
+	/* Setup MEMMAP for the selected mode of operation */
+
+	configmemmap	r0, r1
+
+	/* Configure the DAC and ADC */
+	
+	configdac	r0, r1
+
+	/* Configure the uart so that we can get debug output as soon
+	 * as possible.  Modifies r0, r1, r2, and r14.
+	 */
+
+        bl	up_lowsetup
+	showprogress 'A'
+
+	/* Setup system stack (and get the BSS range) */
+
+	adr	r0, LC0
+	ldmia   r0, {r4, r5, sp}
+
+	/* Clear system BSS section */
+
+	mov	r0, #0
+1:	cmp	r4, r5
+	strcc	r0, [r4], #4
+	bcc	1b
+
+	showprogress 'B'
+
+	/* Copy system .data sections to new home in RAM. */
+
+#ifdef CONFIG_BOOT_FROM_FLASH
+
+	adr	r3, LC2
+	ldmia	r3, {r0, r1, r2}
+
+1:	ldmia	r0!, {r3 - r10}
+	stmia	r1!, {r3 - r10}
+	cmp	r1, r2
+	blt	1b
+
+#endif
+	/* Perform early serial initialization */
+
+	mov	fp, #0
+	bl	up_earlyserialinit
+
+#ifdef CONFIG_DEBUG
+	mov	r0, #'C'
+	bl	up_putc
+	mov	r0, #'\n'
+	bl	up_putc
+#endif
+	/* Initialize onboard LEDs */
+
+#ifdef CONFIG_ARCH_LEDS
+	bl	up_ledinit
+#endif
+
+	/* Then jump to OS entry */
+
+	b	os_start
+
+	/* Variables:
+	 * _sbss is the start of the BSS region (see ld.script)
+	 * _ebss is the end of the BSS regsion (see ld.script)
+	 * The idle task stack starts at the end of BSS and is
+	 * of size CONFIG_PROC_STACK_SIZE.  The heap continues
+	 * from there until the end of memory.  See g_heapbase
+	 * below.
+	 */
+
+LC0:	.long	_sbss
+	.long	_ebss
+	.long	_ebss+CONFIG_PROC_STACK_SIZE-4
+
+#ifdef CONFIG_BOOT_FROM_FLASH
+LC2:	.long	_eronly	/* Where .data defaults are stored in FLASH */
+	.long	_sdata	/* Where .data needs to reside in SDRAM */
+	.long	_edata
+#endif
+	.size	__start, .-__start
+
+	/* This global variable is unsigned long g_heapbase and is
+	 * exported from here only because of its coupling to LCO
+	 * above.
+	 */
+
+	.data
+	.align	4
+	.globl	g_heapbase
+	.type	g_heapbase, object
+g_heapbase:
+	.long	_ebss+CONFIG_PROC_STACK_SIZE
+	.size	g_heapbase, .-g_heapbase
+
+	.end
+

arch/arm/src/lpc214x/lpc214x_irq.c

@@ -0,0 +1,219 @@
+/****************************************************************************
+ * lpc214x/lpc214x_irq.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <nuttx/irq.h>
+
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+#include "lpc214x_vic.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+uint32 *current_regs;
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Funtions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_irqinitialize
+ ****************************************************************************/
+
+void up_irqinitialize(void)
+{
+  int reg;
+
+  /* Disable all interrupts.  We do this by writing zero to the IntEnable
+   * register.  This is equivalent to writing all ones to the IntClearEnable
+   * register.
+   */
+
+  vic_putreg(0, LPC214X_VIC_INTENABLE_OFFSET);
+
+  /* Select all IRQs, no FIQs */
+
+  vic_putreg(0, LPC214X_VIC_INTSELECT_OFFSET);
+
+  /* Set the default vector */
+
+  vic_putreg((uint32)up_decodeirq, LPC214X_VIC_DEFVECTADDR_OFFSET);
+
+  /* Disable all vectored interrupts */
+
+  for (reg = LPC214X_VIC_VECTCNTL0_OFFSET;
+       reg <= LPC214X_VIC_VECTCNTL15_OFFSET;
+       reg += 4)
+    {
+      vic_putreg(0, reg);
+    }
+
+  /* currents_regs is non-NULL only while processing an interrupt */
+
+  current_regs = NULL;
+
+  /* And finally, enable interrupts */
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+  irqrestore(SVC_MODE | PSR_F_BIT);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ *   Disable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_disable_irq(int irq)
+{
+  /* Verify that the IRQ number is within range */
+
+  if (irq < NR_IRQS)
+    {
+      /* Disable the irq by setting the corresponding bit in the VIC
+       * Interrupt Enable Clear register.
+       */
+
+      vic_putreg((1 << irq), LPC214X_VIC_INTENCLEAR_OFFSET);
+    }
+}
+
+/****************************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ *   Enable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_enable_irq(int irq)
+{
+  /* Verify that the IRQ number is within range */
+
+  if (irq < NR_IRQS)
+    {
+      /* Disable all interrupts */
+
+      irqstate_t flags = irqsave();
+
+      /* Enable the irq by setting the corresponding bit in the VIC
+       * Interrupt Enable register.
+       */
+
+      uint32 val = vic_getreg(LPC214X_VIC_INTENABLE_OFFSET);
+      vic_putreg(val | (1 << irq), LPC214X_VIC_INTENCLEAR_OFFSET);
+      irqrestore(flags);
+    }
+}
+
+/****************************************************************************
+ * Name: up_attach_vector
+ *
+ * Description:
+ *   Attach a user-supplied handler to a vectored interrupt
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_VECTORED_INTERRUPTS
+void up_attach_vector(int irq, int vector, vic_vector_t handler)
+{
+  /* Verify that the IRQ number and vector number are within range */
+
+  if (irq < NR_IRQS && vector < 16 && handler)
+    {
+      int offset = vector << 2;
+
+      /* Disable all interrupts */
+
+      irqstate_t flags = irqsave();
+
+      /* Save the vector address */
+
+      vic_putreg((uint32)handler, LPC214X_VIC_VECTADDR0_OFFSET + offset);
+
+      /* Enable the vectored interrupt */
+
+      vic_putreg(((irq << LPC214X_VECTCNTL_IRQSHIFT) | LPC214X_VECTCNTL_ENABLE),
+		 LPC214X_VIC_VECTCNTL0_OFFSET + offset);
+      irqrestore(flags);
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: up_detach_vector
+ *
+ * Description:
+ *   Detach a user-supplied handler from a vectored interrupt
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_VECTORED_INTERRUPTS
+void up_detach_vector(int vector)
+{
+  /* Verify that the vector number is within range */
+
+  if (vector < 16)
+    {
+      /* Disable the vectored interrupt */
+
+      int offset = vector << 2;
+      vic_putreg(0, LPC214X_VIC_VECTCNTL0_OFFSET + offset);
+    }
+}
+#endif

arch/arm/src/lpc214x/lpc214x_lowputc.S

@@ -0,0 +1,198 @@
+/**************************************************************************
+ * lpc214x/lpc214X_lowputc.S
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ **************************************************************************/
+
+/**************************************************************************
+ * Included Files
+ **************************************************************************/
+
+#include <nuttx/config.h>
+#include "up_internal.h"
+#include "up_arch.h"
+#include "lpc214x_uart.h"
+
+/**************************************************************************
+ * Private Definitions
+ **************************************************************************/
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+#  define LPC214X_UART_BASE    LPC214X_UART0_BASE
+#  define LPC214X_UART_PINSEL  LPC214X_UART0_PINSEL
+#  define LPC214X_UART_PINMASK LPC214X_UART0_PINMASK
+#  define LPC214X_UART_BAUD    CONFIG_UART0_BAUD
+#  define LPC214X_UART_BITS    CONFIG_UART0_BITS
+#  define LPC214X_UART_PARITY  CONFIG_UART0_PARITY
+#  define LPC214X_UART_2STOP   CONFIG_UART0_2STOP
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+#  define LPC214X_UART_BASE    LPC214X_UART1_BASE
+#  define LPC214X_UART_PINSEL  LPC214X_UART1_PINSEL
+#  define LPC214X_UART_PINMASK LPC214X_UART1_PINMASK
+#  define LPC214X_UART_BAUD    CONFIG_UART1_BAUD
+#  define LPC214X_UART_BITS    CONFIG_UART1_BITS
+#  define LPC214X_UART_PARITY  CONFIG_UART1_PARITY
+#  define LPC214X_UART_2STOP   CONFIG_UART1_2STOP
+#else
+#  error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
+#endif
+
+#if LPC214X_UART_BITS == 5
+#  define LPC214X_LCR_CHAR LPC214X_LCR_CHAR_5
+#elif LPC214X_UART_BITS == 6
+#  define LPC214X_LCR_CHAR LPC214X_LCR_CHAR_6
+#elif LPC214X_UART_BITS == 7
+#  define LPC214X_LCR_CHAR LPC214X_LCR_CHAR_7
+#elif LPC214X_UART_BITS == 8
+#  define LPC214X_LCR_CHAR LPC214X_LCR_CHAR_8
+#else
+#  error "No CONFIG_UARTn_BITS Setting"
+#endif
+
+#if LPC214X_UART_PARITY == 0
+#  define LPC214X_LCR_PAR LPC214X_LCR_PAR_NONE
+#elif LPC214X_UART_PARITY == 1
+#  define LPC214X_LCR_PAR LPC214X_LCR_PAR_ODD
+#elif LPC214X_UART_PARITY == 2
+#  define LPC214X_LCR_PAR LPC214X_LCR_PAR_EVEN
+#elif LPC214X_UART_PARITY == 3
+#  define LPC214X_LCR_PAR LPC214X_LCR_PAR_MARK
+#elif LPC214X_UART_PARITY == 4
+#  define LPC214X_LCR_PAR LPC214X_LCR_PAR_SPACE
+#else
+#  error "No CONFIG_UARTn_PARITY Setting"
+#endif
+
+#ifdef LPC214X_UART_2STOP != 0
+#  define LPC214X_LCR_STOP LPC214X_LCR_STOP_2
+#else
+#  define LPC214X_LCR_STOP LPC214X_LCR_STOP_1
+#endif
+
+#define LPC214X_LCR_VALUE (LPC214X_LCR_CHAR | LPC214X_LCR_PAR | LPC214X_LCR_STOP)
+
+/**************************************************************************
+ * Private Types
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Function Prototypes
+ **************************************************************************/
+
+/**************************************************************************
+ * Global Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Public Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Name: up_lowputc
+ **************************************************************************/
+
+/* This assembly language version has the advantage that it can does not
+ * require a C stack and uses only r0-r1.  Hence it can be used during
+ * early boot phases.
+ */
+
+	.text
+	.global	up_lowputc
+	.type	up_lowputc, function
+up_lowputc:
+	/* On entry, r0 holds the character to be printed */
+
+	ldr	r1, =LPC214X_UART_BASE
+	strb	r0, [r1, #LPC214X_UART_THR_OFFSET]
+
+	/* Wait for the byte to be transferred */
+
+1:	ldr	r0, [r1, #LPC214X_UART_LSR_OFFSET]
+	ands	r0, #LPC214X_LSR_TEMT  /* Transmitter empty */
+	beq	1b
+
+	/* And return */
+
+	mov     pc, lr
+	.size	up_lowputc, . - up_lowputc
+
+/* This performs basic initialization of the UART.  This can be called very
+ * early in initialization because it does not depend on having a stack.  It
+ * modifies r0-r2 and r14.
+ */
+
+	.text
+	.globl	up_lowsetup
+	.type	up_lowsetup, function
+up_lowsetup:
+	/* Configure PINSEL0 */
+
+	ldr	r0, =LPC214X_PINSEL0
+	ldr	r1, [r0]
+	ldr	r2, =~LPC214X_UART_PINMASK
+	and	r1, r2
+	ldr	r2, =LPC214X_UART_PINSEL
+	orr	r1, r2
+	str	r1, [r0]
+
+	/* Configure parity, data bits, stop bits and set DLAB=1 */
+
+	ldr	r0, =LPC214X_UART0_BASE
+	mov	r1, #(LPC214X_LCR_VALUE | LPC214X_LCR_DLAB_ENABLE)
+	strb	r1, [r0, #LPC214X_UART_LCR_OFFSET]
+
+	/* Set the BAUD divisor */
+
+	mov	r1, #(UART_BAUD(LPC214X_UART_BAUD) >> 8)
+	strb	r1, [r0, #LPC214X_UART_DLM_OFFSET]
+
+	mov	r1, #(UART_BAUD(LPC214X_UART_BAUD) & 0xff)
+	strb	r1, [r0, #LPC214X_UART_DLL_OFFSET]
+
+	/* Clear DLAB */
+	
+	mov	r1, #LPC214X_LCR_VALUE
+	strb	r1, [r0, #LPC214X_UART_LCR_OFFSET]
+
+	/* And return */
+
+	mov	pc, lr
+	.size	up_lowsetup, . - up_lowsetup
+	.end

arch/arm/src/lpc214x/lpc214x_serial.c

@@ -0,0 +1,712 @@
+/****************************************************************************
+ * lpc214x/lpc214x_serial.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <unistd.h>
+#include <semaphore.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/serial.h>
+#include <arch/serial.h>
+
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+
+#include "lpc214x_uart.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+#define BASE_BAUD 115200
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct up_dev_s
+{
+  uint32  uartbase;  /* Base address of UART registers */
+  uint32  baud;      /* Configured baud */
+  ubyte   ier;       /* Saved IER value */
+  ubyte   irq;       /* IRQ associated with this UART */
+  ubyte   parity;    /* 0=none, 1=odd, 2=even */
+  ubyte   bits;      /* Number of bits (7 or 8) */
+  boolean stopbits2; /* TRUE: Configure with 2 stop bits instead of 1 */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int     up_setup(struct uart_dev_s *dev);
+static void    up_shutdown(struct uart_dev_s *dev);
+static int     up_interrupt(int irq, void *context);
+static int     up_ioctl(struct file *filep, int cmd, unsigned long arg);
+static int     up_receive(struct uart_dev_s *dev, uint32 *status);
+static void    up_rxint(struct uart_dev_s *dev, boolean enable);
+static boolean up_rxfifonotempty(struct uart_dev_s *dev);
+static void    up_send(struct uart_dev_s *dev, int ch);
+static void    up_txint(struct uart_dev_s *dev, boolean enable);
+static boolean up_txfifonotfull(struct uart_dev_s *dev);
+static boolean up_txfifoempty(struct uart_dev_s *dev);
+
+/****************************************************************************
+ * Private Variables
+ ****************************************************************************/
+
+struct uart_ops_s g_uart_ops =
+{
+  .setup          = up_setup,
+  .shutdown       = up_shutdown,
+  .handler        = up_interrupt,
+  .ioctl          = up_ioctl,
+  .receive        = up_receive,
+  .rxint          = up_rxint,
+  .rxfifonotempty = up_rxfifonotempty,
+  .send           = up_send,
+  .txint          = up_txint,
+  .txfifonotfull  = up_txfifonotfull,
+  .txfifoempty    = up_txfifoempty,
+};
+
+/* I/O buffers */
+
+static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE];
+static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+/* This describes the state of the LPC214X uart0 port. */
+
+static struct up_dev_s g_uart0priv =
+{
+  .uartbase       = LPC214X_UART0_BASE,
+  .baud           = CONFIG_UART0_BAUD,
+  .parity         = CONFIG_UART0_PARITY,
+  .bits           = CONFIG_UART0_BITS,
+  .stopbits2      = CONFIG_UART0_2STOP,
+};
+
+static uart_dev_t g_uart0port =
+{
+  .irq      = LPC214X_UART0_IRQ,
+  .recv     =
+  {
+    .size   = CONFIG_UART0_RXBUFSIZE,
+    .buffer = g_uart0rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART0_TXBUFSIZE,
+    .buffer = g_uart0txbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart0priv,
+};
+
+/* This describes the state of the LPC214X uart1 port. */
+
+static struct up_dev_s g_uart1priv =
+{
+  .uartbase       = LPC214X_UART1_BASE,
+  .baud           = CONFIG_UART1_BAUD,
+  .parity         = CONFIG_UART1_PARITY,
+  .bits           = CONFIG_UART1_BITS,
+  .stopbits2      = CONFIG_UART1_2STOP,
+};
+
+static uart_dev_t g_uart1port =
+{
+  .irq      = LPC214X_UART1_IRQ,
+  .recv     =
+  {
+    .size   = CONFIG_UART1_RXBUFSIZE,
+    .buffer = g_uart1rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART1_TXBUFSIZE,
+    .buffer = g_uart1txbuffer,
+   },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart1priv,
+};
+
+/* Now, which one with be tty0/console and which tty1? */
+
+#ifdef CONFIG_SERIAL_IRDA_CONSOLE
+# define CONSOLE_DEV     g_uart1port
+# define TTYS0_DEV       g_uart1port
+# define TTYS1_DEV       g_uart0port
+#else
+# define CONSOLE_DEV     g_uart0port
+# define TTYS0_DEV       g_uart0port
+# define TTYS1_DEV       g_uart1port
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_serialin
+ ****************************************************************************/
+
+static inline ubyte up_serialin(struct up_dev_s *priv, int offset)
+{
+  return getreg16(priv->uartbase + offset);
+}
+
+/****************************************************************************
+ * Name: up_serialout
+ ****************************************************************************/
+
+static inline void up_serialout(struct up_dev_s *priv, int offset, ubyte value)
+{
+  putreg16(value, priv->uartbase + offset);
+}
+
+/****************************************************************************
+ * Name: up_disableuartint
+ ****************************************************************************/
+
+static inline void up_disableuartint(struct up_dev_s *priv, ubyte *ier)
+{
+  if (ier)
+    {
+      *ier = priv->ier & LPC214X_IER_ALLIE;
+    }
+
+  priv->ier &= ~LPC214X_IER_ALLIE;
+  up_serialout(priv, LPC214X_UART_IER_OFFSET, priv->ier);
+}
+
+/****************************************************************************
+ * Name: up_restoreuartint
+ ****************************************************************************/
+
+static inline void up_restoreuartint(struct up_dev_s *priv, ubyte ier)
+{
+  priv->ier |= ier & LPC214X_IER_ALLIE;
+  up_serialout(priv, LPC214X_UART_IER_OFFSET, priv->ier);
+}
+
+/****************************************************************************
+ * Name: up_waittxfifonotfull
+ ****************************************************************************/
+
+static inline void up_waittxfifonotfull(struct up_dev_s *priv)
+{
+  int tmp;
+
+  /* Limit how long we will wait for the TX available condition */
+  for (tmp = 1000 ; tmp > 0 ; tmp--)
+    {
+      /* Check if the tranmitter holding register (THR) is empty */
+      if ((up_serialin(priv, LPC214X_UART_LSR_OFFSET) & LPC214X_LSR_THRE) != 0)
+        {
+          /* The THR is empty, return */
+          break;
+        }
+    }
+}
+
+/****************************************************************************
+ * Name: up_enablebreaks
+ ****************************************************************************/
+
+static inline void up_enablebreaks(struct up_dev_s *priv, boolean enable)
+{
+  ubyte lcr = up_serialin(priv, LPC214X_UART_LCR_OFFSET);
+  if (enable)
+    {
+      lcr |= LPC214X_LCR_BREAK_ENABLE;
+    }
+  else
+    {
+      lcr &= ~LPC214X_LCR_BREAK_ENABLE;
+    }
+  up_serialout(priv, LPC214X_UART_LCR_OFFSET, lcr);
+}
+
+/****************************************************************************
+ * Name: up_setup
+ *
+ * Description:
+ *   Configure the UART baud, bits, parity, fifos, etc. This
+ *   method is called the first time that the serial port is
+ *   opened.
+ *
+ ****************************************************************************/
+
+static int up_setup(struct uart_dev_s *dev)
+{
+#ifdef CONFIG_SUPPRESS_LPC214X_UART_CONFIG
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  uint16 baud;
+  ubyte lcr;
+
+  /* Clear fifos */
+
+  up_serialout(priv, LPC214X_UART_FCR_OFFSET, (LPC214X_FCR_RX_FIFO_RESET|LPC214X_FCR_TX_FIFO_RESET));
+ 
+  /* Set trigger */
+
+  up_serialout(priv, LPC214X_UART_FCR_OFFSET, (LPC214X_FCR_FIFO_ENABLE|LPC214X_FCR_FIFO_TRIG14));
+
+  /* Set up the IER */
+
+  priv->ier = up_serialin(priv, LPC214X_UART_IER_OFFSET);
+  
+  /* Set up the LCR */
+  
+  lcr = 0;
+  
+  if (priv->bits == 7)
+    {
+      lcr |= LPC214X_LCR_CHAR_7;
+    }
+  else
+    {
+      lcr |= LPC214X_LCR_CHAR_8;
+    }
+
+  if (priv->stopbits2)
+    {
+      lcr |= LPC214X_LCR_STOP_2;
+    }
+ 
+  if (priv->parity == 1)
+    {
+      lcr |= LPC214X_LCR_PAR_ODD;
+    }
+  else if (priv->parity == 2)
+    {
+      lcr |= LPC214X_LCR_PAR_EVEN;
+    }
+
+  /* Enter DLAB=1 */
+    
+  up_serialout(priv, LPC214X_UART_LCR_OFFSET, (lcr | LPC214X_LCR_DLAB_ENABLE));
+ 
+  /* Set the BAUD divisor */
+
+  baud = UART_BAUD(priv->baud);
+  up_serialout(priv, LPC214X_UART_DLM_OFFSET, baud >> 8);
+  up_serialout(priv, LPC214X_UART_DLL_OFFSET, baud & 0xff);
+ 
+  /* Clear DLAB */
+
+ up_serialout(priv, LPC214X_UART_LCR_OFFSET, lcr);
+#endif
+  return OK;
+}
+
+/****************************************************************************
+ * Name: up_shutdown
+ *
+ * Description:
+ *   Disable the UART.  This method is called when the serial
+ *   port is closed
+ *
+ ****************************************************************************/
+
+static void up_shutdown(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_disableuartint(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: up_interrupt
+ *
+ * Description:
+ *   This is the UART interrupt handler.  It will be invoked
+ *   when an interrupt received on the 'irq'  It should call
+ *   uart_transmitchars or uart_receivechar to perform the
+ *   appropriate data transfers.  The interrupt handling logic\
+ *   must be able to map the 'irq' number into the approprite
+ *   uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int up_interrupt(int irq, void *context)
+{
+  struct uart_dev_s *dev = NULL;
+  struct up_dev_s   *priv;
+  ubyte              status;
+  int                passes;
+
+  if (g_uart1port.irq == irq)
+    {
+      dev = &g_uart1port;
+    }
+  else if (g_uart0port.irq == irq)
+    {
+      dev = &g_uart0port;
+    }
+  else
+    {
+      PANIC(OSERR_INTERNAL);
+    }
+  priv = (struct up_dev_s*)dev->priv;
+
+  /* Loop until there are no characters to be transferred or,
+   * until we have been looping for a long time.
+   */
+
+  for( passes = 0; passes < 256; passes++)
+    {
+      /* Get the current UART status and check for loop
+       * termination conditions
+       */
+
+       status  = up_serialin(priv, LPC214X_UART_IIR_OFFSET);
+      
+      /* The NO INTERRUPT should be zero */
+      
+      if (status  !=  LPC214X_IIR_NO_INT)
+        {
+          /* Handline incoming, receive bytes (with or without timeout) */
+
+          if (status == LPC214X_IIR_RDA_INT || status == LPC214X_IIR_CTI_INT)
+            {
+              uart_recvchars(dev);
+            }
+
+          /* Handle outgoing, transmit bytes */
+
+          else if (status == LPC214X_IIR_THRE_INT)
+            {
+              uart_xmitchars(dev);
+            }
+
+          /* Just clear modem status interrupts */
+        
+          else if (status == LPC214X_IIR_MS_INT)
+           {
+             /* Read the modem status regisgter (MSR) to clear */
+            
+             (void)up_serialin(priv, LPC214X_UART_MSR_OFFSET);
+           }
+
+          /* Just clear any line status interrupts */
+        
+          else if (status == LPC214X_IIR_RLS_INT)
+            {
+              /* Read the line status register (LSR) to clear */
+            
+              (void)up_serialin(priv, LPC214X_UART_LSR_OFFSET);
+            }
+        }
+    }
+    return OK;
+}
+
+/****************************************************************************
+ * Name: up_ioctl
+ *
+ * Description:
+ *   All ioctl calls will be routed through this method
+ *
+ ****************************************************************************/
+
+static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+  struct inode      *inode = filep->f_inode;
+  struct uart_dev_s *dev   = inode->i_private;
+  struct up_dev_s   *priv  = (struct up_dev_s*)dev->priv;
+  int                ret    = OK;
+
+  switch (cmd)
+    {
+    case TIOCSERGSTRUCT:
+      {
+         struct up_dev_s *user = (struct up_dev_s*)arg;
+         if (!user)
+           {
+             *get_errno_ptr() = EINVAL;
+             ret = ERROR;
+           }
+         else
+           {
+             memcpy(user, dev, sizeof(struct up_dev_s));
+           }
+       }
+       break;
+
+    case TIOCSBRK:  /* BSD compatibility: Turn break on, unconditionally */
+      {
+        irqstate_t flags = irqsave();
+        up_enablebreaks(priv, TRUE);
+        irqrestore(flags);
+      }
+      break;
+
+    case TIOCCBRK:  /* BSD compatibility: Turn break off, unconditionally */
+      {
+        irqstate_t flags;
+        flags = irqsave();
+        up_enablebreaks(priv, FALSE);
+        irqrestore(flags);
+      }
+      break;
+
+    default:
+      *get_errno_ptr() = ENOTTY;
+      ret = ERROR;
+      break;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: up_receive
+ *
+ * Description:
+ *   Called (usually) from the interrupt level to receive one
+ *   character from the UART.  Error bits associated with the
+ *   receipt are provided in the the return 'status'.
+ *
+ ****************************************************************************/
+
+static int up_receive(struct uart_dev_s *dev, uint32 *status)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  ubyte rbr;
+
+  rbr     = up_serialin(priv, LPC214X_UART_RBR_OFFSET);
+  *status = up_serialin(priv, LPC214X_UART_RBR_OFFSET);
+  return rbr;
+}
+
+/****************************************************************************
+ * Name: up_rxint
+ *
+ * Description:
+ *   Call to enable or disable RX interrupts
+ *
+ ****************************************************************************/
+
+static void up_rxint(struct uart_dev_s *dev, boolean enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  if (enable)
+    {
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      priv->ier |= LPC214X_IER_ERBFI;
+#endif
+    }
+  else
+    {
+      priv->ier &= ~LPC214X_IER_ERBFI;
+    }
+  up_serialout(priv, LPC214X_UART_IER_OFFSET, priv->ier);
+}
+
+/****************************************************************************
+ * Name: up_rxfifonotempty
+ *
+ * Description:
+ *   Return TRUE if the receive fifo is not empty
+ *
+ ****************************************************************************/
+
+static boolean up_rxfifonotempty(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, LPC214X_UART_LSR_OFFSET) & LPC214X_LSR_RDR) != 0);
+}
+
+/****************************************************************************
+ * Name: up_send
+ *
+ * Description:
+ *   This method will send one byte on the UART
+ *
+ ****************************************************************************/
+
+static void up_send(struct uart_dev_s *dev, int ch)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_serialout(priv, LPC214X_UART_THR_OFFSET, (ubyte)ch);
+}
+
+/****************************************************************************
+ * Name: up_txint
+ *
+ * Description:
+ *   Call to enable or disable TX interrupts
+ *
+ ****************************************************************************/
+
+static void up_txint(struct uart_dev_s *dev, boolean enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  if (enable)
+    {
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      priv->ier |= LPC214X_IER_ETBEI;
+#endif
+    }
+  else
+    {
+      priv->ier &= ~LPC214X_IER_ETBEI;
+    }
+  up_serialout(priv, LPC214X_UART_IER_OFFSET, priv->ier);
+}
+
+/****************************************************************************
+ * Name: up_txfifonotfull
+ *
+ * Description:
+ *   Return TRUE if the tranmsit fifo is not full
+ *
+ ****************************************************************************/
+
+static boolean up_txfifonotfull(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, LPC214X_UART_LSR_OFFSET) & LPC214X_LSR_THRE) != 0);
+}
+
+/****************************************************************************
+ * Name: up_txfifoempty
+ *
+ * Description:
+ *   Return TRUE if the transmit fifo is empty
+ *
+ ****************************************************************************/
+
+static boolean up_txfifoempty(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, LPC214X_UART_LSR_OFFSET) & LPC214X_LSR_THRE) != 0);
+}
+
+/****************************************************************************
+ * Public Funtions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Performs the low level UART initialization early in 
+ *   debug so that the serial console will be available
+ *   during bootup.  This must be called before up_serialinit.
+ *
+ ****************************************************************************/
+
+void up_earlyserialinit(void)
+{
+  /* Enable UART0 and 1 */
+  
+  uint32 pinsel = getreg32(LPC214X_PINSEL0);
+  pinsel &= ~(LPC214X_UART0_PINMASK|LPC214X_UART1_PINMASK);
+  pinsel |= (LPC214X_UART0_PINSEL|LPC214X_UART1_PINSEL);
+  putreg32(pinsel, LPC214X_PINSEL0);
+
+  /* Disable both UARTS */
+  
+  up_disableuartint(TTYS0_DEV.priv, NULL);
+  up_disableuartint(TTYS1_DEV.priv, NULL);
+
+  /* Configuration whichever on is the console */
+  
+  CONSOLE_DEV.isconsole = TRUE;
+  up_setup(&CONSOLE_DEV);
+}
+
+/****************************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Register serial console and serial ports.  This assumes
+ *   that up_earlyserialinit was called previously.
+ *
+ ****************************************************************************/
+
+void up_serialinit(void)
+{
+  (void)uart_register("/dev/console", &CONSOLE_DEV);
+  (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+  (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+}
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug
+ *   writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
+  ubyte  ier;
+
+  up_disableuartint(priv, &ier);
+  up_waittxfifonotfull(priv);
+  up_serialout(priv, LPC214X_UART_THR_OFFSET, (ubyte)ch);
+
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      up_waittxfifonotfull(priv);
+      up_serialout(priv, LPC214X_UART_THR_OFFSET, '\r');
+    }
+
+  up_waittxfifonotfull(priv);
+  up_restoreuartint(priv, ier);
+  return ch;
+}
+

arch/arm/src/lpc214x/lpc214x_timer.h

@@ -0,0 +1,152 @@
+/************************************************************************************
+ * lpc214x/lpc214x_timer.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __LPC214X_TIMER_H
+#define __LPC214X_TIMER_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Timer registers are 8-, 16-bit and 32-bits wide */
+
+/* Timer Interrupt Register Bit Definitions (8-bit) */
+
+#define LPC214X_TMR_IR_MR0I          (1 << 0)  /* Interrupt flag for match channel 0 */
+#define LPC214X_TMR_IR_MR1I          (1 << 1)  /* Interrupt flag for match channel 1 */
+#define LPC214X_TMR_IR_MR2I          (1 << 2)  /* Interrupt flag for match channel 2 */
+#define LPC214X_TMR_IR_MR3I          (1 << 3)  /* Interrupt flag for match channel 3 */
+#define LPC214X_TMR_IR_CR0I          (1 << 4)  /* Interrupt flag for capture channel 0 event */
+#define LPC214X_TMR_IR_CR1I          (1 << 5)  /* Interrupt flag for capture channel 1 event */
+#define LPC214X_TMR_IR_CR2I          (1 << 6)  /* Interrupt flag for capture channel 2 event */
+#define LPC214X_TMR_IR_CR3I          (1 << 7)  /* Interrupt flag for capture channel 3 event */
+#define LPC214X_TMR_IR_ALLI          (0xff)    /* All timer interrupts */
+
+/* Timer Control Register Bit Definitions (8-bits) */
+
+#define LPC214X_TMR_CR_ENABLE        (1 << 0)  /* Counter Enable */
+#define LPC214X_TMR_CR_RESET         (1 << 1)  /* Countger Reset */
+
+/* Timer Counter (32-bits, no bit fields) */
+
+/* Timer Prescale Register Bit Definitions (32-bits, no bit fields) */
+
+/* Timer Prescale Counter Register Bit Definitions */
+
+/* Timer Match Control Register Bit Definitions (16-bit) */
+
+#define LPC214X_TMR_MCR_MR0I         (1 <<  0) /* Enable Interrupt when MR0 matches TC */
+#define LPC214X_TMR_MCR_MR0R         (1 <<  1) /* Enable Reset of TC upon MR0 match */
+#define LPC214X_TMR_MCR_MR0S         (1 <<  2) /* Enable Stop of TC upon MR0 match */
+#define LPC214X_TMR_MCR_MR1I         (1 <<  3) /* Enable Interrupt when MR1 matches TC */
+#define LPC214X_TMR_MCR_MR1R         (1 <<  4) /* Enable Reset of TC upon MR1 match */
+#define LPC214X_TMR_MCR_MR1S         (1 <<  5) /* Enable Stop of TC upon MR1 match */
+#define LPC214X_TMR_MCR_MR2I         (1 <<  6) /* Enable Interrupt when MR2 matches TC */
+#define LPC214X_TMR_MCR_MR2R         (1 <<  7) /* Enable Reset of TC upon MR2 match */
+#define LPC214X_TMR_MCR_MR2S         (1 <<  8) /* Enable Stop of TC upon MR2 match */
+#define LPC214X_TMR_MCR_MR3I         (1 <<  9) /* Enable Interrupt when MR3 matches TC */
+#define LPC214X_TMR_MCR_MR3R         (1 << 10) /* Enable Reset of TC upon MR3 match */
+#define LPC214X_TMR_MCR_MR3S         (1 << 11) /* Enable Stop of TC upon MR3 match */
+
+/* Timer Match Register 0/1/2/3 (32-bits, no bit fields) */
+
+/* Timer Capture Control Register Bit Definitions */
+
+#define LPC214X_TMR_CCR_CAP0RE       (1 <<  0) /* Enable Rising edge on CAPn.0 will load TC to CR0 */
+#define LPC214X_TMR_CCR_CAP0FE       (1 <<  1) /* Enable Falling edge on CAPn.0 will load TC to CR0 */
+#define LPC214X_TMR_CCR_CAP0I        (1 <<  2) /* Enable Interrupt on load of CR0 */
+#define LPC214X_TMR_CCR_CAP1RE       (1 <<  3) /* Enable Rising edge on CAPn.1 will load TC to CR1 */
+#define LPC214X_TMR_CCR_CAP1FE       (1 <<  4) /* Enable Falling edge on CAPn.1 will load TC to CR1 */
+#define LPC214X_TMR_CCR_CAP1I        (1 <<  5) /* Enable Interrupt on load of CR1 */
+#define LPC214X_TMR_CCR_CAP2RE       (1 <<  6) /* Enable Rising edge on CAPn.2 will load TC to CR2 */
+#define LPC214X_TMR_CCR_CAP2FE       (1 <<  7) /* Enable Falling edge on CAPn.2 will load TC to CR2 */
+#define LPC214X_TMR_CCR_CAP2I        (1 <<  8) /* Enable Interrupt on load of CR2 */
+#define LPC214X_TMR_CCR_CAP3RE       (1 <<  9) /* Enable Rising edge on CAPn.3 will load TC to CR3 */
+#define LPC214X_TMR_CCR_CAP3FE       (1 << 10) /* Enable Falling edge on CAPn.3 will load TC to CR3 */
+#define LPC214X_TMR_CCR_CAP3I        (1 << 11) /* Enable Interrupt on load of CR3 */
+
+/* Timer Capture Register 0/1/2/3 (32-bits, no bit fields) */
+
+/* Timer External Match Register Bit Definitions */
+
+#define LPC214X_TMR_EMR_EM0          (1 <<  0) /* External Match 0 */
+#define LPC214X_TMR_EMR_EM1          (1 <<  1) /* External Match 1 */
+#define LPC214X_TMR_EMR_EM2          (1 <<  2) /* External Match 2 */
+#define LPC214X_TMR_EMR_EM3          (1 <<  3) /* External Match 3 */
+
+#define LPC214X_TMR_EMR_EMC0(b)      ((b) <<  4)  /* External match control 0 (see below) */
+#define LPC214X_TMR_EMR_EMC1(b)      ((b) <<  6)  /* External match control 1 (see below) */
+#define LPC214X_TMR_EMR_EMC2(b)      ((b) <<  8)  /* External match control 2 (see below) */
+#define LPC214X_TMR_EMR_EMC3(b)      ((b) << 10)  /* External match control 3 (see below) */
+
+/* EMR External Match Control (EMCn) Field Falues */
+
+#define LPC214X_TMR_EMR_MASK         (3)       /* Mask for all bits */
+#define LPC214X_TMR_EMR_NOOP         (0)       /* Do nothing */
+#define LPC214X_TMR_EMR_CLEAR        (1)       /* Clear corresponding EMn bit/output to 0 */
+#define LPC214X_TMR_EMR_SET          (2)       /* Set corresponding EMn bit/output to 1 */
+#define LPC214X_TMR_EMR_TOGGLE       (3)       /* Toggle corresponding EMn bit/output */
+
+/* Timer Count Control Register Bit Definitions (8-bit) */
+
+#define LPC214X_TMR_
+#define LPC214X_TMR_CTCR_MODE_MASK   (3 << 0) /* Counter/Timer Mode */
+#define   LPC214X_TMR_CTCR_PCLK      (0 << 0) /*   Rising edge of PCLK */
+#define   LPC214X_TMR_CTCR_RISING    (1 << 0) /*   Rising edge of CAP input */
+#define   LPC214X_TMR_CTDR_FALLING   (2 << 0) /*   Failing edge of CAP input */
+#define   LPC214X_TMR_CTCR_BOTH      (3 << 0) /*   Both edges of CAP input */
+#define LPC214X_TMR_CTCR_INPUT_MASK  (3 << 2) /* Counter Input Select */
+#define   LPC214X_TMR_CTCR_CR0       (0 << 2) /*   CAPn.0 */
+#define   LPC214X_TMR_CTCR_CR1       (1 << 2) /*   CAPn.1 */
+#define   LPC214X_TMR_CTCR_CR2       (2 << 2) /*   CAPn.2 */
+#define   LPC214X_TMR_CTCR_CR3       (3 << 2) /*   CAPn.3 */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif  /* __LPC214X_TIMER_H */

arch/arm/src/lpc214x/lpc214x_timerisr.c

@@ -0,0 +1,162 @@
+/************************************************************
+ * lpc214x/lpc214x_timerisr.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+
+#include "clock_internal.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "lpc214x_timer.h"
+#include "lpc214x_vic.h"
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+#define PCLKFREQ (LPC214X_FOSC/4) /* PCLK must be FOSC/4 */
+
+#define tmr_getreg8(o)    getreg8(LPC214X_TMR0_BASE+(o))
+#define tmr_getreg16(o)   getreg16(LPC214X_TMR0_BASE+(o))
+#define tmr_getreg32(o)   getreg32(LPC214X_TMR0_BASE+(o))
+
+#define tmr_putreg8(o,v)  putreg8((v), LPC214X_TMR0_BASE+(o))
+#define tmr_putreg16(o,v) putreg16((v), LPC214X_TMR0_BASE+(o))
+#define tmr_putreg32(o,v) putreg32((v), LPC214X_TMR0_BASE+(o))
+
+/************************************************************
+ * Private Types
+ ************************************************************/
+
+/************************************************************
+ * Private Function Prototypes
+ ************************************************************/
+
+/************************************************************
+ * Global Functions
+ ************************************************************/
+
+/************************************************************
+ * Function:  up_timerisr
+ *
+ * Description:
+ *   The timer ISR will perform a variety of services for
+ *   various portions of the systems.
+ *
+ ************************************************************/
+
+#ifdef CONFIG_VECTORED_INTERRUPTS
+int up_timerisr(uint32 *regs)
+#else
+int up_timerisr(int irq, uint32 *regs)
+#endif
+{
+   /* Process timer interrupt */
+
+   sched_process_timer();
+
+   /* Clear the MR0 match interrupt */
+
+   tmr_putreg8(LPC214X_TMR_IR_MR0I, LPC214X_TMR_IR_OFFSET);
+
+   /* Reset the VIC as well */
+
+#ifdef CONFIG_VECTORED_INTERRUPTS
+   vic_putreg(0, LPC214X_VIC_VECTADDR_OFFSET);
+#endif
+   return 0;
+}
+
+/************************************************************
+ * Function:  up_timerinit
+ *
+ * Description:
+ *   This function is called during start-up to initialize
+ *   the timer interrupt.
+ *
+ ************************************************************/
+
+void up_timerinit(void)
+{
+  uint16 mcr;
+
+  /* Clear all match and capture event interrupts */
+
+  tmr_putreg8(LPC214X_TMR_IR_ALLI, LPC214X_TMR_IR_OFFSET);
+
+  /* Clear the timer counter */
+
+  tmr_putreg32(0, LPC214X_TMR_TC_OFFSET);
+
+  /* No pre-scaler */
+
+  tmr_putreg32(0, LPC214X_TMR_PR_OFFSET);
+
+  /* Set timer match registger to get a TICK_PER_SEC rate
+   * See arch/board.h and sched/os_internal.h
+   */
+
+  tmr_putreg32(LPC214X_PCLKFREQ/TICK_PER_SEC, LPC214X_TMR_MR0_OFFSET);
+
+  /* Reset timer counter regiser and interrupt on match */
+  mcr = tmr_getreg16(LPC214X_TMR_MCR_OFFSET);
+  mcr &= ~LPC214X_TMR_MCR_MR1I;
+  mcr |= (LPC214X_TMR_MCR_MR0I | LPC214X_TMR_MCR_MR0R);
+  tmr_putreg16(mcr, LPC214X_TMR_MCR_OFFSET);
+
+  /* Enable counting */
+
+  tmr_putreg8(LPC214X_TMR_CR_ENABLE, LPC214X_TMR_TCR_OFFSET);
+
+  /* Attach the timer interrupt vector */
+
+#ifdef CONFIG_VECTORED_INTERRUPTS
+  up_attach_vector(LPC214X_IRQ_SYSTIMER, LPC214X_SYSTEMER_VEC, (vic_vector_t)up_timerisr);
+#else
+  (void)irq_attach(LPC214X_IRQ_SYSTIMER, (xcpt_t)up_timerisr);
+#endif
+
+  /* And enable the timer interrupt */
+
+  up_enable_irq(LPC214X_IRQ_SYSTIMER);
+}

arch/arm/src/lpc214x/lpc214x_uart.h

@@ -0,0 +1,142 @@
+/************************************************************************************
+ * lpc214x/uart.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __LPC214X_UART_H
+#define __LPC214X_UART_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <arch/board/board.h> /* For clock settings */
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* PINSEL0 bit definitions for UART0/1 */
+
+#define LPC214X_UART0_PINSEL       0x00000005  /* PINSEL0 value for UART0 */
+#define LPC214X_UART0_PINMASK      0x0000000f  /* PINSEL0 mask for UART0 */
+
+#define LPC214X_UART1_PINSEL       0x00050000  /* PINSEL0 value for UART1 */
+#define LPC214X_UART1_PINMASK      0x000f0000  /* PINSEL0 mask for UART1 */
+
+/* Derive baud divisor setting from clock settings (see board.h) */
+
+#define UART_BAUD(baud)            ((LPC214X_FOSC * LPC214X_PLL_M) / (baud * 16))
+
+/* Interrupt Enable Register (IER) bit definitions */
+
+#define LPC214X_IER_ERBFI          (1 << 0)    /* Enable receive data available int */
+#define LPC214X_IER_ETBEI          (1 << 1)    /* Enable THR empty Interrupt */
+#define LPC214X_IER_ELSI           (1 << 2)    /* Enable receive line status int */
+#define LPC214X_IER_EDSSI          (1 << 3)    /* Enable MODEM atatus interrupt (2146/6/8 UART1 Only) */
+#define LPC214X_IER_ALLIE          0x0f        /* All interrupts */
+
+/* Interrupt ID Register(IIR) bit definitions */
+
+#define LPC214X_IIR_NO_INT         (1 << 0)    /* No interrupts pending  */
+#define LPC214X_IIR_MS_INT         (0 << 1)    /* MODEM Status */
+#define LPC214X_IIR_THRE_INT       (1 << 1)    /* Transmit Holding Register Empty */
+#define LPC214X_IIR_RDA_INT        (2 << 1)    /* Receive Data Available */
+#define LPC214X_IIR_RLS_INT        (3 << 1)    /* Receive Line Status */
+#define LPC214X_IIR_CTI_INT        (6 << 1)    /* Character Timeout Indicator */
+#define LPC214X_IIR_MASK           0x0e
+
+/* FIFO Control Register (FCR) bit definitions */
+
+#define LPC214X_FCR_FIFO_ENABLE    (1 << 0)    /* FIFO wnable */
+#define LPC214X_FCR_RX_FIFO_RESET  (1 << 1)    /* Reset receive FIFO */
+#define LPC214X_FCR_TX_FIFO_RESET  (1 << 2)    /* Reset transmit FIFO */
+#define LPC214X_FCR_FIFO_TRIG1     (0 << 6)    /* Trigger @1 character in FIFO */
+#define LPC214X_FCR_FIFO_TRIG4     (1 << 6)    /* Trigger @4 characters in FIFO */
+#define LPC214X_FCR_FIFO_TRIG8     (2 << 6)    /* Trigger @8 characters in FIFO */
+#define LPC214X_FCR_FIFO_TRIG14    (3 << 6)    /* Trigger @14 characters in FIFO */
+
+/* Line Control Register (LCR) bit definitions */
+
+#define LPC214X_LCR_CHAR_5         (0 << 0)    /* 5-bit character length */
+#define LPC214X_LCR_CHAR_6         (1 << 0)    /* 6-bit character length */
+#define LPC214X_LCR_CHAR_7         (2 << 0)    /* 7-bit character length */
+#define LPC214X_LCR_CHAR_8         (3 << 0)    /* 8-bit character length */
+#define LPC214X_LCR_STOP_1         (0 << 2)    /* 1 stop bit */
+#define LPC214X_LCR_STOP_2         (1 << 2)    /* 2 stop bits */
+#define LPC214X_LCR_PAR_NONE       (0 << 3)    /* No parity */
+#define LPC214X_LCR_PAR_ODD        (1 << 3)    /* Odd parity */
+#define LPC214X_LCR_PAR_EVEN       (3 << 3)    /* Even parity */
+#define LPC214X_LCR_PAR_MARK       (5 << 3)    /* Mark "1" parity */
+#define LPC214X_LCR_PAR_SPACE      (7 << 3)    /* Space "0" parity */
+#define LPC214X_LCR_BREAK_ENABLE   (1 << 6)    /* Output BREAK */
+#define LPC214X_LCR_DLAB_ENABLE    (1 << 7)    /* Enable divisor latch access */
+
+/* Modem Control Register (MCR) bit definitions */
+
+#define LPC214X_MCR_DTR            (1 << 0)    /* Data terminal ready */
+#define LPC214X_MCR_RTS            (1 << 1)    /* Request to send */
+#define LPC214X_MCR_LB             (1 << 4)    /* Loopback */
+
+/* Line Status Register (LSR) bit definitions */
+
+#define LPC214X_LSR_RDR            (1 << 0)    /* Receive data ready */
+#define LPC214X_LSR_OE             (1 << 1)    /* Overrun error */
+#define LPC214X_LSR_PE             (1 << 2)    /* Parity error */
+#define LPC214X_LSR_FE             (1 << 3)    /* Framing error */
+#define LPC214X_LSR_BI             (1 << 4)    /* Break interrupt */
+#define LPC214X_LSR_THRE           (1 << 5)    /* THR empty */
+#define LPC214X_LSR_TEMT           (1 << 6)    /* Transmitter empty */
+#define LPC214X_LSR_RXFE           (1 << 7)    /* Error in receive FIFO */
+#define LPC214X_LSR_ERR_MASK       0x1e
+
+/* Modem Status Register (MSR) bit definitions */
+
+#define LPC214X_MSR_DCTS           (1 << 0)    /* Delta clear to send */
+#define LPC214X_MSR_DDSR           (1 << 1)    /* Delta data set ready */
+#define LPC214X_MSR_TERI           (1 << 2)    /* Trailing edge ring indicator */
+#define LPC214X_MSR_DDCD           (1 << 3)    /* Delta data carrier detect */
+#define LPC214X_MSR_CTS            (1 << 4)    /* Clear to send */
+#define LPC214X_MSR_DSR            (1 << 5)    /* Data set ready */
+#define LPC214X_MSR_RI             (1 << 6)    /* Ring indicator */
+#define LPC214X_MSR_DCD            (1 << 7)    /* Data carrier detect */
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Global Function Prototypes
+ ************************************************************************************/
+
+#endif  /* __LPC214X_UART_H */

arch/arm/src/lpc214x/lpc214x_vic.h

@@ -0,0 +1,70 @@
+/************************************************************************************
+ * lpc214x/lpc214x_vic.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __LPC214X_VIC_H
+#define __LPC214X_VIC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* All VIC registers are 32-bits wide */
+
+#define vic_getreg(o)   getreg32(LPC214X_VIC_BASE+(o))
+#define vic_putreg(v,o) putreg32((v),LPC214X_VIC_BASE+(o))
+
+/* Vector Control Register bit definitions */
+
+#define LPC214X_VECTCNTL_IRQMASK  (0x0000001f)
+#define LPC214X_VECTCNTL_IRQSHIFT (0)
+#define LPC214X_VECTCNTL_ENABLE   (1 << 5)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif  /* __LPC214X_VIC_H */

arch/c5471/include/arch.h

@@ -1,5 +1,5 @@
 /************************************************************
- * arch.h
+ * arch/arch.h
  *
  *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@@ -37,8 +37,8 @@
  * only indirectly through nuttx/arch.h
  */
 
-#ifndef __ARCH_C5471_ARCH_H
-#define __ARCH_C5471_ARCH_H
+#ifndef __ARCH_ARCH_H
+#define __ARCH_ARCH_H
 
 /************************************************************
  * Included Files
@@ -76,5 +76,5 @@ extern "C" {
 }
 #endif
 
-#endif /* __ARCH_C5471_ARCH_H */
+#endif /* __ARCH_ARCH_H */
 

arch/c5471/include/c5471/irq.h

@@ -0,0 +1,105 @@
+/************************************************************
+ * arch/c5471/irq.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/* This file should never be included directed but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_C5471_IRQ_H
+#define __ARCH_C5471_IRQ_H
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/* C5471 Interrupts */
+
+#define C5471_IRQ_TIMER0         0
+#define C5471_IRQ_TIMER1         1
+#define C5471_IRQ_TIMER2         2
+#define C5471_IRQ_GPIO0          3
+#define C5471_IRQ_ETHER          4
+#define C5471_IRQ_KBGPIO_0_7     5
+#define C5471_IRQ_UART           6
+#define C5471_IRQ_UART_IRDA      7
+#define C5471_IRQ_KBGPIO_8_15    8
+#define C5471_IRQ_GPIO3          9
+#define C5471_IRQ_GPIO2         10
+#define C5471_IRQ_I2C           11
+#define C5471_IRQ_GPIO1         12
+#define C5471_IRQ_SPI           13
+#define C5471_IRQ_GPIO_4_19     14
+#define C5471_IRQ_API           15
+
+#define C5471_IRQ_WATCHDOG      C5471_IRQ_TIMER0
+#define C5471_IRQ_SYSTIMER      C5471_IRQ_TIMER2
+#define NR_IRQS                 (C5471_IRQ_API+1)
+
+/************************************************************
+ * Public Types
+ ************************************************************/
+
+/************************************************************
+ * Inline functions
+ ************************************************************/
+
+/************************************************************
+ * Public Variables
+ ************************************************************/
+
+/************************************************************
+ * Public Function Prototypes
+ ************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_C5471_IRQ_H */
+

arch/c5471/include/irq.h

@@ -1,5 +1,5 @@
 /************************************************************
- * irq.h
+ * arch/irq.h
  *
  *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@@ -37,13 +37,15 @@
  * only indirectly through nuttx/irq.h
  */
 
-#ifndef __ARCH_C5471_IRQ_H
-#define __ARCH_C5471_IRQ_H
+#ifndef __ARCH_IRQ_H
+#define __ARCH_IRQ_H
 
 /************************************************************
  * Included Files
  ************************************************************/
 
+#include <arch/chip/irq.h>
+
 /************************************************************
  * Definitions
  ************************************************************/
@@ -60,68 +62,45 @@
  * xcp.regs array:
  */
 
-#define REG_R0                   (0)
-#define REG_R1                   (1)
-#define REG_R2                   (2)
-#define REG_R3                   (3)
-#define REG_R4                   (4)
-#define REG_R5                   (5
-#define REG_R6                   (6)
-#define REG_R7                   (7)
-#define REG_R8                   (8)
-#define REG_R9                   (9)
-#define REG_R10                  (10)
-#define REG_R11                  (11)
-#define REG_R12                  (12)
-#define REG_R13                  (13)
-#define REG_R14                  (14)
-#define REG_R15                  (15)
-#define REG_CPSR                 (16)
+#define REG_R0              (0)
+#define REG_R1              (1)
+#define REG_R2              (2)
+#define REG_R3              (3)
+#define REG_R4              (4)
+#define REG_R5              (5)
+#define REG_R6              (6)
+#define REG_R7              (7)
+#define REG_R8              (8)
+#define REG_R9              (9)
+#define REG_R10             (10)
+#define REG_R11             (11)
+#define REG_R12             (12)
+#define REG_R13             (13)
+#define REG_R14             (14)
+#define REG_R15             (15)
+#define REG_CPSR            (16)
 
-#define XCPTCONTEST_REGS         (17)
-#define XCPTCONTEXT_SIZE         (4 * XCPTCONTEST_REGS)
+#define XCPTCONTEXT_REGS    (17)
+#define XCPTCONTEXT_SIZE    (4 * XCPTCONTEXT_REGS)
 
-#define REG_A1                   REG_R0
-#define REG_A2                   REG_R1
-#define REG_A3                   REG_R2
-#define REG_A4                   REG_R3
-#define REG_V1                   REG_R4
-#define REG_V2                   REG_R5
-#define REG_V3                   REG_R6
-#define REG_V4                   REG_R7
-#define REG_V5                   REG_R8
-#define REG_V6                   REG_R9
-#define REG_V7                   REG_R10
-#define REG_SB                   REG_R9
-#define REG_SL                   REG_R10
-#define REG_FP                   REG_R11
-#define REG_IP                   REG_R12
-#define REG_SP                   REG_R13
-#define REG_LR                   REG_R14
-#define REG_PC                   REG_R15
-
-/* C5471 Interrupts */
-
-#define C5471_IRQ_TIMER0         0
-#define C5471_IRQ_TIMER1         1
-#define C5471_IRQ_TIMER2         2
-#define C5471_IRQ_GPIO0          3
-#define C5471_IRQ_ETHER          4
-#define C5471_IRQ_KBGPIO_0_7     5
-#define C5471_IRQ_UART           6
-#define C5471_IRQ_UART_IRDA      7
-#define C5471_IRQ_KBGPIO_8_15    8
-#define C5471_IRQ_GPIO3          9
-#define C5471_IRQ_GPIO2         10
-#define C5471_IRQ_I2C           11
-#define C5471_IRQ_GPIO1         12
-#define C5471_IRQ_SPI           13
-#define C5471_IRQ_GPIO_4_19     14
-#define C5471_IRQ_API           15
-
-#define C5471_IRQ_WATCHDOG      C5471_IRQ_TIMER0
-#define C5471_IRQ_SYSTIMER      C5471_IRQ_TIMER2
-#define NR_IRQS                 (C5471_IRQ_API+1)
+#define REG_A1              REG_R0
+#define REG_A2              REG_R1
+#define REG_A3              REG_R2
+#define REG_A4              REG_R3
+#define REG_V1              REG_R4
+#define REG_V2              REG_R5
+#define REG_V3              REG_R6
+#define REG_V4              REG_R7
+#define REG_V5              REG_R8
+#define REG_V6              REG_R9
+#define REG_V7              REG_R10
+#define REG_SB              REG_R9
+#define REG_SL              REG_R10
+#define REG_FP              REG_R11
+#define REG_IP              REG_R12
+#define REG_SP              REG_R13
+#define REG_LR              REG_R14
+#define REG_PC              REG_R15
 
 /************************************************************
  * Public Types
@@ -144,7 +123,7 @@
  *---
  *  5	(XCPTCONTEXT_IRQ_REGS)
  *
- * For a total of 17 (XCPTCONTEST_REGS)
+ * For a total of 17 (XCPTCONTEXT_REGS)
  */
 
 #ifndef __ASSEMBLY__
@@ -165,7 +144,7 @@ struct xcptcontext
 
   /* Register save area */
 
-  uint32 regs[XCPTCONTEST_REGS];
+  uint32 regs[XCPTCONTEXT_REGS];
 };
 #endif
 
@@ -243,5 +222,5 @@ extern "C" {
 #endif
 #endif
 
-#endif /* __ARCH_C5471_IRQ_H */
+#endif /* __ARCH_IRQ_H */
 

arch/c5471/include/limits.h

@@ -0,0 +1,75 @@
+/************************************************************
+ * limits.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+#ifndef __ARCH_LIMITS_H
+#define __ARCH_LIMITS_H
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+#define CHAR_BIT        8
+#define SCHAR_MIN	0x80
+#define SCHAR_MAX	0x7f
+#define UCHAR_MAX	0xff
+
+/* These could be different on machines where char is unsigned */
+
+#define CHAR_MIN	SCHAR_MIN
+#define CHAR_MAX	SCHAR_MAX
+
+#define SHRT_MIN	0x8000
+#define SHRT_MAX	0x7fff
+#define USHRT_MAX	0xffff
+
+#define INT_MIN         0x80000000
+#define INT_MAX         0x7fffffff
+#define UINT_MAX	0xffffffff
+
+/* These change on 32-bit and 64-bit platforms */
+
+#define LONG_MAX	0x80000000
+#define LONG_MIN	0x7fffffff
+#define ULONG_MAX	0xffffffff
+
+#define LLONG_MAX	0x8000000000000000
+#define LLONG_MIN	0x7fffffffffffffff
+#define ULLONG_MAX	0xffffffffffffffff
+
+#endif /* __ARCH_LIMITS_H */

arch/c5471/include/serial.h

@@ -1,5 +1,5 @@
 /************************************************************
- * serial.h
+ * arch/serial.h
  *
  *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@@ -44,18 +44,14 @@
  * Definitions
  ************************************************************/
 
-/* IOCTL commands supported by the C5471 serial driver */
+/* IOCTL commands supported by the ARM serial driver */
 
 #define TIOCSBRK        0x5401  /* BSD compatibility */
 #define TIOCCBRK        0x5402  /* " " "           " */
 #define TIOCSERGSTRUCT  0x5403  /* Get up_dev_t for port */
 
 /************************************************************
- * Private Data
- ************************************************************/
-
-/************************************************************
- * Private Functions
+ * Public Data
  ************************************************************/
 
 /************************************************************

arch/c5471/include/types.h

@@ -1,5 +1,5 @@
 /************************************************************
- * types.h
+ * arch/types.h
  *
  *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@@ -37,8 +37,8 @@
  * only indirectly through sys/types.h
  */
 
-#ifndef __ARCH_C5471_TYPES_H
-#define __ARCH_C5471_TYPES_H
+#ifndef __ARCH_TYPES_H
+#define __ARCH_TYPES_H
 
 /************************************************************
  * Included Files
@@ -79,4 +79,4 @@ typedef unsigned int irqstate_t;
  * Global Function Prototypes
  ************************************************************/
 
-#endif /* __ARCH_C5471_TYPES_H */
+#endif /* __ARCH_TYPES_H */

arch/c5471/include/watchdog.h

@@ -0,0 +1,63 @@
+/************************************************************
+ * watchdog.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+#ifndef __ARCH_WATCHDOG_H
+#define __ARCH_WATCHDOG_H
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/* IOCTL commands supported by the C5471 watchdog driver */
+
+#define WDIOC_KEEPALIVE 0x5701  /* Restart the watchdog timer */
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/************************************************************
+ * Private Functions
+ ************************************************************/
+
+/************************************************************
+ * Public Functions
+ ************************************************************/
+
+#endif /* __ARCH_WATCHDOG_H */

arch/c5471/src/Makefile

@@ -51,7 +51,7 @@ CSRCS		= up_initialize.c up_initialstate.c up_idle.c up_doirq.c \
 		  up_exit.c up_assert.c up_blocktask.c up_unblocktask.c \
 		  up_releasepending.c up_reprioritizertr.c up_copystate.c \
 		  up_schedulesigaction.c up_sigdeliver.c up_serial.c \
-		  up_delay.c up_allocateheap.c up_leds.c
+		  up_delay.c up_allocateheap.c up_watchdog.c
 COBJS		= $(CSRCS:.c=.o)
 
 SRCS		= $(ASRCS) $(CSRCS)
@@ -65,6 +65,8 @@ LINKLIBS	=
 LDPATHES	= $(addprefix -L$(TOPDIR)/,$(dir $(LINKLIBS)))
 LDLIBS		= $(patsubst lib%,-l%,$(basename $(notdir $(LINKLIBS))))
 
+BOARDDIR	= $(TOPDIR)/arch/$(CONFIG_ARCH)/src/board
+
 LIBGCC		= ${shell $(CC) -print-libgcc-file-name}
 
 all: up_head.o libarch$(LIBEXT)
@@ -81,9 +83,12 @@ libarch$(LIBEXT): $(OBJS)
 			{ echo "$(AR) $@ $obj FAILED!" ; exit 1 ; } ; \
 	done ; )
 
-nuttx: $(LINKOBJS)
-	$(LD) --entry=__start $(LDFLAGS) $(LDPATHES) -o $(TOPDIR)/$@ $(LINKOBJS) \
-		--start-group $(LDLIBS) --end-group $(EXTRA_LIBS) $(LIBGCC) 
+board/libboard$(LIBEXT):
+	$(MAKE) -C board TOPDIR=$(TOPDIR) libboard$(LIBEXT)
+
+nuttx: $(LINKOBJS) board/libboard$(LIBEXT)
+	$(LD) --entry=__start $(LDFLAGS) $(LDPATHES) -L$(BOARDDIR) -o $(TOPDIR)/$@ $(LINKOBJS) \
+		--start-group $(LDLIBS) -lboard --end-group $(EXTRA_LIBS) $(LIBGCC) 
 	@$(NM) $(TOPDIR)/$@ | \
 	grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
 	sort > $(TOPDIR)/System.map
@@ -93,7 +98,7 @@ nuttx: $(LINKOBJS)
 		mv $(TOPDIR)/$@.flashimage $(TOPDIR)/$@; \
 	fi
 ifeq ($(CONFIG_RRLOAD_BINARY),y)
-	@$(TOPDIR)/tools/mkimage.sh $(TOPDIR)/$@ $(TOPDIR)/$@.rr
+	@$(TOPDIR)/tools/mkimage.sh --Prefix $(CROSSDEV) $(TOPDIR)/$@ $(TOPDIR)/$@.rr
 	@if [ -w /tftpboot ] ; then \
 		cp -f $(TOPDIR)/$@.rr /tftpboot/$@.rr.${CONFIG_ARCH}; \
 	fi
@@ -101,14 +106,21 @@ endif
 
 .depend: Makefile $(SRCS)
 	$(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep
+	$(MAKE) -C board TOPDIR=$(TOPDIR) depend
 	touch $@
 
 depend: .depend
 
 clean:
+	@if [ -e board/Makefile ]; then \
+		$(MAKE) -C board TOPDIR=$(TOPDIR) clean ; \
+	fi
 	rm -f libarch$(LIBEXT) *.o *~
 
 distclean: clean
+	@if [ -e board/Makefile ]; then \
+		$(MAKE) -C board TOPDIR=$(TOPDIR) distclean ; \
+	fi
 	rm -f Make.dep .depend
 
 -include Make.dep

arch/c5471/src/c5471.h

@@ -40,10 +40,18 @@
  * Included Files
  ************************************************************/
 
+#include <nuttx/config.h>
+
 #ifndef __ASSEMBLY__
 # include <sys/types.h>
 #endif
 
+#if defined(CONFIG_ARCH_BOARD_C5471EVM)
+# include <arch/board/c5471evm.h>
+#else
+# warning "Undefined C5471 Board"
+#endif
+
 /************************************************************
  * Definitions
  ************************************************************/
@@ -72,10 +80,6 @@
 #define CC_Z_BIT               (1 << 30)
 #define CC_N_BIT               (1 << 31)
 
-/* Clocking *************************************************/
-
-#define C5471_CLOCK            47500000 /* 47.5 MHz */
-
 /* UARTs ****************************************************/
 
 #define UART_IRDA_BASE         0xffff0800
@@ -157,30 +161,30 @@
                                         /* Bits 31-7: Reserved */
 #define UART_LCR_BOC         0x00000040 /* Bit 6: Break Control */
                                         /* Bit 5: Parity Type 2 */
-#define UART_LCR_ParEven     0x00000010 /* Bit 4: Parity Type 1 */
-#define UART_LCR_ParOdd      0x00000000
-#define UART_LCR_ParEn       0x00000008 /* Bit 3: Paity Enable */
-#define UART_LCR_ParDis      0x00000000
-#define UART_LCR_2stop       0x00000004 /* Bit 2: Number of stop bits */
-#define UART_LCR_1stop       0x00000000
-#define UART_LCR_5bits       0x00000000 /* Bits 0-1: Word-length */
-#define UART_LCR_6bits       0x00000001
-#define UART_LCR_7bits       0x00000002
-#define UART_LCR_8bits       0x00000003
+#define UART_LCR_PAREVEN     0x00000010 /* Bit 4: Parity Type 1 */
+#define UART_LCR_PARODD      0x00000000
+#define UART_LCR_PAREN       0x00000008 /* Bit 3: Paity Enable */
+#define UART_LCR_PARDIS      0x00000000
+#define UART_LCR_2STOP       0x00000004 /* Bit 2: Number of stop bits */
+#define UART_LCR_1STOP       0x00000000
+#define UART_LCR_5BITS       0x00000000 /* Bits 0-1: Word-length */
+#define UART_LCR_6BITS       0x00000001
+#define UART_LCR_7BITS       0x00000002
+#define UART_LCR_8BITS       0x00000003
 
 #define UART_FCR_FTL         0x00000000
 #define UART_FCR_FIFO_EN     0x00000001
 #define UART_FCR_TX_CLR      0x00000002
 #define UART_FCR_RX_CLR      0x00000004
 
-#define UART_IER_RecvInt     0x00000001
-#define UART_IER_XmitInt     0x00000002
-#define UART_IER_LineStsInt  0x00000004
-#define UART_IER_ModemStsInt 0x00000008 /* IrDA UART only */
-#define UART_IER_XoffInt     0x00000020
-#define UART_IER_RtsInt      0x00000040 /* IrDA UART only */
-#define UART_IER_CtsInt      0x00000080 /* IrDA UART only */
-#define UART_IER_AllInts     0x000000ff
+#define UART_IER_RECVINT     0x00000001
+#define UART_IER_XMITINT     0x00000002
+#define UART_IER_LINESTSINT  0x00000004
+#define UART_IER_MODEMSTSINT 0x00000008 /* IrDA UART only */
+#define UART_IER_XOFFINT     0x00000020
+#define UART_IER_RTSINT      0x00000040 /* IrDA UART only */
+#define UART_IER_CTSINT      0x00000080 /* IrDA UART only */
+#define UART_IER_INTMASK     0x000000ff
 
 #define BAUD_115200          0x00000001
 #define BAUD_57600           0x00000002
@@ -370,11 +374,6 @@ static inline void putreg16(uint16 val, unsigned int addr)
  __asm__ __volatile__("\tstrh %0, [%1]\n\t": : "r"(val), "r"(addr));
 }
 
-/* Most C5471 registers are 16-bits wide */
-
-#define getreg(a)   getreg16(1)
-#define putreg(v,a) putreg16(v,a)
-
 #endif
 
 #endif  /* __C5471_H */