mirror of
https://github.com/FreeRTOS/FreeRTOS.git
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Update to V4.0.4. Add in STR912 port and demo.
This commit is contained in:
Richard Barry
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
# FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
# FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
#
|
||||
# This file is part of the FreeRTOS.org distribution.
|
||||
#
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
# FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
# FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
#
|
||||
# This file is part of the FreeRTOS.org distribution.
|
||||
#
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
||||
175
Demo/ARM9_STR91X_IAR/91x_init_IAR.s
Normal file
175
Demo/ARM9_STR91X_IAR/91x_init_IAR.s
Normal file
@@ -0,0 +1,175 @@
|
||||
;******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
;* File Name : 91x_init.s
|
||||
;* Author : MCD Application Team
|
||||
;* Date First Issued : 05/18/2006 : Version 1.0
|
||||
;* Description : This module performs:
|
||||
;* - FLASH/RAM initialization,
|
||||
;* - Stack pointer initialization for each mode ,
|
||||
;* - Branches to ?main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;*
|
||||
;* On reset, the ARM core starts up in Supervisor (SVC) mode,
|
||||
;* in ARM state,with IRQ and FIQ disabled.
|
||||
;*******************************************************************************
|
||||
; History:
|
||||
; 05/24/2006 : Version 1.1
|
||||
; 05/18/2006 : Version 1.0
|
||||
;*******************************************************************************
|
||||
;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
|
||||
;* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
|
||||
;* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
|
||||
;* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
|
||||
;* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
|
||||
;* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
;******************************************************************************/
|
||||
|
||||
; Depending in Your Application, Disable or Enable the following Define
|
||||
|
||||
; #define BUFFERED_Mode ; Work on Buffered mode, when enabling this define
|
||||
; just enable the Buffered define on 91x_conf.h
|
||||
|
||||
; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs
|
||||
|
||||
Mode_USR EQU 0x10
|
||||
Mode_FIQ EQU 0x11
|
||||
Mode_IRQ EQU 0x12
|
||||
Mode_SVC EQU 0x13
|
||||
Mode_ABT EQU 0x17
|
||||
Mode_UND EQU 0x1B
|
||||
Mode_SYS EQU 0x1F ; available on ARM Arch 4 and later
|
||||
|
||||
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
|
||||
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
|
||||
|
||||
;--- BASE ADDRESSES
|
||||
; System memory locations
|
||||
|
||||
SRAM_Base EQU 0x04000000
|
||||
SRAM_Limit EQU 0x04018000 ; at the top of 96 KB SRAM
|
||||
|
||||
SVC_Stack DEFINE SRAM_Limit ; 512 byte SVC stack at
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||||
; top of memory - used by kernel.
|
||||
IRQ_Stack DEFINE SVC_Stack-512 ; followed by IRQ stack
|
||||
USR_Stack DEFINE IRQ_Stack-512 ; followed by USR stack. Tasks run in
|
||||
; system mode but task stacks are allocated
|
||||
; when the task is created.
|
||||
FIQ_Stack DEFINE USR_Stack-8 ; followed by FIQ stack
|
||||
ABT_Stack DEFINE FIQ_Stack-8 ; followed by ABT stack
|
||||
UND_Stack DEFINE ABT_Stack-8 ; followed by UNDEF stack
|
||||
|
||||
EXTERN main
|
||||
|
||||
; STR9X register specific definition
|
||||
|
||||
FMI_BBSR_AHB_UB EQU 0x54000000
|
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FMI_BBADR_AHB_UB EQU 0x5400000C
|
||||
FMI_NBBSR_AHB_UB EQU 0x54000004
|
||||
FMI_NBBADR_AHB_UB EQU 0x54000010
|
||||
|
||||
SCU_SCRO_APB1_UB EQU 0x4C002034
|
||||
SCRO_AHB_UNB EQU 0x5C002034
|
||||
|
||||
|
||||
|
||||
;---------------------------------------------------------------
|
||||
; ?program_start
|
||||
;---------------------------------------------------------------
|
||||
MODULE ?program_start
|
||||
RSEG ICODE:CODE(2)
|
||||
IMPORT LINK
|
||||
PUBLIC __program_start
|
||||
EXTERN ?main
|
||||
CODE32
|
||||
|
||||
|
||||
__program_start:
|
||||
LDR pc, =NextInst
|
||||
|
||||
|
||||
NextInst
|
||||
|
||||
|
||||
NOP ; execute some instructions to access CPU registers after wake
|
||||
NOP ; up from Reset, while waiting for OSC stabilization
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
ldr r0,=LINK ; to include the vector table inside the final executable.
|
||||
|
||||
|
||||
|
||||
; --- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000,
|
||||
; when the bank 0 is the boot bank, then enable the Bank 1.
|
||||
|
||||
LDR R6, =0x54000000
|
||||
LDR R7, =0x4
|
||||
STR R7, [R6]
|
||||
|
||||
LDR R6, =0x54000004
|
||||
LDR R7, =0x3
|
||||
STR R7, [R6]
|
||||
|
||||
LDR R6, =0x5400000C
|
||||
LDR R7, =0x0
|
||||
STR R7, [R6]
|
||||
|
||||
LDR R6, =0x54000010
|
||||
LDR R7, =0x20000
|
||||
STR R7, [R6]
|
||||
|
||||
LDR R6, =0x54000018
|
||||
LDR R7, =0x18
|
||||
STR R7, [R6]
|
||||
|
||||
; --- Enable 96K RAM
|
||||
LDR R0, = SCRO_AHB_UNB
|
||||
LDR R1, = 0x0196
|
||||
STR R1, [R0]
|
||||
|
||||
|
||||
/* Setup a stack for each mode - note that this only sets up a usable stack
|
||||
for system/user, SWI and IRQ modes. Also each mode is setup with
|
||||
interrupts initially disabled. */
|
||||
|
||||
MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit ; No interrupts
|
||||
LDR SP, =FIQ_Stack
|
||||
|
||||
MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit ; No interrupts
|
||||
LDR SP, =IRQ_Stack
|
||||
|
||||
MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit ; No interrupts
|
||||
LDR SP, =ABT_Stack
|
||||
|
||||
MSR CPSR_c, #Mode_UND|I_Bit|F_Bit ; No interrupts
|
||||
LDR SP, =UND_Stack
|
||||
|
||||
MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit ; No interrupts
|
||||
LDR SP, =SVC_Stack
|
||||
|
||||
MSR CPSR_c, #Mode_SYS|I_Bit|F_Bit ; No interrupts
|
||||
LDR SP, =USR_Stack
|
||||
|
||||
/* We want to start in supervisor mode. Operation will switch to system
|
||||
mode when the first task starts. */
|
||||
MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit
|
||||
|
||||
|
||||
; --- Set bits 17-18 of the Core Configuration Control Register
|
||||
|
||||
MOV r0, #0x60000
|
||||
MCR p15,0x1,r0,c15,c1,0
|
||||
|
||||
|
||||
; --- Now enter the C code
|
||||
B ?main ; Note : use B not BL, because an application will
|
||||
; never return this way
|
||||
|
||||
LTORG
|
||||
|
||||
END
|
||||
;******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****
|
||||
|
||||
134
Demo/ARM9_STR91X_IAR/91x_vect_IAR.s
Normal file
134
Demo/ARM9_STR91X_IAR/91x_vect_IAR.s
Normal file
@@ -0,0 +1,134 @@
|
||||
;******************** (C) COPYRIGHT 2005 STMicroelectronics ********************
|
||||
;* File Name : 91x_vect.s
|
||||
;* Author : MCD Application Team
|
||||
;* Date First Issued : 10/25/2005 : Beta Version V0.1
|
||||
;* Description : This File used to initialize the exception and IRQ
|
||||
;* vectors, and to enter/return to/from exceptions
|
||||
;* handlers.
|
||||
;*******************************************************************************
|
||||
; History:
|
||||
; 10/25/2005 : Beta Version V0.1
|
||||
;*******************************************************************************
|
||||
; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
|
||||
; CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
|
||||
; A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
|
||||
; OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
|
||||
; OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
|
||||
; CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
;******************************************************************************/
|
||||
|
||||
#include "FreeRTOSConfig.h"
|
||||
#include "ISR_Support.h"
|
||||
|
||||
MODULE ?RESET
|
||||
COMMON INTVEC:CODE(2)
|
||||
CODE32
|
||||
EXPORT LINK
|
||||
|
||||
VectorAddress EQU 0xFFFFF030 ; VIC Vector address register address.
|
||||
VectorAddressDaisy EQU 0xFC000030 ; Daisy VIC Vector address register
|
||||
; address.
|
||||
LINK EQU 0x0
|
||||
|
||||
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
|
||||
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
|
||||
|
||||
;*******************************************************************************
|
||||
; MACRO
|
||||
;*******************************************************************************
|
||||
|
||||
;*******************************************************************************
|
||||
; Import the __program_start address from 91x_init.s
|
||||
;*******************************************************************************
|
||||
|
||||
IMPORT __program_start
|
||||
|
||||
;*******************************************************************************
|
||||
; Import exception handlers
|
||||
;*******************************************************************************
|
||||
|
||||
IMPORT vPortYieldProcessor ; FreeRTOS SWI handler
|
||||
|
||||
;*******************************************************************************
|
||||
; Export Peripherals IRQ handlers table address
|
||||
;*******************************************************************************
|
||||
|
||||
;*******************************************************************************
|
||||
; Exception vectors
|
||||
;*******************************************************************************
|
||||
|
||||
LDR PC, Reset_Addr
|
||||
LDR PC, Undefined_Addr
|
||||
LDR PC, SWI_Addr
|
||||
LDR PC, Prefetch_Addr
|
||||
LDR PC, Abort_Addr
|
||||
NOP ; Reserved vector
|
||||
LDR PC, IRQ_Addr
|
||||
LDR PC, FIQ_Addr
|
||||
|
||||
;*******************************************************************************
|
||||
; Exception handlers address table
|
||||
;*******************************************************************************
|
||||
|
||||
Reset_Addr DCD __program_start
|
||||
Undefined_Addr DCD UndefinedHandler
|
||||
SWI_Addr DCD vPortYieldProcessor
|
||||
Prefetch_Addr DCD PrefetchAbortHandler
|
||||
Abort_Addr DCD DataAbortHandler
|
||||
DCD 0 ; Reserved vector
|
||||
IRQ_Addr DCD IRQHandler
|
||||
FIQ_Addr DCD FIQHandler
|
||||
|
||||
|
||||
;*******************************************************************************
|
||||
; Exception Handlers
|
||||
;*******************************************************************************
|
||||
|
||||
; - NOTE -
|
||||
; The IRQ and SWI handlers are the only managed exception.
|
||||
|
||||
UndefinedHandler
|
||||
b UndefinedHandler
|
||||
|
||||
PrefetchAbortHandler
|
||||
b PrefetchAbortHandler
|
||||
|
||||
DataAbortHandler
|
||||
b DataAbortHandler
|
||||
|
||||
FIQHandler
|
||||
b FIQHandler
|
||||
|
||||
DefaultISR
|
||||
b DefaultISR
|
||||
|
||||
|
||||
;*******************************************************************************
|
||||
;* Function Name : IRQHandler
|
||||
;* Description : This function called when IRQ exception is entered.
|
||||
;* Input : none
|
||||
;* Output : none
|
||||
;*******************************************************************************
|
||||
|
||||
IRQHandler
|
||||
portSAVE_CONTEXT ; Save the context of the current task.
|
||||
|
||||
LDR r0, = VectorAddress
|
||||
LDR r0, [r0] ; Read the routine address
|
||||
LDR r1, = VectorAddressDaisy
|
||||
LDR r1, [r1]
|
||||
MOV lr, pc
|
||||
bx r0
|
||||
LDR r0, = VectorAddress ; Write to the VectorAddress to clear the
|
||||
STR r0, [r0] ; respective interrupt in the internal interrupt
|
||||
LDR r1, = VectorAddressDaisy ; Write to the VectorAddressDaisy to clear the
|
||||
STR r1,[r1] ; respective interrupt in the internal interrupt
|
||||
|
||||
portRESTORE_CONTEXT ; Restore the context of the selected task.
|
||||
|
||||
|
||||
LTORG
|
||||
|
||||
END
|
||||
|
||||
;******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****
|
||||
76
Demo/ARM9_STR91X_IAR/FreeRTOSConfig.h
Normal file
76
Demo/ARM9_STR91X_IAR/FreeRTOSConfig.h
Normal file
@@ -0,0 +1,76 @@
|
||||
/*
|
||||
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef FREERTOS_CONFIG_H
|
||||
#define FREERTOS_CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Application specific definitions.
|
||||
*
|
||||
* These definitions should be adjusted for your particular hardware and
|
||||
* application requirements.
|
||||
*
|
||||
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
|
||||
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
#define configUSE_PREEMPTION 1
|
||||
#define configUSE_IDLE_HOOK 0
|
||||
#define configUSE_TICK_HOOK 0
|
||||
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 96000000 )
|
||||
#define configCPU_PERIPH_HZ ( ( unsigned portLONG ) 96000000 )
|
||||
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
|
||||
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
|
||||
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 180 )
|
||||
#define configTOTAL_HEAP_SIZE ( ( size_t ) 50000 )
|
||||
#define configMAX_TASK_NAME_LEN ( 16 )
|
||||
#define configUSE_TRACE_FACILITY 1
|
||||
#define configUSE_16_BIT_TICKS 0
|
||||
#define configIDLE_SHOULD_YIELD 1
|
||||
|
||||
/* Co-routine definitions. */
|
||||
#define configUSE_CO_ROUTINES 0
|
||||
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
|
||||
|
||||
/* Set the following definitions to 1 to include the API function, or zero
|
||||
to exclude the API function. */
|
||||
|
||||
#define INCLUDE_vTaskPrioritySet 1
|
||||
#define INCLUDE_uxTaskPriorityGet 1
|
||||
#define INCLUDE_vTaskDelete 1
|
||||
#define INCLUDE_vTaskCleanUpResources 0
|
||||
#define INCLUDE_vTaskSuspend 1
|
||||
#define INCLUDE_vTaskDelayUntil 1
|
||||
#define INCLUDE_vTaskDelay 1
|
||||
|
||||
|
||||
#endif /* FREERTOS_CONFIG_H */
|
||||
60
Demo/ARM9_STR91X_IAR/Library/include/91x_ahbapb.h
Normal file
60
Demo/ARM9_STR91X_IAR/Library/include/91x_ahbapb.h
Normal file
@@ -0,0 +1,60 @@
|
||||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : 91x_ahbapb.h
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : 05/18/2006 : Version 1.0
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* AHBAPB software library.
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 05/24/2006 : Version 1.1
|
||||
* 05/18/2006 : Version 1.0
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
|
||||
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
|
||||
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
|
||||
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
|
||||
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
|
||||
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef _91x_AHBAPB_H
|
||||
#define _91x_AHBAPB_H
|
||||
|
||||
#include "91x_map.h"
|
||||
|
||||
#define AHBAPB_Split_Enable 0x01000000
|
||||
#define AHBAPB_Split_Disable 0xFEFFFFFF
|
||||
#define AHBAPB_Error_Enable 0x0000100
|
||||
#define AHBAPB_Error_Disable 0xFFFFEFF
|
||||
|
||||
/*FLAG*/
|
||||
#define AHBAPB_FLAG_ERROR 0x01 /* error flag*/
|
||||
#define AHBAPB_FLAG_OUTM 0x10 /* Out of Memory flag */
|
||||
#define AHBAPB_FLAG_APBT 0x20 /* APB Time-out flag */
|
||||
#define AHBAPB_FLAG_RW 0x40 /*Access type flag*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
||||
|
||||
/* AHBAPB Init structure definition */
|
||||
typedef struct
|
||||
{
|
||||
u32 AHBAPB_SetTimeOut;
|
||||
u32 AHBAPB_Error;
|
||||
u32 AHBAPB_Split;
|
||||
u8 AHBAPB_SplitCounter;
|
||||
}AHBAPB_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
void AHBAPB_DeInit(AHBAPB_TypeDef* AHBAPBx);
|
||||
void AHBAPB_Init(AHBAPB_TypeDef* AHBAPBx, AHBAPB_InitTypeDef* AHBAPB_InitStruct);
|
||||
void AHBAPB_StructInit(AHBAPB_InitTypeDef* AHBAPB_InitStruct);
|
||||
FlagStatus AHBAPB_GetFlagStatus(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG);
|
||||
void AHBAPB_ClearFlag(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG);
|
||||
u32 AHBAPB_GetPeriphAddrError(AHBAPB_TypeDef* AHBAPBx);
|
||||
|
||||
|
||||
#endif /* _91x_AHBAPB_H */
|
||||
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
||||
119
Demo/ARM9_STR91X_IAR/Library/include/91x_conf.h
Normal file
119
Demo/ARM9_STR91X_IAR/Library/include/91x_conf.h
Normal file
@@ -0,0 +1,119 @@
|
||||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : 91x_conf.h
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : 03/31/2006 : Beta Version V0.1
|
||||
* Description : Library configuration.
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 03/31/2006 : Beta Version V0.1
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
|
||||
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
|
||||
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
|
||||
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
|
||||
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
|
||||
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __91x_CONF_H
|
||||
#define __91x_CONF_H
|
||||
|
||||
/* To work in buffered mode just decomment the following line */
|
||||
|
||||
//#define Buffered
|
||||
|
||||
/* Comment the line below to put the library in release mode */
|
||||
|
||||
//#ifndef inline
|
||||
// #define inline inline
|
||||
//#endif
|
||||
|
||||
/************************* AHBAPB *************************/
|
||||
#define _AHBAPB
|
||||
#define _AHBAPB0
|
||||
#define _AHBAPB1
|
||||
/************************* VIC *************************/
|
||||
#define _VIC
|
||||
#define _VIC0
|
||||
#define _VIC1
|
||||
/************************* DMA *************************/
|
||||
//#define _DMA
|
||||
//#define _DMA_Channel0
|
||||
//#define _DMA_Channel1
|
||||
//#define _DMA_Channel2
|
||||
//#define _DMA_Channel3
|
||||
//#define _DMA_Channel4
|
||||
//#define _DMA_Channel5
|
||||
//#define _DMA_Channel6
|
||||
//#define _DMA_Channel7
|
||||
|
||||
/************************* EMI *************************/
|
||||
//#define _EMI
|
||||
//#define _EMI_Bank0
|
||||
//#define _EMI_Bank1
|
||||
//#define _EMI_Bank2
|
||||
//#define _EMI_Bank3
|
||||
/************************* FMI *************************/
|
||||
#define _FMI
|
||||
/************************* WIU *************************/
|
||||
//#define _WIU
|
||||
/************************* TIM *************************/
|
||||
//#define _TIM
|
||||
//#define _TIM0
|
||||
//#define _TIM1
|
||||
//#define _TIM2
|
||||
//#define _TIM3
|
||||
/************************* GPIO ************************/
|
||||
#define _GPIO
|
||||
#define _GPIO0
|
||||
#define _GPIO1
|
||||
#define _GPIO2
|
||||
#define _GPIO3
|
||||
#define _GPIO4
|
||||
#define _GPIO5
|
||||
#define _GPIO6
|
||||
#define _GPIO7
|
||||
#define _GPIO8
|
||||
#define _GPIO9
|
||||
/************************* RTC *************************/
|
||||
//#define _RTC
|
||||
/************************* SCU *************************/
|
||||
#define _SCU
|
||||
/************************* MC **************************/
|
||||
//#define _MC
|
||||
/************************* UART ************************/
|
||||
#define _UART
|
||||
//#define _UART0
|
||||
#define _UART1
|
||||
//#define _UART2
|
||||
/************************* SSP *************************/
|
||||
//#define _SSP
|
||||
//#define _SSP0
|
||||
//#define _SSP1
|
||||
/************************* CAN *************************/
|
||||
//#define _CAN
|
||||
/************************* ADC *************************/
|
||||
//#define _ADC
|
||||
/************************* WDG *************************/
|
||||
#define _WDG
|
||||
/************************* I2C *************************/
|
||||
//#define _I2C
|
||||
//#define _I2C0
|
||||
//#define _I2C1
|
||||
/************************ ENET *************************/
|
||||
#define _ENET
|
||||
/************************ DENET ************************/
|
||||
//#define _DENET
|
||||
|
||||
/*---------------------------- _Main_Crystal frequency value (KHz)------------*/
|
||||
|
||||
#ifndef _Main_Crystal
|
||||
#define _Main_Crystal 25000
|
||||
#endif
|
||||
/*------------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#endif /* __91x_CONF_H */
|
||||
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
||||
247
Demo/ARM9_STR91X_IAR/Library/include/91x_dma.h
Normal file
247
Demo/ARM9_STR91X_IAR/Library/include/91x_dma.h
Normal file
@@ -0,0 +1,247 @@
|
||||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : template.h
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : 05/18/2006 : Version 1.0
|
||||
* Description : provide a short description of the source file indicating
|
||||
* its purpose.
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 05/24/2006 : Version 1.1
|
||||
* 05/18/2006 : Version 1.0
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
|
||||
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
|
||||
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
|
||||
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __91x_DMA_H
|
||||
#define __91x_DMA_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include"91x_map.h"
|
||||
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
u32 DMA_Channel_SrcAdd; /* The current source address (byte-aligned) of the data to be transferred.*/
|
||||
|
||||
u32 DMA_Channel_DesAdd; /* The current destination address (byte-aligned) of the data to be transferred.*/
|
||||
|
||||
u32 DMA_Channel_LLstItm; /* The word- aligned address for the next Linked List Item. */
|
||||
|
||||
u32 DMA_Channel_DesWidth; /* Destination transfer width. */
|
||||
|
||||
u32 DMA_Channel_SrcWidth; /* Source transfer width. */
|
||||
|
||||
u32 DMA_Channel_DesBstSize; /* The destination burst size which indicates the number of transfers that make up a destination burst transfer request.*/
|
||||
|
||||
u32 DMA_Channel_SrcBstSize; /* The source burst size.Indicates the number of transfers that make up a source burst */
|
||||
|
||||
u32 DMA_Channel_TrsfSize; /* Transfer size which indicates the size of the transfer when the DMA controller is the flow controller*/
|
||||
|
||||
u32 DMA_Channel_FlowCntrl; /* Flow control and transfer type. */
|
||||
|
||||
u32 DMA_Channel_Src; /* Source peripheral: selects the DMA source request peripheral. */
|
||||
|
||||
u32 DMA_Channel_Des; /* Destination peripheral:selects the DMA destination request peripheral. */
|
||||
|
||||
} DMA_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* Interrupts masks */
|
||||
|
||||
#define DMA_ITMask_IE 0x4000 /* Interrupt error mask. */
|
||||
#define DMA_ITMask_ITC 0x8000 /* Terminal count interrupt mask.*/
|
||||
#define DMA_ITMask_ALL 0xC000 /* All DMA_Channelx interrupts enable/disable mask*/
|
||||
|
||||
/* Sources Request (used as masks) */
|
||||
|
||||
#define DMA_USB_RX_Mask 0x0001
|
||||
#define DMA_USB_TX_Mask 0x0002
|
||||
#define DMA_TIM0_Mask 0x0004
|
||||
#define DMA_TIM1_Mask 0x0008
|
||||
#define DMA_UART0_RX_Mask 0x0010
|
||||
#define DMA_UART0_TX_Mask 0x0020
|
||||
#define DMA_UART1_RX_Mask 0x0040
|
||||
#define DMA_UART1_TX_Mask 0x0080
|
||||
#define DMA_External_Req0_Mask 0x0100
|
||||
#define DMA_External_Req1_Mask 0x0200
|
||||
#define DMA_I2C0_Mask 0x0400
|
||||
#define DMA_I2C1_Mask 0x0800
|
||||
#define DMA_SSP0_RX_Mask 0x1000
|
||||
#define DMA_SSP0_TX_Mask 0x2000
|
||||
#define DMA_SSP1_RX_Mask 0x4000
|
||||
#define DMA_SSP1_TX_Mask 0x8000
|
||||
|
||||
|
||||
/* Previleged Mode and user mode */
|
||||
|
||||
#define DMA_PrevilegedMode 0x10000000
|
||||
#define DMA_UserMode 0xEFFFFFFF
|
||||
|
||||
|
||||
/* Error and Terminal Count interrupts Status, after and before"raw" masking */
|
||||
#define DMA_IS 0x01
|
||||
#define DMA_TCS 0x02
|
||||
#define DMA_ES 0x03
|
||||
#define DMA_TCRS 0x04
|
||||
#define DMA_ERS 0x05
|
||||
|
||||
|
||||
/* interrupt clear: Terminal Count flag Clear and Error flag clear*/
|
||||
|
||||
#define DMA_TCC 0x01
|
||||
#define DMA_EC 0x02
|
||||
|
||||
/* channel index "0...7"*/
|
||||
|
||||
#define Channel0 0
|
||||
#define Channel1 1
|
||||
#define Channel2 2
|
||||
#define Channel3 3
|
||||
#define Channel4 4
|
||||
#define Channel5 5
|
||||
#define Channel6 6
|
||||
#define Channel7 7
|
||||
|
||||
|
||||
|
||||
/* Destination request selection: selects the DMA Destination request peripheral */
|
||||
|
||||
#define DMA_DES_USB_RX 0x00
|
||||
#define DMA_DES_USB_TX 0x40
|
||||
#define DMA_DES_TIM1 0x80
|
||||
#define DMA_DES_TIM2 0xC0
|
||||
#define DMA_DES_UART0_RX 0x100
|
||||
#define DMA_DES_UART0_TX 0x140
|
||||
#define DMA_DES_UART1_RX 0x180
|
||||
#define DMA_DES_UART1_TX 0x1C0
|
||||
#define DMA_DES_External_Req0 0x200
|
||||
#define DMA_DES_External_Req1 0x240
|
||||
#define DMA_DES_I2C0 0x280
|
||||
#define DMA_DES_I2C1 0x2C0
|
||||
#define DMA_DES_SSP0_RX 0x300
|
||||
#define DMA_DES_SSP0_TX 0x340
|
||||
#define DMA_DES_SSP1_RX 0x380
|
||||
#define DMA_DES_SSP1_TX 0x3C0
|
||||
|
||||
|
||||
|
||||
|
||||
/* Source request selection: selects the DMA Source request peripheral */
|
||||
|
||||
#define DMA_SRC_USB_RX 0x00
|
||||
#define DMA_SRC_USB_TX 0x02
|
||||
#define DMA_SRC_TIM1 0x04
|
||||
#define DMA_SRC_TIM2 0x06
|
||||
#define DMA_SRC_UART0_RX 0x08
|
||||
#define DMA_SRC_UART0_TX 0x0A
|
||||
#define DMA_SRC_UART1_RX 0x0C
|
||||
#define DMA_SRC_UART1_TX 0x0E
|
||||
#define DMA_SRC_External_Req0 0x10
|
||||
#define DMA_SRC_External_Req1 0x12
|
||||
#define DMA_SRC_I2C0 0x14
|
||||
#define DMA_SRC_I2C1 0x16
|
||||
#define DMA_SRC_SSP0_RX 0x18
|
||||
#define DMA_SRC_SSP0_TX 0x1A
|
||||
#define DMA_SRC_SSP1_RX 0x1C
|
||||
#define DMA_SRC_SSP1_TX 0x1E
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define DMA_FlowCntrlt0_DMA 0x00000000 /* transfer type :Memory-to-memory, flow controller:DMA */
|
||||
#define DMA_FlowCntrl1_DMA 0x00000800 /* transfer type :Memory-to-peripheral, flow controller:DMA */
|
||||
#define DMA_FlowCntrl2_DMA 0x00001000 /* transfer type :Peripheral-to-memory, flow controller:DMA */
|
||||
#define DMA_FlowCntrl3_DMA 0x00001800 /* transfer type :Source peripheral-to-destination peripheral, flow controller:DMA */
|
||||
#define DMA_FlowCntrl_DestPerip 0x00002000 /* transfer type :Source peripheral-to-destination peripheral, flow controller:Destination peripheral */
|
||||
#define DMA_FlowCntrl_Perip1 0x00002800 /* transfer type :Memory-to-peripheral, flow controller:peripheral */
|
||||
#define DMA_FlowCntrl_Perip2 0x00003000 /* transfer type : Peripheral-to-memory, flow controller:peripheral */
|
||||
#define DMA_FlowCntrl_SrcPerip 0x00003800 /* transfer type :Source peripheral-to-destination peripheral, flow controller:Source peripheral */
|
||||
|
||||
|
||||
|
||||
|
||||
#define DMA_SrcBst_1Data 0x00000000 /* Source Burst transfer request IS 1 Data ( DATA = Source transfer width ) */
|
||||
#define DMA_SrcBst_4Data 0x00001000 /* Source Burst transfer request IS 4 Data */
|
||||
#define DMA_SrcBst_8Data 0x00002000 /* Source Burst transfer request IS 8 Data */
|
||||
#define DMA_SrcBst_16Data 0x00003000 /* Source Burst transfer request IS 16 Data */
|
||||
#define DMA_SrcBst_32Data 0x00004000 /* Source Burst transfer request IS 32 Data */
|
||||
#define DMA_SrcBst_64Data 0x00005000 /* Source Burst transfer request IS 64Data */
|
||||
#define DMA_SrcBst_128Data 0x00006000 /* Source Burst transfer request IS 128 Data */
|
||||
#define DMA_SrcBst_256Data 0x00007000 /* Source Burst transfer request IS 256 Data */
|
||||
|
||||
|
||||
|
||||
|
||||
#define DMA_DesBst_1Data 0x00000000 /*Destination Burst transfer request IS 1Data ( DATA = destination transfer width ) */
|
||||
#define DMA_DesBst_4Data 0x00008000 /*Destination Burst transfer request IS 1 Data */
|
||||
#define DMA_DesBst_8Data 0x00010000 /*Destination Burst transfer request IS 4 Data */
|
||||
#define DMA_DesBst_16Data 0x00018000 /*Destination Burst transfer request IS 8 Data */
|
||||
#define DMA_DesBst_32Data 0x00020000 /*Destination Burst transfer request IS 16 Data */
|
||||
#define DMA_DesBst_64Data 0x00028000 /*Destination Burst transfer request IS 32 Data */
|
||||
#define DMA_DesBst_128Data 0x00030000 /*Destination Burst transfer request IS 128 Data */
|
||||
#define DMA_DesBst_256Data 0x00038000 /*Destination Burst transfer request IS 256 Data */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define DMA_SrcWidth_Byte 0x00000000 /* source Width is one Byte */
|
||||
#define DMA_SrcWidth_HalfWord 0x00040000 /* source Width is one HalfWord */
|
||||
#define DMA_SrcWidth_Word 0x00080000 /* source Width is one Word */
|
||||
|
||||
|
||||
|
||||
|
||||
#define DMA_DesWidth_Byte 0x00000000 /* Destination Width is one Byte */
|
||||
#define DMA_DesWidth_HalfWord 0x00200000 /* Destination Width is one HalfWord */
|
||||
#define DMA_DesWidth_Word 0x00400000 /* Destination Width is one Word */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
void DMA_DeInit(void);
|
||||
void DMA_Init(DMA_Channel_TypeDef * DMA_Channelx, DMA_InitTypeDef * DMA_InitStruct);
|
||||
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct);
|
||||
void DMA_Cmd(FunctionalState NewState);
|
||||
void DMA_ITMaskConfig(DMA_Channel_TypeDef * DMA_Channelx, u16 DMA_ITMask, FunctionalState NewState);
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState);
|
||||
FlagStatus DMA_GetChannelStatus(u8 ChannelIndx );
|
||||
ITStatus DMA_GetITStatus(u8 ChannelIndx,u8 DMA_ITReq);
|
||||
void DMA_ClearIT(u8 ChannelIndx,u8 DMA_ITClr);
|
||||
void DMA_SyncConfig(u16 DMA_SrcReq, FunctionalState NewState);
|
||||
FlagStatus DMA_GetSReq(u16 DMA_SrcReq);
|
||||
FlagStatus DMA_GetLSReq(u16 DMA_SrcReq);
|
||||
FlagStatus DMA_GetBReq(u16 DMA_SrcReq);
|
||||
FlagStatus DMA_GetLBReq(u16 DMA_SrcReq);
|
||||
FlagStatus DMA_GetChannelActiveStatus( DMA_Channel_TypeDef * DMA_Channelx);
|
||||
void DMA_SetSReq(u16 DMA_SrcReq);
|
||||
void DMA_SetLSReq(u16 DMA_SrcReq);
|
||||
void DMA_SetBReq(u16 DMA_SrcReq);
|
||||
void DMA_SetLBReq(u16 DMA_SrcReq);
|
||||
void DMA_ChannelCmd (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState);
|
||||
void DMA_ChannelHalt (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState);
|
||||
void DMA_ChannelBuffering (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState);
|
||||
void DMA_ChannelLockTrsf(DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState);
|
||||
void DMA_ChannelCache(DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState);
|
||||
void DMA_ChannelProt0Mode(DMA_Channel_TypeDef * DMA_Channelx,u32 Prot0Mode);
|
||||
void DMA_ChannelSRCIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState);
|
||||
void DMA_ChannelDESIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState);
|
||||
|
||||
#endif /* __91x_DMA_H */
|
||||
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
||||
357
Demo/ARM9_STR91X_IAR/Library/include/91x_enet.h
Normal file
357
Demo/ARM9_STR91X_IAR/Library/include/91x_enet.h
Normal file
@@ -0,0 +1,357 @@
|
||||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : 91x_enet.h
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : May 2006
|
||||
* Description : ENET driver defines & function prototypes
|
||||
********************************************************************************
|
||||
* History:
|
||||
* May 2006: v1.0
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
|
||||
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
|
||||
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
|
||||
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _ENET_H_
|
||||
#define _ENET_H_
|
||||
|
||||
#include <91x_lib.h>
|
||||
|
||||
#define ENET_BUFFER_SIZE 1520
|
||||
/*Structures typedef----------------------------------------------------------*/
|
||||
|
||||
/*Struct containing the DMA Descriptor data */
|
||||
typedef struct {
|
||||
volatile u32 dmaStatCntl; /* DMA Status and Control Register */
|
||||
volatile u32 dmaAddr; /* DMA Start Address Register */
|
||||
volatile u32 dmaNext; /* DMA Next Descriptor Register */
|
||||
volatile u32 dmaPackStatus; /* DMA Packet Status and Control Register */
|
||||
} ENET_DMADSCRBase;
|
||||
|
||||
|
||||
/* ENET_MACConfig Struct*/
|
||||
typedef struct {
|
||||
FunctionalState ReceiveALL; /* Receive All frames: no address rule filtering */
|
||||
u32 MIIPrescaler; /* MII Clock Prescaler value */
|
||||
FunctionalState LoopbackMode; /* MAC Loopback mode */
|
||||
u32 AddressFilteringMode; /* Address Filtering Mode */
|
||||
u32 VLANFilteringMode; /* VLAN Filtering Mode */
|
||||
FunctionalState PassWrongFrame; /* Pass wrong frame (CRC, overlength, runt..)*/
|
||||
FunctionalState LateCollision; /* Retransmit frame when late collision*/
|
||||
FunctionalState BroadcastFrameReception; /* Accept broardcast frame */
|
||||
FunctionalState PacketRetry; /* Retransmit frame in case of collision */
|
||||
FunctionalState RxFrameFiltering; /* Filter early runt frame and address filter fail frames*/
|
||||
FunctionalState AutomaticPadRemoval; /* Automatic Padding removal */
|
||||
FunctionalState DeferralCheck; /* Excessive Defferal check */
|
||||
} ENET_MACConfig;
|
||||
|
||||
/* ENET_TxStatus Struct*/
|
||||
typedef struct {
|
||||
FlagStatus PacketRetry;
|
||||
u8 ByteCount;
|
||||
u8 collisionCount;
|
||||
FlagStatus LateCollisionObserved;
|
||||
FlagStatus Deffered;
|
||||
FlagStatus UnderRun;
|
||||
FlagStatus ExcessiveCollision;
|
||||
FlagStatus LateCollision;
|
||||
FlagStatus ExcessiveDefferal;
|
||||
FlagStatus LossOfCarrier;
|
||||
FlagStatus NoCarrier;
|
||||
FlagStatus FrameAborted;
|
||||
} ENET_TxStatus;
|
||||
|
||||
/* ENET_RxStatus Struct*/
|
||||
typedef struct {
|
||||
FlagStatus FrameAborted;
|
||||
FlagStatus PacketFilter;
|
||||
FlagStatus FilteringFail;
|
||||
FlagStatus BroadCastFrame;
|
||||
FlagStatus MulticastFrame;
|
||||
FlagStatus UnsupportedControFrame;
|
||||
FlagStatus ControlFrame;
|
||||
FlagStatus LengthError;
|
||||
FlagStatus Vlan2Tag;
|
||||
FlagStatus Vlan1Tag;
|
||||
FlagStatus CRCError;
|
||||
FlagStatus ExtraBit;
|
||||
FlagStatus MIIError;
|
||||
FlagStatus FrameType;
|
||||
FlagStatus LateCollision;
|
||||
FlagStatus OverLength;
|
||||
FlagStatus RuntFrame;
|
||||
FlagStatus WatchDogTimout;
|
||||
FlagStatus FalseCarrierIndication;
|
||||
u16 FrameLength;
|
||||
} ENET_RxStatus;
|
||||
|
||||
/*Constants-------------------------------------------------------------------*/
|
||||
|
||||
|
||||
/* AddressFilteringMode */
|
||||
#define MAC_Perfect_Multicast_Perfect 0x0
|
||||
#define MAC_Perfect_Muticast_Hash 0x1<<17
|
||||
#define MAC_Hash_Multicast_Hash 0x3<<17
|
||||
#define Inverse 0x4<<17
|
||||
#define Promiscuous 0x5<<17
|
||||
#define MAC_Hash_Muticast_All 0x6<<17
|
||||
|
||||
/* VLANFilteringMode */
|
||||
#define VLANFilter_VLTAG_VLID 1
|
||||
#define VLANfilter_VLTAG 0
|
||||
|
||||
/* MIIPrescaler */
|
||||
#define MIIPrescaler_1 0 /* Prescaler for MDC clock when HCLK < 50 MHz */
|
||||
#define MIIPrescaler_2 1 /* Precaler for MDC when HCLK > = 50 MHz */
|
||||
|
||||
|
||||
/* MAC Address*/
|
||||
#define MAC_ADDR0 0x0D
|
||||
#define MAC_ADDR1 0x0A
|
||||
#define MAC_ADDR2 0x08
|
||||
#define MAC_ADDR3 0x04
|
||||
#define MAC_ADDR4 0x02
|
||||
#define MAC_ADDR5 0x01
|
||||
|
||||
/* Multicast Address */
|
||||
#define MCAST_ADDR0 0xFF
|
||||
#define MCAST_ADDR1 0x00
|
||||
#define MCAST_ADDR2 0xFF
|
||||
#define MCAST_ADDR3 0x00
|
||||
#define MCAST_ADDR4 0xFF
|
||||
#define MCAST_ADDR5 0x00
|
||||
|
||||
|
||||
|
||||
#define ENET_MAX_PACKET_SIZE 1520
|
||||
#define ENET_NEXT_ENABLE 0x4000
|
||||
|
||||
/*ENET_OperatingMode*/
|
||||
/* Set the full/half-duplex mode at 100 Mb/s */
|
||||
#define PHY_FULLDUPLEX_100M 0x2100
|
||||
#define PHY_HALFDUPLEX_100M 0x2000
|
||||
/* Set the full/half-duplex mode at 10 Mb/s */
|
||||
#define PHY_FULLDUPLEX_10M 0x0100
|
||||
#define PHY_HALFDUPLEX_10M 0x0000
|
||||
|
||||
|
||||
/*----------------------------functions----------------------------------------*/
|
||||
|
||||
void ENET_MACControlConfig(ENET_MACConfig *MAC_Config);
|
||||
void ENET_GetRxStatus(ENET_RxStatus * RxStatus);
|
||||
void ENET_GetTxStatus(ENET_TxStatus * TxStatus);
|
||||
long ENET_SetOperatingMode(void);
|
||||
void ENET_InitClocksGPIO(void);
|
||||
void ENET_MIIWriteReg (u8 phyDev, u8 phyReg, u32 phyVal);
|
||||
u32 ENET_MIIReadReg (u8 phyDev, u32 phyReg );
|
||||
void ENET_RxDscrInit(void);
|
||||
void ENET_TxDscrInit(void);
|
||||
void ENET_Init(void);
|
||||
void ENET_Start(void);
|
||||
u32 ENET_RxPacketGetSize(void);
|
||||
void ENET_TxPkt(void *ppkt, u16 size);
|
||||
u32 ENET_HandleRxPkt(void *ppkt);
|
||||
|
||||
|
||||
/*Driver internal constants---------------------------------------------------*/
|
||||
|
||||
/* MII Address */
|
||||
/* Description of bit field values of the MII Address Register */
|
||||
#define MAC_MIIA_PADDR 0x0000F800
|
||||
#define MAC_MII_ADDR_PHY_ADDR MAC_MIIA_PADDR /* Phy Address (default: 0): select one of 32 dev */
|
||||
#define MAC_MII_ADDR_MII_REG 0x000007C0 /* MII Register (default: 0) */
|
||||
#define MAC_MII_ADDR_MII_WRITE 0x00000002 /* MII Write */
|
||||
#define MAC_MIIA_PHY_DEV_ADDR (0x00005000 & MAC_MIIA_PADDR) /*To be changed if PHY device address changes */
|
||||
#define MAC_MII_ADDR_MII_BUSY 0x00000001 /* MII Busy */
|
||||
|
||||
|
||||
/* MII DATA register */
|
||||
#define MAC_MII_DATA_REG 0x0000FFFF /* MII Data */
|
||||
|
||||
/* MII Read / write timeouts*/
|
||||
#define MII_READ_TO 0x0004FFFF
|
||||
#define MII_WRITE_TO 0x0004FFFF
|
||||
|
||||
/* Description of common PHY registers */
|
||||
#define MAC_MII_REG_XCR 0x00000000 /* Tranceiver control register */
|
||||
#define MAC_MII_REG_XSR 0x00000001 /* Tranceiver status register */
|
||||
#define MAC_MII_REG_PID1 0x00000002 /* Tranceiver PHY identifier 1 */
|
||||
#define MAC_MII_REG_PID2 0x00000003 /* Tranceiver PHY identifier 2 */
|
||||
#define MAC_MII_REG_ANA 0x00000004 /* Auto-Negociation Advertissement register */
|
||||
#define MAC_MII_REG_ANLPA 0x00000005 /* Auto-Negociation Link Partner Ability register */
|
||||
#define MAC_MII_REG_ANE 0x00000006 /* Auto-Negociation Expansion register */
|
||||
|
||||
|
||||
|
||||
|
||||
/* MAC_MCR register fields */
|
||||
#define MAC_MCR_RA 0x80000000
|
||||
#define MAC_MCR_EN 0x40000000
|
||||
#define MAC_MCR_PS 0x03000000
|
||||
#define MAC_MCR_DRO 0x00800000
|
||||
#define MAC_MCR_LM 0x00600000
|
||||
#define MAC_MCR_FDM 0x00100000
|
||||
#define MAC_MCR_AFM 0x000E0000
|
||||
#define MAC_MCR_PWF 0x00010000
|
||||
#define MAC_MCR_VFM 0x00008000
|
||||
#define MAC_MCR_ELC 0x00001000
|
||||
#define MAC_MCR_DBF 0x00000800
|
||||
#define MAC_MCR_DPR 0x00000400
|
||||
#define MAC_MCR_RVFF 0x00000200
|
||||
#define MAC_MCR_APR 0x00000100
|
||||
#define MAC_MCR_BL 0x000000C0
|
||||
#define MAC_MCR_DCE 0x00000020
|
||||
#define MAC_MCR_RVBE 0x00000010
|
||||
#define MAC_MCR_TE 0x00000008
|
||||
#define MAC_MCR_RE 0x00000004
|
||||
#define MAC_MCR_RCFA 0x00000001
|
||||
|
||||
/* MTS */
|
||||
#define MAC_MTS_FA 0x00000001
|
||||
#define MAC_MTS_NC 0x00000004
|
||||
#define MAC_MTS_LOC 0x00000008
|
||||
#define MAC_MTS_ED 0x00000010
|
||||
#define MAC_MTS_LC 0x00000020
|
||||
#define MAC_MTS_EC 0x00000040
|
||||
#define MAC_MTS_UR 0x00000080
|
||||
#define MAC_MTS_DEF 0x00000100
|
||||
#define MAC_MTS_LCO 0x00000200
|
||||
#define MAC_MTS_CC 0x00003C00
|
||||
#define MAC_MTS_BC 0x7FFC0000
|
||||
#define MAC_MTS_PR 0x80000000
|
||||
|
||||
/* MRS */
|
||||
#define MAC_MRS_FL 0x000007FF
|
||||
#define MAC_MRS_FCI 0x00002000
|
||||
#define MAC_MRS_WT 0x00004000
|
||||
#define MAC_MRS_RF 0x00008000
|
||||
#define MAC_MRS_OL 0x00010000
|
||||
#define MAC_MRS_LC 0x00020000
|
||||
#define MAC_MRS_FT 0x00040000
|
||||
#define MAC_MRS_ME 0x00080000
|
||||
#define MAC_MRS_EB 0x00100000
|
||||
#define MAC_MRS_CE 0x00200000
|
||||
#define MAC_MRS_VL1 0x00400000
|
||||
#define MAC_MRS_VL2 0x00800000
|
||||
#define MAC_MRS_LE 0x01000000
|
||||
#define MAC_MRS_CF 0x02000000
|
||||
#define MAC_MRS_UCF 0x04000000
|
||||
#define MAC_MRS_MCF 0x08000000
|
||||
#define MAC_MRS_BF 0x10000000
|
||||
#define MAC_MRS_FF 0x20000000
|
||||
#define MAC_MRS_PF 0x40000000
|
||||
#define MAC_MRS_FA 0x80000000
|
||||
|
||||
/* SCR */
|
||||
#define DMA_SCR_SRESET 0x00000001 /* Soft Reset (DMA_SCR_RESET) */
|
||||
#define DMA_SCR_LOOPB 0x00000002 /* Loopback mode (DMA_SCR_LOOPB) */
|
||||
#define DMA_SCR_RX_MBSIZE 0x00000010 /* Max defined burst length in RX mode (DMA_SCR_RX_MAX_BURST_...) */
|
||||
#define DMA_SCR_TX_MBSIZE 0x000000C0 /* Max defined burst length in TX mode (DMA_SCR_TX_MAX_BURST_...) */
|
||||
#define DMA_SCR_RX_MAX_BURST_SZ DMA_SCR_RX_MBSIZE /* Maximum value of defined burst length in RX mode */
|
||||
#define DMA_SCR_RX_MAX_BURST_SZ_VAL 0x00000000 /* Default value of burst length in RX mode */
|
||||
#define DMA_SCR_TX_MAX_BURST_SZ DMA_SCR_TX_MBSIZE /* Maximum value of defined burst length in TX mode */
|
||||
#define DMA_SCR_TX_MAX_BURST_SZ_VAL 0x000000C0 /* Default value of burst length in TX mode */
|
||||
|
||||
|
||||
/* DMA_RX_START */
|
||||
#define DMA_RX_START_DMAEN 0x00000001
|
||||
#define DMA_RX_START_STFETCH 0x00000004
|
||||
#define DMA_RX_START_FFAIL 0x00000020
|
||||
#define DMA_RX_START_RUNT 0x00000040
|
||||
#define DMA_RX_START_COLLS 0x00000080
|
||||
#define DMA_RX_START_DMA_EN 0x00000001 /* set = 0 by sw force a DMA abort */
|
||||
#define DMA_RX_START_FETCH 0x00000004 /* start fetching the 1st descriptor */
|
||||
#define DMA_RX_START_FILTER_FAIL 0x00000020 /* if = 1 the address filtering failed cond */
|
||||
#define DMA_RX_START_RUNT 0x00000040 /* discard damaged RX frames from cpu charge */
|
||||
#define DMA_RX_START_COLLS_SEEN 0x00000080 /* Late Collision Seen Cond discard frame automat. */
|
||||
#define DMA_RX_START_DFETCH_DLY 0x00FFFF00 /* Descriptor Fetch Delay */
|
||||
#define DMA_RX_START_DFETCH_DLY_POS 8
|
||||
#define DMA_RX_START_DFETCH_DEFAULT 0x00010000 /* Descriptor Fetch Delay default value */
|
||||
|
||||
/* DMA_DSCR_PACK_STAT */
|
||||
#define DMA_DSCR_PACK_STAT 0x00010000
|
||||
|
||||
|
||||
/* DMA_TX_START */
|
||||
#define DMA_TX_START_DMAEN 0x00000001
|
||||
#define DMA_TX_START_STFETCH 0x00000004
|
||||
#define DMA_TX_START_URUN 0x00000020
|
||||
#define DMA_TX_START_DISPAD 0x00000040
|
||||
#define DMA_TX_START_ADDCTC 0x00000080
|
||||
#define DMA_TX_START_DMA_EN 0x00000001 /* set = 0 by sw force a DMA abort */
|
||||
#define DMA_TX_START_FETCH 0x00000004 /* start fetching the 1st descriptor */
|
||||
#define DMA_RX_START_FILTER_FAIL 0x00000020 /* if = 1 the address filtering failed cond */
|
||||
#define DMA_TX_START_DFETCH_DLY 0x00FFFF00 /* Descriptor Fetch Delay */
|
||||
#define DMA_TX_START_DFETCH_DEFAULT 0x00010000 /* Descriptor Fetch Delay */
|
||||
#define DMA_TX_START_DFETCH_DLY_POS 0x8
|
||||
#define DMA_TX_START_URUN 0x00000020
|
||||
#define DMA_TX_START_DIS_PADDING 0x00000040 /* Avoid automatic addition of padding bits by MAC*/
|
||||
#define DMA_TX_START_ADD_CRC_DIS 0x00000080 /* Tell MAC not to ADD CRC field at end of frame */
|
||||
|
||||
/* DMA_DSCR_CNTL */
|
||||
#define DMA_DSCR_CNTL_XFERCOUNT 0x00000FFF
|
||||
#define DMA_DSCR_CNTL_NXTEN 0x00004000
|
||||
|
||||
/* DMA_DSCR_ADDR */
|
||||
#define DMA_DSCR_ADDR 0xFFFFFFFC /* for DMA Start Address (32 bit Word Align) */
|
||||
#define DMA_DSCR_ADDR_FIX_ADDR 0x00000002 /* Disable incrementing of DMA_ADDR */
|
||||
#define DMA_DSCR_ADDR_WRAPEN_SET 0x00000001
|
||||
#define DMA_DSCR_ADDR_WRAPEN_RST 0x00000000
|
||||
|
||||
/* DMA_DSCR_NEXT_ADDR TX/RX */
|
||||
#define DMA_DSCR_NXT_DSCR_ADDR 0xFFFFFFFC /* Points to Next descriptor starting address */
|
||||
#define DMA_DSCR_NXT_NPOL_EN 0x00000001 /* Next Descriptor Polling Enable */
|
||||
#define DMA_DSCR_NXT_NEXT_EN 0x00000002 /* Next Descriptor Fetch mode Enable */
|
||||
|
||||
/* DMA Descriptor Packet Status: TX */
|
||||
#define DMA_DSCR_TX_STATUS_FA_MSK 0x00000001 /* Frame Aborted */
|
||||
#define DMA_DSCR_TX_STATUS_JTO_MSK 0x00000002 /* Jabber Timeout. */
|
||||
#define DMA_DSCR_TX_STATUS_NOC_MSK 0x00000004 /* No Carrier */
|
||||
#define DMA_DSCR_TX_STATUS_LOC_MSK 0x00000008 /* Loss of Carrier */
|
||||
#define DMA_DSCR_TX_STATUS_EXCD_MSK 0x00000010 /* Excessive Deferral */
|
||||
#define DMA_DSCR_TX_STATUS_LCOLL_MSK 0x00000020 /* Late Collision */
|
||||
#define DMA_DSCR_TX_STATUS_ECOLL_MSK 0x00000040 /* Excessive Collisions */
|
||||
#define DMA_DSCR_TX_STATUS_URUN_MSK 0x00000080 /* Under Run */
|
||||
#define DMA_DSCR_TX_STATUS_DEFER_MSK 0x00000100 /* Deferred */
|
||||
#define DMA_DSCR_TX_STATUS_LCOLLO_MSK 0x00000200 /* Late Collision Observed */
|
||||
#define DMA_DSCR_TX_STATUS_CCNT_MSK 0x00003C00 /* Collision Count */
|
||||
#define DMA_DSCR_TX_STATUS_HBFAIL_MSK 0x00004000 /* Heart Beat Fail */
|
||||
#define DMA_DSCR_TX_STATUS_VALID_MSK 0x00010000 /* Valid bit indicator - This bit marks the dscriptors this word belong */
|
||||
#define DMA_DSCR_TX_STATUS_PKT_RTRY_MSK 0x80000000 /* Packet Retry */
|
||||
#define DMA_DSCR_TX_STATUS_ORED_ERR_MSK 0x000003D7 /* for total number of errors */
|
||||
|
||||
/* DMA Descriptor Packet Status: RX */
|
||||
#define DMA_DSCR_RX_STATUS_FLEN_MSK 0x000007ff /* 0x00003FFF * Frame Length (max 2047) */
|
||||
#define DMA_DSCR_RX_STATUS_FTLONG_MSK 0x00001000 /* Over Lenght */
|
||||
#define DMA_DSCR_RX_STATUS_FCI_MSK 0x00002000 /* Frame too Long */
|
||||
#define DMA_DSCR_RX_STATUS_WDTO_MSK 0x00004000 /* Watchdog Timeout */
|
||||
#define DMA_DSCR_RX_STATUS_RUNTFR_MSK 0x00008000 /* Runt Frame */
|
||||
#define DMA_DSCR_RX_STATUS_VALID_MSK 0x00010000 /* Valid bit indicator - This bit marks the dscriptors this word */
|
||||
#define DMA_DSCR_RX_STATUS_COLLSEEN_MSK 0x00020000 /* Collision Seen */
|
||||
#define DMA_DSCR_RX_STATUS_FTYPE_MSK 0x00040000 /* Frame Type */
|
||||
#define DMA_DSCR_RX_STATUS_MII_ERR_MSK 0x00080000 /* MII Error */
|
||||
#define DMA_DSCR_RX_STATUS_DRBBIT_MSK 0x00100000 /* Dribbling Bit */
|
||||
#define DMA_DSCR_RX_STATUS_CRC_ERR_MSK 0x00200000 /* CRC Error */
|
||||
#define DMA_DSCR_RX_STATUS_VLAN1_FR_MSK 0x00400000 /* One-Level VLAN Frame */
|
||||
#define DMA_DSCR_RX_STATUS_VLAN2_FR_MSK 0x00800000 /* Two-Level VLAN Frame */
|
||||
#define DMA_DSCR_RX_STATUS_LEN_ERR_MSK 0x01000000 /* Length Error */
|
||||
#define DMA_DSCR_RX_STATUS_CTL_FR_MSK 0x02000000 /* Control Frame */
|
||||
#define DMA_DSCR_RX_STATUS_UCTRL_FR_MSK 0x04000000 /* Unsupported Control Frame */
|
||||
#define DMA_DSCR_RX_STATUS_MCAST_FR_MSK 0x08000000 /* Multicast Frame */
|
||||
#define DMA_DSCR_RX_STATUS_BCAST_FR_MSK 0x10000000 /* BroadCast Frame */
|
||||
#define DMA_DSCR_RX_STATUS_FLT_FAIL_MSK 0x20000000 /* Filtering Fail */
|
||||
#define DMA_DSCR_RX_STATUS_PKT_FILT_MSK 0x40000000 /* Packet Filter */
|
||||
#define DMA_DSCR_RX_STATUS_MIS_FR_MSK 0x80000000 /* Missed Frame */
|
||||
#define DMA_DSCR_RX_STATUS_ERROR_MSK (DMA_DSCR_RX_STATUS_LEN_ERR | DMA_DSCR_RX_STATUS_CRC_ERR | \
|
||||
DMA_DSCR_RX_STATUS_MII_ERR | DMA_DSCR_RX_STATUS_RUNTFR | \
|
||||
DMA_DSCR_RX_STATUS_FTLONG | DMA_DSCR_RX_STATUS_COLLSEEN)
|
||||
#define DMA_DSCR_RX_STATUS_ORED_ERR_MSK 0x00000000 /*Mask for total number of errors */
|
||||
|
||||
|
||||
#endif /* _ENET_H_ */
|
||||
|
||||
/******************** (C) COPYRIGHT 2006 STMicroelectronics *******************/
|
||||
|
||||
184
Demo/ARM9_STR91X_IAR/Library/include/91x_fmi.h
Normal file
184
Demo/ARM9_STR91X_IAR/Library/include/91x_fmi.h
Normal file
@@ -0,0 +1,184 @@
|
||||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : 91x_fmi.h
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : 05/18/2006 : Version 1.0
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* FMI software library.
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 05/24/2006 : Version 1.1
|
||||
* 05/18/2006 : Version 1.0
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
|
||||
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
|
||||
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
|
||||
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
|
||||
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
|
||||
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion ------------------------------------ */
|
||||
|
||||
#ifndef __91x_FMI_H
|
||||
#define __91x_FMI_H
|
||||
|
||||
/* ========================================================================== */
|
||||
/* When bank 1 is remapped at address 0x0, decomment the following line */
|
||||
/* ========================================================================== */
|
||||
|
||||
//#define Remap_Bank_1
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
||||
#include "91x_map.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* FMI banks */
|
||||
|
||||
#ifdef Remap_Bank_1
|
||||
|
||||
#define FMI_BANK_0 ((*(vu32*)0x54000010) << 2) /* FMI Bank 0 */
|
||||
#define FMI_BANK_1 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 1 */
|
||||
|
||||
#else /* Remap Bank 0 */
|
||||
|
||||
#define FMI_BANK_0 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 0 */
|
||||
#define FMI_BANK_1 ((*(vu32*)0x54000010) << 2) /* FMI Bank 1 */
|
||||
|
||||
#endif
|
||||
|
||||
/* FMI sectors */
|
||||
|
||||
#define FMI_B0S0 0x00000000 + FMI_BANK_0 /* Bank 0 sector 0 */
|
||||
#define FMI_B0S1 0x00010000 + FMI_BANK_0 /* Bank 0 sector 1 */
|
||||
#define FMI_B0S2 0x00020000 + FMI_BANK_0 /* Bank 0 sector 2 */
|
||||
#define FMI_B0S3 0x00030000 + FMI_BANK_0 /* Bank 0 sector 3 */
|
||||
#define FMI_B0S4 0x00040000 + FMI_BANK_0 /* Bank 0 sector 4 */
|
||||
#define FMI_B0S5 0x00050000 + FMI_BANK_0 /* Bank 0 sector 5 */
|
||||
#define FMI_B0S6 0x00060000 + FMI_BANK_0 /* Bank 0 sector 6 */
|
||||
#define FMI_B0S7 0x00070000 + FMI_BANK_0 /* Bank 0 sector 7 */
|
||||
|
||||
#define FMI_B1S0 0x00000000 + FMI_BANK_1 /* Bank 1 sector 0 */
|
||||
#define FMI_B1S1 0x00002000 + FMI_BANK_1 /* Bank 1 sector 1 */
|
||||
#define FMI_B1S2 0x00004000 + FMI_BANK_1 /* Bank 1 sector 2 */
|
||||
#define FMI_B1S3 0x00006000 + FMI_BANK_1 /* Bank 1 sector 3 */
|
||||
|
||||
/* FMI Flags */
|
||||
|
||||
#define FMI_FLAG_SPS 0x02 /* Sector Protection Status Flag */
|
||||
#define FMI_FLAG_PSS 0x04 /* Program Suspend Status Flag */
|
||||
#define FMI_FLAG_PS 0x10 /* Program Status Flag */
|
||||
#define FMI_FLAG_ES 0x20 /* Erase Status Flag */
|
||||
#define FMI_FLAG_ESS 0x40 /* Erase Suspend Status Flag */
|
||||
#define FMI_FLAG_PECS 0x80 /* FPEC Status Flag */
|
||||
|
||||
/* FMI read wait states */
|
||||
|
||||
#define FMI_READ_WAIT_STATE_1 0x0000 /* One read wait state */
|
||||
#define FMI_READ_WAIT_STATE_2 0x2000 /* Two read wait states */
|
||||
#define FMI_READ_WAIT_STATE_3 0x4000 /* Three read wait states */
|
||||
|
||||
/* FMI write wait states */
|
||||
|
||||
#define FMI_WRITE_WAIT_STATE_0 0xFFFFFEFF /* Zero wait state */
|
||||
#define FMI_WRITE_WAIT_STATE_1 0x00000100 /* One wait state */
|
||||
|
||||
/* FMI power down configuration */
|
||||
|
||||
#define FMI_PWD_ENABLE 0x1000 /* FMI Power Down Enable */
|
||||
#define FMI_PWD_DISABLE 0x0000 /* FMI Power Down Disable */
|
||||
|
||||
/* FMI low voltage detector */
|
||||
|
||||
#define FMI_LVD_ENABLE 0x0000 /* FMI Low Voltage Detector Enable */
|
||||
#define FMI_LVD_DISABLE 0x0800 /* FMI Low Voltage Detector Disable */
|
||||
|
||||
/* FMI frequency range */
|
||||
|
||||
#define FMI_FREQ_LOW 0x0000 /* FMI Low bus working frequency */
|
||||
#define FMI_FREQ_HIGH 0x0040 /* FMI High bus working gfrequency */
|
||||
/* Above 66 MHz*/
|
||||
/* FMI OTP word addresses */
|
||||
|
||||
#define FMI_OTP_WORD_0 0x00 /* OTP word 0 */
|
||||
#define FMI_OTP_WORD_1 0x04 /* OTP word 1 */
|
||||
#define FMI_OTP_WORD_2 0x08 /* OTP word 2 */
|
||||
#define FMI_OTP_WORD_3 0x0C /* OTP word 3 */
|
||||
#define FMI_OTP_WORD_4 0x10 /* OTP word 4 */
|
||||
#define FMI_OTP_WORD_5 0x14 /* OTP word 5 */
|
||||
#define FMI_OTP_WORD_6 0x18 /* OTP word 6 */
|
||||
#define FMI_OTP_WORD_7 0x1C /* OTP word 7 */
|
||||
|
||||
/* FMI OTP halfword addresses */
|
||||
|
||||
#define FMI_OTP_LOW_HALFWORD_0 0x00 /* OTP Low halfword 0 */
|
||||
#define FMI_OTP_HIGH_HALFWORD_0 0x02 /* OTP High halfword 0 */
|
||||
#define FMI_OTP_LOW_HALFWORD_1 0x04 /* OTP Low halfword 1 */
|
||||
#define FMI_OTP_HIGH_HALFWORD_1 0x06 /* OTP High halfword 1 */
|
||||
#define FMI_OTP_LOW_HALFWORD_2 0x08 /* OTP Low halfword 2 */
|
||||
#define FMI_OTP_HIGH_HALFWORD_2 0x0A /* OTP High halfword 2 */
|
||||
#define FMI_OTP_LOW_HALFWORD_3 0x0C /* OTP Low halfword 3 */
|
||||
#define FMI_OTP_HIGH_HALFWORD_3 0x0E /* OTP High halfword 3 */
|
||||
#define FMI_OTP_LOW_HALFWORD_4 0x10 /* OTP Low halfword 4 */
|
||||
#define FMI_OTP_HIGH_HALFWORD_4 0x12 /* OTP High halfword 4 */
|
||||
#define FMI_OTP_LOW_HALFWORD_5 0x14 /* OTP Low halfword 5 */
|
||||
#define FMI_OTP_HIGH_HALFWORD_5 0x16 /* OTP High halfword 5 */
|
||||
#define FMI_OTP_LOW_HALFWORD_6 0x18 /* OTP Low halfword 6 */
|
||||
#define FMI_OTP_HIGH_HALFWORD_6 0x1A /* OTP High halfword 6 */
|
||||
#define FMI_OTP_LOW_HALFWORD_7 0x1C /* OTP Low halfword 7 */
|
||||
#define FMI_OTP_HIGH_HALFWORD_7 0x1E /* OTP High halfword 7 */
|
||||
|
||||
/* FMI sectors Masks */
|
||||
|
||||
#define FMI_B0S0_MASK 0x0001 /* FMI B0S0 mask */
|
||||
#define FMI_B0S1_MASK 0x0002 /* FMI B0S1 mask */
|
||||
#define FMI_B0S2_MASK 0x0004 /* FMI B0S2 mask */
|
||||
#define FMI_B0S3_MASK 0x0008 /* FMI B0S3 mask */
|
||||
#define FMI_B0S4_MASK 0x0010 /* FMI B0S4 mask */
|
||||
#define FMI_B0S5_MASK 0x0020 /* FMI B0S5 mask */
|
||||
#define FMI_B0S6_MASK 0x0040 /* FMI B0S6 mask */
|
||||
#define FMI_B0S7_MASK 0x0080 /* FMI B0S7 mask */
|
||||
|
||||
#define FMI_B1S0_MASK 0x0100 /* FMI B1S0 mask */
|
||||
#define FMI_B1S1_MASK 0x0200 /* FMI B1S1 mask */
|
||||
#define FMI_B1S2_MASK 0x0400 /* FMI B1S2 mask */
|
||||
#define FMI_B1S3_MASK 0x0800 /* FMI B1S3 mask */
|
||||
|
||||
/* Timeout error */
|
||||
|
||||
#define FMI_TIME_OUT_ERROR 0x00 /* Timeout error */
|
||||
#define FMI_NO_TIME_OUT_ERROR 0x01 /* No Timeout error */
|
||||
|
||||
/* Module private variables --------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \
|
||||
u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress);
|
||||
void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\
|
||||
u16 FMI_LVDEN, u16 FMI_FreqRange);
|
||||
void FMI_EraseSector(vu32 FMI_Sector);
|
||||
void FMI_EraseBank(vu32 FMI_Bank);
|
||||
void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data);
|
||||
void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData);
|
||||
u32 FMI_ReadWord(u32 FMI_Address);
|
||||
u32 FMI_ReadOTPData(u8 FMI_OTPAddress);
|
||||
FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank);
|
||||
u16 FMI_GetReadWaitStateValue(void);
|
||||
u16 FMI_GetWriteWaitStateValue(void);
|
||||
void FMI_SuspendEnable(vu32 FMI_Bank);
|
||||
void FMI_ResumeEnable(vu32 FMI_Bank);
|
||||
void FMI_ClearFlag(vu32 FMI_Bank);
|
||||
void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState);
|
||||
FlagStatus FMI_GetWriteProtectionStatus(u32 FMI_Sector_Protection);
|
||||
u8 FMI_WaitForLastOperation(vu32 FMI_Bank);
|
||||
|
||||
#endif /* __91x_FMI_H */
|
||||
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
||||
|
||||
93
Demo/ARM9_STR91X_IAR/Library/include/91x_gpio.h
Normal file
93
Demo/ARM9_STR91X_IAR/Library/include/91x_gpio.h
Normal file
@@ -0,0 +1,93 @@
|
||||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : 91x_gpio.h
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : 05/18/2006 : Version 1.0
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* GPIO software library.
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 05/24/2006 : Version 1.1
|
||||
* 05/18/2006 : Version 1.0
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
|
||||
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
|
||||
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
|
||||
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
|
||||
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
|
||||
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
/* Define to prevent recursive inclusion ------------------------------------ */
|
||||
|
||||
#ifndef _91x_GPIO_H
|
||||
#define _91x_GPIO_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "91x_map.h"
|
||||
|
||||
/* GPIO Init structure definition */
|
||||
typedef struct
|
||||
{
|
||||
u8 GPIO_Pin;
|
||||
u8 GPIO_Direction;
|
||||
u8 GPIO_Type;
|
||||
u8 GPIO_IPConnected;
|
||||
u16 GPIO_Alternate;
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
/* Bit_SET and Bit_RESET enumeration */
|
||||
typedef enum
|
||||
{ Bit_RESET = 0,
|
||||
Bit_SET
|
||||
}BitAction;
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
#define GPIO_Pin_None 0x00
|
||||
#define GPIO_Pin_0 0x01
|
||||
#define GPIO_Pin_1 0x02
|
||||
#define GPIO_Pin_2 0x04
|
||||
#define GPIO_Pin_3 0x08
|
||||
#define GPIO_Pin_4 0x10
|
||||
#define GPIO_Pin_5 0x20
|
||||
#define GPIO_Pin_6 0x40
|
||||
#define GPIO_Pin_7 0x80
|
||||
#define GPIO_Pin_All 0xFF
|
||||
|
||||
#define GPIO_PinInput 0x00
|
||||
#define GPIO_PinOutput 0x01
|
||||
|
||||
#define GPIO_Type_PushPull 0x00
|
||||
#define GPIO_Type_OpenCollector 0x01
|
||||
|
||||
#define GPIO_IPConnected_Disable 0x00
|
||||
#define GPIO_IPConnected_Enable 0x01
|
||||
|
||||
#define GPIO_InputAlt1 0x00
|
||||
#define GPIO_OutputAlt1 0x01
|
||||
#define GPIO_OutputAlt2 0x02
|
||||
#define GPIO_OutputAlt3 0x03
|
||||
|
||||
#define GPIO_ANAChannel0 0x01
|
||||
#define GPIO_ANAChannel1 0x02
|
||||
#define GPIO_ANAChannel2 0x04
|
||||
#define GPIO_ANAChannel3 0x08
|
||||
#define GPIO_ANAChannel4 0x10
|
||||
#define GPIO_ANAChannel5 0x20
|
||||
#define GPIO_ANAChannel6 0x40
|
||||
#define GPIO_ANAChannel7 0x80
|
||||
#define GPIO_ANAChannelALL 0xFF
|
||||
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin);
|
||||
u8 GPIO_Read(GPIO_TypeDef* GPIOx);
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal);
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal);
|
||||
void GPIO_EMIConfig(FunctionalState NewState);
|
||||
void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState);
|
||||
|
||||
#endif /* _91x_GPIO_H */
|
||||
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
||||
73
Demo/ARM9_STR91X_IAR/Library/include/91x_it.h
Normal file
73
Demo/ARM9_STR91X_IAR/Library/include/91x_it.h
Normal file
@@ -0,0 +1,73 @@
|
||||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : 91x_it.h
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : 05/18/2006 : Version 1.0
|
||||
* Description : This file contains the headers of the interrupt
|
||||
* handlers'routines
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 05/24/2006 : Version 1.1
|
||||
* 05/18/2006 : Version 1.0
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
|
||||
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
|
||||
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
|
||||
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
|
||||
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
|
||||
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
/* Define to prevent recursive inclusion ------------------------------------ */
|
||||
#ifndef _91x_IT_H
|
||||
#define _91x_IT_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "91x_lib.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Module private variables --------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void Undefined_Handler (void);
|
||||
void SWI_Handler (void);
|
||||
void Prefetch_Handler (void);
|
||||
void Abort_Handler (void);
|
||||
void FIQ_Handler (void);
|
||||
void WDG_IRQHandler (void);
|
||||
void SW_IRQHandler (void);
|
||||
void ARMRX_IRQHandler (void);
|
||||
void ARMTX_IRQHandler (void);
|
||||
void TIM0_IRQHandler (void);
|
||||
void TIM1_IRQHandler (void);
|
||||
void TIM2_IRQHandler (void);
|
||||
void TIM3_IRQHandler (void);
|
||||
void USBHP_IRQHandler (void);
|
||||
void USBLP_IRQHandler (void);
|
||||
void SCU_IRQHandler (void);
|
||||
void ENET_IRQHandler (void);
|
||||
void DMA_IRQHandler (void);
|
||||
void CAN_IRQHandler (void);
|
||||
void MC_IRQHandler (void);
|
||||
void ADC_IRQHandler (void);
|
||||
void UART0_IRQHandler (void);
|
||||
void UART1_IRQHandler (void);
|
||||
void UART2_IRQHandler (void);
|
||||
void I2C0_IRQHandler (void);
|
||||
void I2C1_IRQHandler (void);
|
||||
void SSP0_IRQHandler (void);
|
||||
void SSP1_IRQHandler (void);
|
||||
void LVD_IRQHandler (void);
|
||||
void RTC_IRQHandler (void);
|
||||
void WIU_IRQHandler (void);
|
||||
void EXTIT0_IRQHandler (void);
|
||||
void EXTIT1_IRQHandler (void);
|
||||
void EXTIT2_IRQHandler (void);
|
||||
void EXTIT3_IRQHandler (void);
|
||||
void USBWU_IRQHandler (void);
|
||||
void PFQBC_IRQHandler (void);
|
||||
|
||||
#endif /* _91x_IT_H */
|
||||
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
||||
114
Demo/ARM9_STR91X_IAR/Library/include/91x_lib.h
Normal file
114
Demo/ARM9_STR91X_IAR/Library/include/91x_lib.h
Normal file
@@ -0,0 +1,114 @@
|
||||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : 91x_lib.h
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : 05/18/2006 : Version 1.0
|
||||
* Description : Used to include the peripherals header file in the
|
||||
* user application.
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 05/24/2006 : Version 1.1
|
||||
* 05/18/2006 : Version 1.0
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
|
||||
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
|
||||
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
|
||||
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
|
||||
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
|
||||
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef __91x_LIB_H
|
||||
#define __91x_LIB_H
|
||||
|
||||
#include "91x_map.h"
|
||||
#include "91x_conf.h"
|
||||
|
||||
#ifdef _AHBAPB
|
||||
#include "91x_ahbapb.h"
|
||||
#endif /* _AHBAPB */
|
||||
|
||||
#ifdef _EMI
|
||||
#include "91x_emi.h"
|
||||
#endif /* _EMI */
|
||||
|
||||
#ifdef _DMA
|
||||
#include "91x_dma.h"
|
||||
#endif /* _DMA */
|
||||
|
||||
#ifdef _FMI
|
||||
#include "91x_fmi.h"
|
||||
#endif /* _FMI */
|
||||
|
||||
#ifdef _VIC
|
||||
#include "91x_vic.h"
|
||||
#endif /* _VIC */
|
||||
|
||||
#ifdef _WIU
|
||||
#include "91x_wiu.h"
|
||||
#endif /* _WIU */
|
||||
|
||||
#ifdef _TIM
|
||||
#include "91x_tim.h"
|
||||
#endif /* _TIM */
|
||||
|
||||
#ifdef _GPIO
|
||||
#include "91x_gpio.h"
|
||||
#endif /* _GPIO */
|
||||
|
||||
#ifdef _RTC
|
||||
#include "91x_rtc.h"
|
||||
#endif /* _RTC */
|
||||
|
||||
#ifdef _SCU
|
||||
#include "91x_scu.h"
|
||||
#endif /* _SCU */
|
||||
|
||||
#ifdef _UART
|
||||
#include "91x_uart.h"
|
||||
#endif /* _UART */
|
||||
|
||||
#ifdef _SSP
|
||||
#include "91x_ssp.h"
|
||||
#endif /* _SSP */
|
||||
|
||||
#ifdef _CAN
|
||||
#include "91x_can.h"
|
||||
#endif /* _CAN */
|
||||
|
||||
#ifdef _ADC
|
||||
#include "91x_adc.h"
|
||||
#endif /* _ADC */
|
||||
|
||||
#ifdef _WDG
|
||||
#include "91x_wdg.h"
|
||||
#endif /* _WDG */
|
||||
|
||||
#ifdef _I2C
|
||||
#include "91x_i2c.h"
|
||||
#endif /* _I2C */
|
||||
|
||||
#ifdef _WIU
|
||||
#include "91x_wiu.h"
|
||||
#endif
|
||||
|
||||
#ifdef _MC
|
||||
#include "91x_mc.h"
|
||||
#endif
|
||||
|
||||
#ifdef _ENET
|
||||
#include "91x_enet.h"
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Module private variables --------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
void debug( void );
|
||||
|
||||
|
||||
#endif /* __91x_LIB_H */
|
||||
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
||||
878
Demo/ARM9_STR91X_IAR/Library/include/91x_map.h
Normal file
878
Demo/ARM9_STR91X_IAR/Library/include/91x_map.h
Normal file
File diff suppressed because it is too large
Load Diff
196
Demo/ARM9_STR91X_IAR/Library/include/91x_scu.h
Normal file
196
Demo/ARM9_STR91X_IAR/Library/include/91x_scu.h
Normal file
@@ -0,0 +1,196 @@
|
||||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : 91x_scu.h
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : 05/18/2006 : Version 1.0
|
||||
* Description : This file provides the SCU library software functions
|
||||
* prototypes & definitions
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 05/24/2006 : Version 1.1
|
||||
* 05/18/2006 : Version 1.0
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
|
||||
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
|
||||
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
|
||||
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
|
||||
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
|
||||
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __91x_SCU_H
|
||||
#define __91x_SCU_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "91x_map.h"
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/*MCLK_Source*/
|
||||
#define SCU_MCLK_PLL 0x0
|
||||
#define SCU_MCLK_RTC 0x1
|
||||
#define SCU_MCLK_OSC 0x2
|
||||
|
||||
/*RCLK_Divisor*/
|
||||
#define SCU_RCLK_Div1 0xFFFFFFE3
|
||||
#define SCU_RCLK_Div2 0x4
|
||||
#define SCU_RCLK_Div4 0x8
|
||||
#define SCU_RCLK_Div8 0xC
|
||||
#define SCU_RCLK_Div16 0x10
|
||||
#define SCU_RCLK_Div1024 0x14
|
||||
|
||||
/*HCLK_Divisor*/
|
||||
#define SCU_HCLK_Div1 0xFFFFFF9F
|
||||
#define SCU_HCLK_Div2 0x20
|
||||
#define SCU_HCLK_Div4 0x40
|
||||
|
||||
/*PCLK_Divisor*/
|
||||
#define SCU_PCLK_Div1 0xFFFFFE7F
|
||||
#define SCU_PCLK_Div2 0x80
|
||||
#define SCU_PCLK_Div4 0x100
|
||||
#define SCU_PCLK_Div8 0x180
|
||||
|
||||
/*FMICLK_Divisor*/
|
||||
#define SCU_FMICLK_Div1 0xFFFEFFFF
|
||||
#define SCU_FMICLK_Div2 0x10000
|
||||
|
||||
/*BRCLK_Divisor*/
|
||||
#define SCU_BRCLK_Div1 0xFFFFFDFF
|
||||
#define SCU_BRCLK_Div2 0x200
|
||||
|
||||
/*TIMCLK_Source*/
|
||||
#define SCU_TIMCLK_EXT 0x1
|
||||
#define SCU_TIMCLK_INT 0x0
|
||||
|
||||
/*TIMx*/
|
||||
#define SCU_TIM01 0x0
|
||||
#define SCU_TIM23 0x1
|
||||
|
||||
|
||||
/*USBCLK_Source*/
|
||||
#define SCU_USBCLK_MCLK 0xFFFFF3FF
|
||||
#define SCU_USBCLK_MCLK2 0x400
|
||||
#define SCU_USBCLK_EXT 0x800
|
||||
|
||||
/*SCU_EMIBCLK*/
|
||||
#define SCU_EMIBCLK_Div1 0xFFF9FFFF
|
||||
#define SCU_EMIBCLK_Div2 0x20000
|
||||
|
||||
/*SCU_EMIMODE*/
|
||||
#define SCU_EMI_MUX 0xFFFFFFBF
|
||||
#define SCU_EMI_DEMUX 0x40
|
||||
|
||||
/*SCU_EMIALE_LEN*/
|
||||
#define SCU_EMIALE_LEN1 0xFFFFFEFF
|
||||
#define SCU_EMIALE_LEN2 0x100
|
||||
|
||||
/*SCU_EMIALE_POL*/
|
||||
#define SCU_EMIALE_POLLow 0xFFFFFF7F
|
||||
#define SCU_EMIALE_POLHigh 0x80
|
||||
|
||||
/*UART_IrDA_Mode*/
|
||||
#define SCU_UARTMode_IrDA 0x1
|
||||
#define SCU_UARTMode_UART 0x0
|
||||
|
||||
/*APBPeriph*/
|
||||
#define __TIM01 0x1
|
||||
#define __TIM23 0x2
|
||||
#define __MC 0x4
|
||||
#define __UART0 0x8
|
||||
#define __UART1 0x10
|
||||
#define __UART2 0x20
|
||||
#define __I2C0 0x40
|
||||
#define __I2C1 0x80
|
||||
#define __SSP0 0x100
|
||||
#define __SSP1 0x200
|
||||
#define __CAN 0x400
|
||||
#define __ADC 0x800
|
||||
#define __WDG 0x1000
|
||||
#define __WIU 0x2000
|
||||
#define __GPIO0 0x4000
|
||||
#define __GPIO1 0x8000
|
||||
#define __GPIO2 0x10000
|
||||
#define __GPIO3 0x20000
|
||||
#define __GPIO4 0x40000
|
||||
#define __GPIO5 0x80000
|
||||
#define __GPIO6 0x100000
|
||||
#define __GPIO7 0x200000
|
||||
#define __GPIO8 0x400000
|
||||
#define __GPIO9 0x800000
|
||||
#define __RTC 0x1000000
|
||||
|
||||
/*AHBPeriph*/
|
||||
#define __FMI 0x1
|
||||
#define __FPQBC 0x2
|
||||
#define __SRAM 0x8
|
||||
#define __SRAM_ARBITER 0x10
|
||||
#define __VIC 0x20
|
||||
#define __EMI 0x40
|
||||
#define __EMI_MEM_CLK 0x80
|
||||
#define __DMA 0x100
|
||||
#define __USB 0x200
|
||||
#define __USB48M 0x400
|
||||
#define __ENET 0x800
|
||||
#define __PFQBC_AHB 0x1000
|
||||
|
||||
/*SCU_IT*/
|
||||
#define SCU_IT_LVD_RST 0x10
|
||||
#define SCU_IT_SRAM_ERROR 0x8
|
||||
#define SCU_IT_ACK_PFQBC 0x4
|
||||
#define SCU_IT_LOCK_LOST 0x2
|
||||
#define SCU_IT_LOCK 0x1
|
||||
|
||||
/*SCU_FLAG*/
|
||||
#define SCU_FLAG_SRAM_ERROR 0x20
|
||||
#define SCU_FLAG_ACK_PFQBC 0x10
|
||||
#define SCU_FLAG_LVD_RESET 0x8
|
||||
#define SCU_FLAG_WDG_RST 0x4
|
||||
#define SCU_FLAG_LOCK_LOST 0x2
|
||||
#define SCU_FLAG_LOCK 0x1
|
||||
|
||||
|
||||
/* Module private variables --------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source);
|
||||
ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP);
|
||||
ErrorStatus SCU_PLLCmd(FunctionalState NewState);
|
||||
void SCU_RCLKDivisorConfig(u32 RCLK_Divisor);
|
||||
void SCU_HCLKDivisorConfig(u32 HCLK_Divisor);
|
||||
void SCU_PCLKDivisorConfig(u32 PCLK_Divisor);
|
||||
void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState);
|
||||
void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState);
|
||||
void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState);
|
||||
void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState);
|
||||
void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState);
|
||||
void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState);
|
||||
void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState);
|
||||
void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState);
|
||||
void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor);
|
||||
void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source);
|
||||
void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler);
|
||||
void SCU_USBCLKConfig(u32 USBCLK_Source);
|
||||
void SCU_PHYCLKConfig(FunctionalState NewState);
|
||||
void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor);
|
||||
void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK);
|
||||
void SCU_EMIModeConfig(u32 SCU_EMIMODE);
|
||||
void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL);
|
||||
void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState);
|
||||
FlagStatus SCU_GetFlagStatus(u32 SCU_Flag);
|
||||
void SCU_ClearFlag(u32 SCU_Flag);
|
||||
u32 SCU_GetPLLFreqValue(void);
|
||||
u32 SCU_GetMCLKFreqValue(void);
|
||||
u32 SCU_GetRCLKFreqValue(void);
|
||||
u32 SCU_GetHCLKFreqValue(void);
|
||||
u32 SCU_GetPCLKFreqValue(void);
|
||||
void SCU_WakeUpLineConfig(u8 EXTint);
|
||||
void SCU_SpecIntRunModeConfig(FunctionalState NewState);
|
||||
void SCU_EnterIdleMode(void);
|
||||
void SCU_EnterSleepMode(void);
|
||||
void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode);
|
||||
void SCU_PFQBCCmd(FunctionalState NewState);
|
||||
|
||||
#endif /*__91x_SCU_H*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
||||
155
Demo/ARM9_STR91X_IAR/Library/include/91x_tim.h
Normal file
155
Demo/ARM9_STR91X_IAR/Library/include/91x_tim.h
Normal file
@@ -0,0 +1,155 @@
|
||||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : 91x_tim.h
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : 05/18/2006 : Version 1.0
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* TIM software library.
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 05/24/2006 : Version 1.1
|
||||
* 05/18/2006 : Version 1.0
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
|
||||
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
|
||||
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
|
||||
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
|
||||
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
|
||||
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __91x_TIM_H
|
||||
#define __91x_TIM_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "91x_map.h"
|
||||
#include "91x_scu.h"
|
||||
|
||||
/* Exported types ----------------------------------------------------------- */
|
||||
|
||||
/* TIM Init structure define */
|
||||
typedef struct
|
||||
{
|
||||
u16 TIM_Mode; /* Timer mode */
|
||||
u16 TIM_OC1_Modes; /* Output Compare 1 Mode: Timing or Wave */
|
||||
u16 TIM_OC2_Modes; /* Output Compare 2 Mode: Timing or Wave */
|
||||
u16 TIM_Clock_Source; /* Timer Clock source APB/SCU/EXTERNAL */
|
||||
u16 TIM_Clock_Edge; /* Timer Clock Edge: Rising or Falling Edge */
|
||||
u16 TIM_OPM_INPUT_Edge; /* Timer Input Capture 1 Edge used in OPM Mode */
|
||||
u16 TIM_ICAP1_Edge; /* Timer Input Capture 1 Edge used in ICAP1 Mode */
|
||||
u16 TIM_ICAP2_Edge; /* Timer Input Capture 2 Edge used in ICAP2 Mode */
|
||||
u8 TIM_Prescaler; /* Timer Prescaler factor */
|
||||
u16 TIM_Pulse_Level_1; /* Level applied on the Output Compare Pin 1 */
|
||||
u16 TIM_Pulse_Level_2; /* Level applied on the Output Compare Pin 2 */
|
||||
u16 TIM_Period_Level; /* Level applied during the Period of a PWM Mode */
|
||||
u16 TIM_Pulse_Length_1; /* Pulse 1 Length used in Output Compare 1 Mode */
|
||||
u16 TIM_Pulse_Length_2; /* Pulse 2 Length used in Output Compare 2 Mode */
|
||||
u16 TIM_Full_Period; /* Period Length used in PWM Mode */
|
||||
} TIM_InitTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
TIM_START,
|
||||
TIM_STOP,
|
||||
TIM_CLEAR
|
||||
} TIM_CounterOperations;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* TIM MODE */
|
||||
#define TIM_PWMI 0x4000 /* PWM INPUT Mode */
|
||||
#define TIM_OCM_CHANNEL_1 0x0040 /* OUTPUT COMPARE CHANNEL 1 Mode */
|
||||
#define TIM_OCM_CHANNEL_2 0x0080 /* OUTPUT COMPARE CHANNEL 2 Mode */
|
||||
#define TIM_OCM_CHANNEL_12 0x00C0 /* OUTPUT COMPARE CHANNEL 1 & 2 Mode */
|
||||
#define TIM_PWM 0x0010 /* PWM Mode */
|
||||
#define TIM_OPM 0x0020 /* ONE PULSE Mode */
|
||||
#define TIM_ICAP_CHANNEL_1 0x0400 /* INPUT CAPTURE 1 Mode */
|
||||
#define TIM_ICAP_CHANNEL_2 0x0500 /* INPUT CAPTURE 2 Mode */
|
||||
#define TIM_ICAP_CHANNEL_12 0x0600 /* INPUT CAPTURE 1 & 2 Mode */
|
||||
|
||||
/* TIM OUTPUT COMPARE MODE */
|
||||
#define TIM_WAVE 0x0001
|
||||
#define TIM_TIMING 0x0002
|
||||
|
||||
/* TIM CLOCK SOURCE */
|
||||
#define TIM_CLK_APB 0xFFFE
|
||||
#define TIM_CLK_EXTERNAL 0x0001
|
||||
#define TIM_CLK_SCU 0x0001
|
||||
|
||||
/* TIM CLOCK EDGE */
|
||||
#define TIM_CLK_EDGE_FALLING 0xFFFD
|
||||
#define TIM_CLK_EDGE_RISING 0x0002
|
||||
|
||||
/* TIM OPM INPUT EDGE */
|
||||
#define TIM_OPM_EDGE_FALLING 0xFFFB
|
||||
#define TIM_OPM_EDGE_RISING 0x0004
|
||||
|
||||
/* TIM ICAPA INPUT EDGE */
|
||||
#define TIM_ICAP1_EDGE_FALLING 0xFFFB
|
||||
#define TIM_ICAP1_EDGE_RISING 0x0004
|
||||
|
||||
/* TIM ICAPB INPUT EDGE */
|
||||
#define TIM_ICAP2_EDGE_FALLING 0xFFF7
|
||||
#define TIM_ICAP2_EDGE_RISING 0x0008
|
||||
|
||||
/* TIM OUTPUT LEVEL */
|
||||
#define TIM_HIGH 0x0200
|
||||
#define TIM_LOW 0x0300
|
||||
|
||||
/* TIM OUTPUT EDGE */
|
||||
#define TIM_OUTPUT_EDGE_RISING 0x8000
|
||||
#define TIM_OUTPUT_EDGE_FALLING 0x0800
|
||||
|
||||
/* TIM channels */
|
||||
#define TIM_PWM_OC1_Channel 0x1 /* PWM/Output Compare 1 Channel */
|
||||
#define TIM_OC2_Channel 0x2 /* Output Compare 2 Channel */
|
||||
|
||||
/* TIM DMA SOURCE */
|
||||
#define TIM_DMA_IC1 0x0000 /* Input Capture Channel 1 DMA Source */
|
||||
#define TIM_DMA_OC1 0x1000 /* OUTPUT Compare Channel 1 DMA Source */
|
||||
#define TIM_DMA_IC2 0x2000 /* Input Capture Channel 2 DMA Source */
|
||||
#define TIM_DMA_OC2 0x3000 /* OUTPUT Compare Channel 2 DMA Source */
|
||||
|
||||
/* TIM DMA ENABLE or DISABLE */
|
||||
#define TIM_DMA_ENABLE 0x0400 /* DMA Enable */
|
||||
#define TIM_DMA_DISABLE 0xFBFF /* DMA Disable */
|
||||
|
||||
/* TIM Interruption Sources*/
|
||||
#define TIM_IT_IC1 0x8000 /* Input Capture Channel 1 Interrupt Source */
|
||||
#define TIM_IT_OC1 0x4000 /* Output Compare Channel 1 Interrupt Source */
|
||||
#define TIM_IT_TO 0x2000 /* Timer OverFlow Interrupt Source */
|
||||
#define TIM_IT_IC2 0x1000 /* Input Capture Channel 2 Interrupt Source */
|
||||
#define TIM_IT_OC2 0x0800 /* Output Compare Channel 2 Interrupt Source */
|
||||
|
||||
/* TIM Flags */
|
||||
#define TIM_FLAG_IC1 0x8000 /* Input Capture Channel 1 Flag */
|
||||
#define TIM_FLAG_OC1 0x4000 /* Output Compare Channel 1 Flag */
|
||||
#define TIM_FLAG_TO 0x2000 /* Timer OverFlow Flag */
|
||||
#define TIM_FLAG_IC2 0x1000 /* Input Capture Channel 2 Flag */
|
||||
#define TIM_FLAG_OC2 0x0800 /* Output Compare Channel 2 Flag */
|
||||
|
||||
/* Module private variables --------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void TIM_Init(TIM_TypeDef *TIMx, TIM_InitTypeDef *TIM_InitStruct);
|
||||
void TIM_DeInit(TIM_TypeDef *TIMx);
|
||||
void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct);
|
||||
void TIM_CounterCmd(TIM_TypeDef *TIMx, TIM_CounterOperations TIM_operation);
|
||||
void TIM_PrescalerConfig(TIM_TypeDef *TIMx, u8 TIM_Prescaler);
|
||||
u8 TIM_GetPrescalerValue(TIM_TypeDef *TIMx);
|
||||
u16 TIM_GetCounterValue(TIM_TypeDef *TIMx);
|
||||
u16 TIM_GetICAP1Value(TIM_TypeDef *TIMx);
|
||||
u16 TIM_GetICAP2Value(TIM_TypeDef *TIMx);
|
||||
void TIM_SetPulse(TIM_TypeDef *TIMx,u16 TIM_Channel ,u16 TIM_Pulse);
|
||||
FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, u16 TIM_Flag);
|
||||
void TIM_ClearFlag(TIM_TypeDef *TIMx, u16 TIM_Flag);
|
||||
u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx);
|
||||
u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx);
|
||||
void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState TIM_Newstate);
|
||||
void TIM_DMAConfig(TIM_TypeDef *TIMx, u16 TIM_DMA_Sources);
|
||||
void TIM_DMACmd(TIM_TypeDef *TIMx, FunctionalState TIM_Newstate);
|
||||
|
||||
#endif /* __91x_TIM_H */
|
||||
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
||||
50
Demo/ARM9_STR91X_IAR/Library/include/91x_type.h
Normal file
50
Demo/ARM9_STR91X_IAR/Library/include/91x_type.h
Normal file
@@ -0,0 +1,50 @@
|
||||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : 91x_type.h
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : 05/18/2006 : Version 1.0
|
||||
* Description : It contains common types and constants used in all the
|
||||
* peripherals' drivers.
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 05/24/2006 : Version 1.1
|
||||
* 05/18/2006 : Version 1.0
|
||||
**********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
|
||||
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
|
||||
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
|
||||
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
|
||||
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*********************************************************************************/
|
||||
|
||||
#ifndef __91x_type_H
|
||||
#define __91x_type_H
|
||||
|
||||
typedef long long u64;
|
||||
typedef unsigned long u32;
|
||||
typedef unsigned short u16;
|
||||
typedef unsigned char u8;
|
||||
|
||||
typedef signed long s32;
|
||||
typedef signed short s16;
|
||||
typedef signed char s8;
|
||||
|
||||
typedef volatile unsigned long vu32;
|
||||
typedef volatile unsigned short vu16;
|
||||
typedef volatile unsigned char vu8;
|
||||
|
||||
typedef volatile signed long vs32;
|
||||
typedef volatile signed short vs16;
|
||||
typedef volatile signed char vs8;
|
||||
|
||||
typedef enum { FALSE = 0, TRUE = !FALSE } bool;
|
||||
|
||||
typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus;
|
||||
|
||||
typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
|
||||
|
||||
typedef enum { ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
|
||||
|
||||
#endif /* __91x_type_H */
|
||||
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
||||
174
Demo/ARM9_STR91X_IAR/Library/include/91x_uart.h
Normal file
174
Demo/ARM9_STR91X_IAR/Library/include/91x_uart.h
Normal file
@@ -0,0 +1,174 @@
|
||||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : 91x_uart.h
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : 05/18/2006 : Version 1.0
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* UART software library.
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 05/24/2006 : Version 1.1
|
||||
* 05/18/2006 : Version 1.0
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
|
||||
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
|
||||
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
|
||||
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __91x_UART_H
|
||||
#define __91x_UART_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include <91x_map.h>
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* UART FIFO Level enumeration */
|
||||
typedef enum
|
||||
{
|
||||
UART_FIFOLevel_1_8 = 0x0000, /* FIFO size 16 bytes, FIFO level 2 bytes */
|
||||
UART_FIFOLevel_1_4 = 0x0001, /* FIFO size 16 bytes, FIFO level 4 bytes */
|
||||
UART_FIFOLevel_1_2 = 0x0002, /* FIFO size 16 bytes, FIFO level 8 bytes */
|
||||
UART_FIFOLevel_3_4 = 0x0003, /* FIFO size 16 bytes, FIFO level 12 bytes */
|
||||
UART_FIFOLevel_7_8 = 0x0004 /* FIFO size 16 bytes, FIFO level 14 bytes */
|
||||
}UART_FIFOLevel;
|
||||
|
||||
/* UART Init Structure definition */
|
||||
typedef struct
|
||||
{
|
||||
u16 UART_WordLength;
|
||||
u16 UART_StopBits;
|
||||
u16 UART_Parity;
|
||||
u32 UART_BaudRate;
|
||||
u16 UART_HardwareFlowControl;
|
||||
u16 UART_Mode;
|
||||
u16 UART_FIFO;
|
||||
UART_FIFOLevel UART_TxFIFOLevel;
|
||||
UART_FIFOLevel UART_RxFIFOLevel;
|
||||
}UART_InitTypeDef;
|
||||
|
||||
|
||||
/* UART RTS enumeration */
|
||||
typedef enum
|
||||
{
|
||||
LowLevel = 0,
|
||||
HighLevel
|
||||
}UART_LevelTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* UART Data Length */
|
||||
#define UART_WordLength_5D 0x0000 /* 5 bits Data */
|
||||
#define UART_WordLength_6D 0x0020 /* 6 bits Data */
|
||||
#define UART_WordLength_7D 0x0040 /* 7 bits Data */
|
||||
#define UART_WordLength_8D 0x0060 /* 8 bits Data */
|
||||
|
||||
/* UART Stop Bits */
|
||||
#define UART_StopBits_1 0xFFF7 /* Disable two stop bit is transmitted
|
||||
at the end of frame */
|
||||
#define UART_StopBits_2 0x0008 /* Enable Two stop bits are transmitted
|
||||
at the end of frame */
|
||||
/* UART Parity */
|
||||
#define UART_Parity_No 0x0000 /* Parity Disable */
|
||||
#define UART_Parity_Even 0x0006 /* Even Parity */
|
||||
#define UART_Parity_Odd 0x0002 /* Odd Parity */
|
||||
#define UART_Parity_OddStick 0x0082 /* 1 is transmitted as bit parity */
|
||||
#define UART_Parity_EvenStick 0x0086 /* 0 is transmitted as bit parity */
|
||||
|
||||
/* UART Hardware Flow Control */
|
||||
#define UART_HardwareFlowControl_None 0x0000 /* HFC Disable */
|
||||
#define UART_HardwareFlowControl_RTS 0x4000 /* RTS Enable */
|
||||
#define UART_HardwareFlowControl_CTS 0x8000 /* CTS Enable */
|
||||
#define UART_HardwareFlowControl_RTS_CTS 0xC000 /* CTS and RTS Enable */
|
||||
|
||||
/* UART Mode */
|
||||
#define UART_Mode_Rx 0x0200 /* UART Rx Enabled */
|
||||
#define UART_Mode_Tx 0x0100 /* UART Tx Enbled */
|
||||
#define UART_Mode_Tx_Rx 0x0300 /* UART Tx and Rx Enabled */
|
||||
|
||||
/* UART FIFO */
|
||||
#define UART_FIFO_Disable 0xFFEF /* FIFOs Disable */
|
||||
#define UART_FIFO_Enable 0x0010 /* FIFOs Enable */
|
||||
|
||||
/* UART Interrupt definition */
|
||||
#define UART_IT_OverrunError 0x0400 /* Overrun Error interrupt mask */
|
||||
#define UART_IT_BreakError 0x0200 /* Break Error interrupt mask */
|
||||
#define UART_IT_ParityError 0x0100 /* Parity Error interrupt mask */
|
||||
#define UART_IT_FrameError 0x0080 /* Frame Error interrupt mask */
|
||||
#define UART_IT_ReceiveTimeOut 0x0040 /* Receive Time Out interrupt mask */
|
||||
#define UART_IT_Transmit 0x0020 /* Transmit interrupt mask */
|
||||
#define UART_IT_Receive 0x0010 /* Receive interrupt mask */
|
||||
#define UART_IT_DSR 0x0008 /* DSR interrupt mask */
|
||||
#define UART_IT_DCD 0x0004 /* DCD interrupt mask */
|
||||
#define UART_IT_CTS 0x0002 /* CTS interrupt mask */
|
||||
#define UART_IT_RI 0x0001 /* RI interrupt mask */
|
||||
|
||||
/* UART DMA On Error */
|
||||
#define UART_DMAOnError_Enable 0xFFFB /* DMA receive request enabled
|
||||
when the UART error interrupt
|
||||
is asserted. */
|
||||
#define UART_DMAOnError_Disable 0x0004 /* DMA receive request disabled
|
||||
when the UART error interrupt
|
||||
is asserted. */
|
||||
/* UART DMA Request */
|
||||
#define UART_DMAReq_Tx 0x02 /* Transmit DMA Enable */
|
||||
#define UART_DMAReq_Rx 0x01 /* Receive DMA Enable */
|
||||
|
||||
/* UART FLAG */
|
||||
#define UART_FLAG_OverrunError 0x23 /* Overrun error flag */
|
||||
#define UART_FLAG_Break 0x22 /* break error flag */
|
||||
#define UART_FLAG_ParityError 0x21 /* parity error flag */
|
||||
#define UART_FLAG_FrameError 0x20 /* frame error flag */
|
||||
#define UART_FLAG_RI 0x48 /* RI flag */
|
||||
#define UART_FLAG_TxFIFOEmpty 0x47 /* Transmit FIFO Empty flag */
|
||||
#define UART_FLAG_RxFIFOFull 0x46 /* Receive FIFO Full flag */
|
||||
#define UART_FLAG_TxFIFOFull 0x45 /* Transmit FIFO Full flag */
|
||||
#define UART_FLAG_RxFIFOEmpty 0x44 /* Receive FIFO Empty flag */
|
||||
#define UART_FLAG_Busy 0x43 /* UART Busy flag */
|
||||
#define UART_FLAG_DCD 0x42 /* DCD flag */
|
||||
#define UART_FLAG_DSR 0x41 /* DSR flag */
|
||||
#define UART_FLAG_CTS 0x40 /* CTS flag */
|
||||
#define UART_RawIT_OverrunError 0x6A /* Overrun Error Raw IT flag */
|
||||
#define UART_RawIT_BreakError 0x69 /* Break Error Raw IT flag */
|
||||
#define UART_RawIT_ParityError 0x68 /* Parity Error Raw IT flag */
|
||||
#define UART_RawIT_FrameError 0x67 /* Frame Error Raw IT flag */
|
||||
#define UART_RawIT_ReceiveTimeOut 0x66 /* ReceiveTimeOut Raw IT flag */
|
||||
#define UART_RawIT_Transmit 0x65 /* Transmit Raw IT flag */
|
||||
#define UART_RawIT_Receive 0x64 /* Receive Raw IT flag */
|
||||
#define UART_RawIT_DSR 0x63 /* DSR Raw IT flag */
|
||||
#define UART_RawIT_DCD 0x62 /* DCD Raw IT flag */
|
||||
#define UART_RawIT_CTS 0x61 /* CTS Raw IT flag */
|
||||
#define UART_RawIT_RI 0x60 /* RI Raw IT flag */
|
||||
|
||||
/*IrDAx select*/
|
||||
#define IrDA0 0x01 /*IrDA0 select*/
|
||||
#define IrDA1 0x02 /*IrDA0 select*/
|
||||
#define IrDA2 0x03 /*IrDA0 select*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void UART_DeInit(UART_TypeDef* UARTx);
|
||||
void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct);
|
||||
void UART_StructInit(UART_InitTypeDef* UART_InitStruct);
|
||||
void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState);
|
||||
void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState);
|
||||
void UART_DMAConfig(UART_TypeDef* UARTx, u16 UART_DMAOnError);
|
||||
void UART_DMACmd(UART_TypeDef* UARTx, u8 UART_DMAReq, FunctionalState NewState);
|
||||
void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState);
|
||||
FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG);
|
||||
void UART_ClearFlag(UART_TypeDef* UARTx);
|
||||
void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT);
|
||||
void UART_IrDALowPowerConfig(u8 IrDAx, FunctionalState NewState);
|
||||
void UART_IrDACmd(u8 IrDAx, FunctionalState NewState);
|
||||
void UART_IrDASetCounter(u8 IrDAx, u32 IrDA_Counter);
|
||||
void UART_SendData(UART_TypeDef* UARTx, u8 Data);
|
||||
u8 UART_ReceiveData(UART_TypeDef* UARTx);
|
||||
void UART_SendBreak(UART_TypeDef* UARTx);
|
||||
void UART_DTRConfig(UART_LevelTypeDef LevelState);
|
||||
void UART_RTSConfig(UART_LevelTypeDef LevelState);
|
||||
ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT);
|
||||
|
||||
#endif /* __91x_UART_H */
|
||||
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
||||
94
Demo/ARM9_STR91X_IAR/Library/include/91x_vic.h
Normal file
94
Demo/ARM9_STR91X_IAR/Library/include/91x_vic.h
Normal file
@@ -0,0 +1,94 @@
|
||||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : 91x_vic.h
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : 05/18/2006 : Version 1.0
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* VIC software library.
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 05/24/2006 : Version 1.1
|
||||
* 05/18/2006 : Version 1.0
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
|
||||
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
|
||||
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
|
||||
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
|
||||
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
|
||||
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion ------------------------------------ */
|
||||
#ifndef __91x_VIC_H
|
||||
#define __91x_VIC_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "91x_map.h"
|
||||
#include "91x_it.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Type of interrupt */
|
||||
typedef enum
|
||||
{
|
||||
VIC_IRQ,
|
||||
VIC_FIQ
|
||||
} VIC_ITLineMode;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* VIC sources*/
|
||||
|
||||
#define WDG_ITLine 0
|
||||
#define SW_ITLine 1
|
||||
#define ARMRX_ITLine 2
|
||||
#define ARMTX_ITLine 3
|
||||
#define TIM0_ITLine 4
|
||||
#define TIM1_ITLine 5
|
||||
#define TIM2_ITLine 6
|
||||
#define TIM3_ITLine 7
|
||||
#define USBHP_ITLine 8
|
||||
#define USBLP_ITLine 9
|
||||
#define SCU_ITLine 10
|
||||
#define ENET_ITLine 11
|
||||
#define DMA_ITLine 12
|
||||
#define CAN_ITLine 13
|
||||
#define MC_ITLine 14
|
||||
#define ADC_ITLine 15
|
||||
#define UART0_ITLine 16
|
||||
#define UART1_ITLine 17
|
||||
#define UART2_ITLine 18
|
||||
#define I2C0_ITLine 19
|
||||
#define I2C1_ITLine 20
|
||||
#define SSP0_ITLine 21
|
||||
#define SSP1_ITLine 22
|
||||
#define LVD_ITLine 23
|
||||
#define RTC_ITLine 24
|
||||
#define WIU_ITLine 25
|
||||
#define EXTIT0_ITLine 26
|
||||
#define EXTIT1_ITLine 27
|
||||
#define EXTIT2_ITLine 28
|
||||
#define EXTIT3_ITLine 29
|
||||
#define USBWU_ITLine 30
|
||||
#define PFQBC_ITLine 31
|
||||
|
||||
|
||||
/* Module private variables --------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
void VIC_DeInit(void);
|
||||
FlagStatus VIC_GetIRQStatus(u16 VIC_Source);
|
||||
FlagStatus VIC_GetFIQStatus(u16 VIC_Source);
|
||||
FlagStatus VIC_GetSourceITStatus(u16 VIC_Source);
|
||||
void VIC_ITCmd(u16 VIC_Source, FunctionalState VIC_NewState);
|
||||
void VIC_SWITCmd(u16 VIC_Source, FunctionalState VIC_NewState);
|
||||
void VIC_ProtectionCmd(FunctionalState VIC_NewState);
|
||||
u32 VIC_GetCurrentISRAdd(VIC_TypeDef* VICx);
|
||||
u32 VIC_GetISRVectAdd(u16 VIC_Source);
|
||||
void VIC_Config(u16 VIC_Source, VIC_ITLineMode VIC_LineMode, u8 VIC_Priority);
|
||||
|
||||
#endif /* __91x_VIC_H */
|
||||
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
||||
|
||||
82
Demo/ARM9_STR91X_IAR/Library/include/91x_wdg.h
Normal file
82
Demo/ARM9_STR91X_IAR/Library/include/91x_wdg.h
Normal file
@@ -0,0 +1,82 @@
|
||||
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
|
||||
* File Name : 91x_wdg.h
|
||||
* Author : MCD Application Team
|
||||
* Date First Issued : 05/18/2006 : Version 1.0
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* WDG software library.
|
||||
********************************************************************************
|
||||
* History:
|
||||
* 05/24/2006 : Version 1.1
|
||||
* 05/18/2006 : Version 1.0
|
||||
********************************************************************************
|
||||
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
|
||||
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
|
||||
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
|
||||
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*******************************************************************************/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __91x_WDG_H
|
||||
#define __91x_WDG_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "91x_map.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
u16 WDG_Mode;
|
||||
u16 WDG_ClockSource;
|
||||
u16 WDG_Prescaler;
|
||||
u16 WDG_Preload;
|
||||
|
||||
} WDG_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* WDG_Mode */
|
||||
#define WDG_Mode_Wdg 0x0001 /*WDG configured to run in watchdog mode.*/
|
||||
#define WDG_Mode_Timer 0xFFFE /*WDG configured to be in Free-running Timer mode.*/
|
||||
|
||||
|
||||
/* WDG_ClockSource */
|
||||
#define WDG_ClockSource_Rtc 0x0004 /* External clock ( 32 khz RTC clock ) will be used as counting clock.*/
|
||||
#define WDG_ClockSource_Apb 0xFFFB /*The APB clock signal will be used as counting clock.*/
|
||||
|
||||
/* WDG_Prescaler */
|
||||
/*This member must be a number between 0x00 and 0xFF.
|
||||
Specifies the Prescaler value to divide the clock source.
|
||||
The clock of the Watchdog Timer Counter is divided by " WDG_Prescaler + 1".*/
|
||||
|
||||
|
||||
|
||||
/* WDG_Preload */
|
||||
/*This member must be a number between 0x0000 and 0xFFFF.
|
||||
This value is loaded in the WDG Counter when it starts counting.*/
|
||||
|
||||
|
||||
/* WDG Sequence */
|
||||
#define WDG_KeyValue1 0xA55A
|
||||
#define WDG_KeyValue2 0x5AA5
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
void WDG_DeInit(void);
|
||||
void WDG_Init(WDG_InitTypeDef* WDG_InitStruct);
|
||||
void WDG_StructInit(WDG_InitTypeDef* WDG_InitStruct);
|
||||
void WDG_Cmd(FunctionalState NewState);
|
||||
void WDG_ITConfig(FunctionalState NewState);
|
||||
u16 WDG_GetCounter(void);
|
||||
FlagStatus WDG_GetFlagStatus(void);
|
||||
void WDG_ClearFlag(void);
|
||||
ITStatus WDG_GetITStatus(void);
|
||||
void WDG_ClearITPendingBit(void);
|
||||
|
||||
#endif /* __WDG_H */
|
||||
|
||||
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|
||||
768
Demo/ARM9_STR91X_IAR/Library/source/91x_can.c
Normal file
768
Demo/ARM9_STR91X_IAR/Library/source/91x_can.c
Normal file
File diff suppressed because it is too large
Load Diff
588
Demo/ARM9_STR91X_IAR/Library/source/91x_enet.c
Normal file
588
Demo/ARM9_STR91X_IAR/Library/source/91x_enet.c
Normal file
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user