mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2025-12-13 11:25:24 +08:00
Sebastian Huber
416
bsps/shared/grlib/i2c/i2cmst.c
Normal file
416
bsps/shared/grlib/i2c/i2cmst.c
Normal file
@@ -0,0 +1,416 @@
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/*
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* Driver for GRLIB port of OpenCores I2C-master
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*
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* COPYRIGHT (c) 2007 Cobham Gaisler AB
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* based on the RTEMS MPC83xx I2C driver (c) 2007 Embedded Brains GmbH.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*
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* This file contains the driver and initialization code
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*/
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#include <bsp.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <grlib/ambapp.h>
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#include <rtems/libi2c.h>
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#include <drvmgr/drvmgr.h>
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#include <grlib/ambapp_bus.h>
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#include <grlib/i2cmst.h>
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#include <grlib/grlib_impl.h>
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/* Enable debug printks? */
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/*#define DEBUG*/
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#ifdef DEBUG
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#define DBG(args...) printk(args)
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#else
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#define DBG(args...)
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#endif
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/* The OC I2C core will perform a write after a start unless the RD bit
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in the command register has been set. Since the rtems framework has
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a send_start function we buffer that command and use it when the first
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data is written. The START is buffered in the sendstart member below */
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typedef struct gr_i2cmst_prv {
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rtems_libi2c_bus_t i2clib_desc;
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struct drvmgr_dev *dev;
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gr_i2cmst_regs_t *reg_ptr;
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unsigned int sysfreq; /* System clock frequency in kHz */
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int minor;
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unsigned char sendstart; /* START events are buffered here */
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/* rtems_irq_number irq_number; */
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/* rtems_id irq_sema_id; */
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} gr_i2cmst_prv_t;
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/* Calculates the scaler value for 100 kHz operation */
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static int gr_i2cmst_calc_scaler(int sysfreq)
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{
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return sysfreq/500 - 1;
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}
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/* Wait for the current transfer to end */
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static int gr_i2cmst_wait(gr_i2cmst_prv_t *prv_ptr, uint8_t expected_sts)
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{
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uint32_t tout = 0;
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int current_sts;
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DBG("(gr_i2cmst_wait called...");
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do {
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if (tout++ > 1000000) {
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DBG("gr_i2cmst_wait: TIMEOUT\n");
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return RTEMS_TIMEOUT;
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}
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} while (prv_ptr->reg_ptr->cmdsts & GRI2C_STS_TIP);
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current_sts = prv_ptr->reg_ptr->cmdsts & ~GRI2C_STS_IF & ~GRI2C_STS_BUSY;
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if (current_sts != expected_sts) {
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#if defined(DEBUG)
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if (prv_ptr->reg_ptr->cmdsts & GRI2C_STS_RXACK) {
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DBG("Transfer NAKed..");
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}
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if (prv_ptr->reg_ptr->cmdsts & GRI2C_STS_AL) {
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DBG("arbitration lost..");
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}
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if (prv_ptr->reg_ptr->cmdsts & GRI2C_STS_TIP) {
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DBG("transfer still in progress, huh?..");
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}
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DBG("exited with IO error..)");
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#endif
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DBG("gr_i2cmst_wait: IO-ERROR\n");
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return RTEMS_IO_ERROR;
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}
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DBG("exited...)");
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return RTEMS_SUCCESSFUL;
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}
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/* Initialize hardware core */
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static rtems_status_code gr_i2cmst_init(rtems_libi2c_bus_t *bushdl)
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{
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gr_i2cmst_prv_t *prv_ptr = (gr_i2cmst_prv_t *)bushdl;
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DBG("gr_i2cmst_init called...");
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/* Disable core before changing prescale register */
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prv_ptr->reg_ptr->ctrl = 0;
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/* Calculate and set prescale value */
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prv_ptr->reg_ptr->prescl = gr_i2cmst_calc_scaler(prv_ptr->sysfreq);
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/* Enable core, interrupts are not enabled */
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prv_ptr->reg_ptr->ctrl = GRI2C_CTRL_EN;
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/* Clear possible START condition */
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prv_ptr->sendstart = 0;
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DBG("exited\n");
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return RTEMS_SUCCESSFUL;
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}
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static rtems_status_code gr_i2cmst_send_start(rtems_libi2c_bus_t *bushdl)
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{
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gr_i2cmst_prv_t *prv_ptr = (gr_i2cmst_prv_t *)bushdl;
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DBG("gr_i2cmst_send_start called...");
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/* The OC I2C core does not work with stand alone START events,
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instead the event is buffered */
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prv_ptr->sendstart = GRI2C_CMD_STA;
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DBG("exited\n");
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return RTEMS_SUCCESSFUL;
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}
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static rtems_status_code gr_i2cmst_send_stop(rtems_libi2c_bus_t *bushdl)
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{
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gr_i2cmst_prv_t *prv_ptr = (gr_i2cmst_prv_t *)bushdl;
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DBG("gr_i2cmst_send_stop called...");
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prv_ptr->reg_ptr->cmdsts = GRI2C_CMD_STO;
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DBG("exited\n");
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return RTEMS_SUCCESSFUL;
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}
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static rtems_status_code gr_i2cmst_send_addr(rtems_libi2c_bus_t *bushdl,
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uint32_t addr, int rw)
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{
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gr_i2cmst_prv_t *prv_ptr = (gr_i2cmst_prv_t *)bushdl;
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uint8_t addr_byte;
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rtems_status_code rc;
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DBG("gr_i2cmst_send_addr called, addr = 0x%x, rw = %d...",
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addr, rw);
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/* Check if long address is needed */
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if (addr > 0x7f) {
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addr_byte = ((addr >> 7) & 0x06) | (rw ? 1 : 0);
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prv_ptr->reg_ptr->tdrd = addr_byte;
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prv_ptr->reg_ptr->cmdsts = GRI2C_CMD_WR | prv_ptr->sendstart;
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prv_ptr->sendstart = 0;
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/* Wait for transfer to complete */
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rc = gr_i2cmst_wait(prv_ptr, GRI2C_STATUS_IDLE);
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if (rc != RTEMS_SUCCESSFUL) {
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DBG("exited with error\n");
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return -rc;
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}
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}
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/* For 10-bit adresses the last byte should only be written for a
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write operation */
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rc = RTEMS_SUCCESSFUL;
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if (addr <= 0x7f || rw == 0) {
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addr_byte = (addr << 1) | (rw ? 1 : 0);
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prv_ptr->reg_ptr->tdrd = addr_byte;
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prv_ptr->reg_ptr->cmdsts = GRI2C_CMD_WR | prv_ptr->sendstart;
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prv_ptr->sendstart = 0;
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/* Wait for transfer to complete */
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rc = gr_i2cmst_wait(prv_ptr, GRI2C_STATUS_IDLE);
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if (rc != RTEMS_SUCCESSFUL) {
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DBG("exited with error\n");
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return -rc;
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}
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}
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DBG("exited\n");
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return rc;
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}
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static int gr_i2cmst_read_bytes(rtems_libi2c_bus_t *bushdl,
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unsigned char *bytes, int nbytes)
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{
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gr_i2cmst_prv_t *prv_ptr = (gr_i2cmst_prv_t *)bushdl;
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unsigned char *buf = bytes;
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rtems_status_code rc;
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unsigned char expected_sts = GRI2C_STATUS_IDLE;
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DBG("gr_i2cmst_read_bytes called, nbytes = %d...", nbytes);
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while (nbytes-- > 0) {
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if (nbytes == 0) {
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/* Respond with NAK to end sequential read */
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prv_ptr->reg_ptr->cmdsts = (GRI2C_CMD_RD | GRI2C_CMD_ACK |
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prv_ptr->sendstart);
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expected_sts = GRI2C_STS_RXACK;
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} else {
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prv_ptr->reg_ptr->cmdsts = GRI2C_CMD_RD | prv_ptr->sendstart;
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}
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prv_ptr->sendstart = 0;
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/* Wait until end of transfer */
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rc = gr_i2cmst_wait(prv_ptr, expected_sts);
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if (rc != RTEMS_SUCCESSFUL) {
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DBG("exited with error\n");
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return -rc;
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}
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*buf++ = prv_ptr->reg_ptr->tdrd;
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}
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DBG("exited\n");
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return buf - bytes;
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}
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static int gr_i2cmst_write_bytes(rtems_libi2c_bus_t *bushdl,
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unsigned char *bytes, int nbytes)
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{
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gr_i2cmst_prv_t *prv_ptr = (gr_i2cmst_prv_t *)bushdl;
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unsigned char *buf = bytes;
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rtems_status_code rc;
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DBG("gr_i2cmst_write_bytes called, nbytes = %d...", nbytes);
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while (nbytes-- > 0) {
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DBG("writing byte 0x%02X...", *buf);
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prv_ptr->reg_ptr->tdrd = *buf++;
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prv_ptr->reg_ptr->cmdsts = GRI2C_CMD_WR | prv_ptr->sendstart;
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prv_ptr->sendstart = 0;
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/* Wait for transfer to complete */
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rc = gr_i2cmst_wait(prv_ptr, GRI2C_STATUS_IDLE);
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if (rc != RTEMS_SUCCESSFUL) {
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DBG("exited with error\n");
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return -rc;
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}
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}
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DBG("exited\n");
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return buf - bytes;
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}
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static rtems_libi2c_bus_ops_t gr_i2cmst_ops = {
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init: gr_i2cmst_init,
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send_start: gr_i2cmst_send_start,
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send_stop: gr_i2cmst_send_stop,
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send_addr: gr_i2cmst_send_addr,
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read_bytes: gr_i2cmst_read_bytes,
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write_bytes: gr_i2cmst_write_bytes,
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};
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/* Get Hardware and disable it */
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static int i2cmst_device_init(gr_i2cmst_prv_t *priv)
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{
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struct amba_dev_info *ambadev;
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struct ambapp_core *pnpinfo;
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/* Get device information from AMBA PnP information */
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ambadev = (struct amba_dev_info *)priv->dev->businfo;
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if ( ambadev == NULL ) {
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return -1;
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}
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pnpinfo = &ambadev->info;
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priv->reg_ptr = (gr_i2cmst_regs_t *)pnpinfo->apb_slv->start;
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/* Disable core */
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priv->reg_ptr->ctrl = 0;
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priv->i2clib_desc.ops = &gr_i2cmst_ops;
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priv->i2clib_desc.size = sizeof(gr_i2cmst_ops);
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return 0;
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}
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/******************* Driver Manager Part ***********************/
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int i2cmst_init2(struct drvmgr_dev *dev);
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int i2cmst_init3(struct drvmgr_dev *dev);
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struct drvmgr_drv_ops i2cmst_ops =
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{
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.init = {NULL, i2cmst_init2, i2cmst_init3, NULL},
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.remove = NULL,
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.info = NULL
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};
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struct amba_dev_id i2cmst_ids[] =
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{
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{VENDOR_GAISLER, GAISLER_I2CMST},
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{0, 0} /* Mark end of table */
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};
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struct amba_drv_info i2cmst_drv_info =
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{
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{
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DRVMGR_OBJ_DRV, /* Driver */
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NULL, /* Next driver */
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NULL, /* Device list */
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DRIVER_AMBAPP_GAISLER_I2CMST_ID, /* Driver ID */
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"I2CMST_DRV", /* Driver Name */
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DRVMGR_BUS_TYPE_AMBAPP, /* Bus Type */
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&i2cmst_ops,
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NULL, /* Funcs */
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0, /* No devices yet */
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0,
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},
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&i2cmst_ids[0]
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};
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void i2cmst_register_drv (void)
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{
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DBG("Registering I2CMST driver\n");
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drvmgr_drv_register(&i2cmst_drv_info.general);
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}
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/* The I2CMST Driver is informed about a new hardware device */
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int i2cmst_init2(struct drvmgr_dev *dev)
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{
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gr_i2cmst_prv_t *priv;
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DBG("I2CMST[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name);
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priv = dev->priv = grlib_calloc(1, sizeof(*priv));
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if ( !priv )
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return DRVMGR_NOMEM;
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priv->dev = dev;
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/* This core will not find other cores, so we wait for init2() */
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return DRVMGR_OK;
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}
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/* Init stage 2 */
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int i2cmst_init3(struct drvmgr_dev *dev)
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{
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gr_i2cmst_prv_t *priv;
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char prefix[32];
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char devName[32];
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int rc;
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priv = (gr_i2cmst_prv_t *)dev->priv;
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/* Do initialization */
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/* Initialize i2c library */
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rc = rtems_libi2c_initialize();
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if (rc != 0) {
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DBG("I2CMST: rtems_libi2c_initialize failed, exiting...\n");
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free(dev->priv);
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dev->priv = NULL;
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return DRVMGR_FAIL;
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}
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/* I/O system registered and initialized
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* Now we take care of device initialization.
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*/
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/* Get frequency */
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if ( drvmgr_freq_get(dev, DEV_APB_SLV, &priv->sysfreq) ) {
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return DRVMGR_FAIL;
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}
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priv->sysfreq = priv->sysfreq / 1000; /* Convert to kHz */
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if ( i2cmst_device_init(priv) ) {
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free(dev->priv);
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dev->priv = NULL;
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return DRVMGR_FAIL;
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}
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/* Get Filesystem name prefix */
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prefix[0] = '\0';
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if ( drvmgr_get_dev_prefix(dev, prefix) ) {
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/* Failed to get prefix, make sure of a unique FS name
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* by using the driver minor.
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*/
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sprintf(devName, "/dev/i2c%d", dev->minor_drv+1);
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} else {
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/* Got special prefix, this means we have a bus prefix
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||||
* And we should use our "bus minor"
|
||||
*/
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sprintf(devName, "/dev/%si2c%d", prefix, dev->minor_bus+1);
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||||
}
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||||
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||||
/* Register Bus for this Device */
|
||||
rc = rtems_libi2c_register_bus(devName, &priv->i2clib_desc);
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||||
if (rc < 0) {
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||||
DBG("I2CMST: rtems_libi2c_register_bus(%s) failed, exiting..\n", devName);
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free(dev->priv);
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||||
dev->priv = NULL;
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||||
return DRVMGR_FAIL;
|
||||
}
|
||||
priv->minor = rc;
|
||||
|
||||
return DRVMGR_OK;
|
||||
}
|
||||
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