1998-06-22 09:28:03 +00:00
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/*
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* This file contains the termios TTY driver for the Motorola MC68681.
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*
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* This part is available from a number of secondary sources.
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* In particular, we know about the following:
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*
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* + Exar 88c681 and 68c681
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*
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* COPYRIGHT (c) 1989-1998.
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* On-Line Applications Research Corporation (OAR).
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* Copyright assigned to U.S. Government, 1994.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* $Id$
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*/
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#include <rtems.h>
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#include <rtems/libio.h>
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#include <stdlib.h>
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#include <ringbuf.h>
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#include <libchip/serial.h>
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#include "mc68681_p.h"
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1998-06-22 11:09:32 +00:00
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#include "mc68681.h"
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1998-06-22 09:28:03 +00:00
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/*
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* Flow control is only supported when using interrupts
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*/
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1998-06-22 10:17:14 +00:00
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1998-06-22 09:28:03 +00:00
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console_flow mc68681_flow_RTSCTS =
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{
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mc68681_negate_RTS, /* deviceStopRemoteTx */
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mc68681_assert_RTS /* deviceStartRemoteTx */
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};
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console_flow mc68681_flow_DTRCTS =
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{
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mc68681_negate_DTR, /* deviceStopRemoteTx */
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mc68681_assert_DTR /* deviceStartRemoteTx */
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};
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console_fns mc68681_fns =
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{
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mc68681_probe, /* deviceProbe */
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mc68681_open, /* deviceFirstOpen */
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mc68681_flush, /* deviceLastClose */
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NULL, /* deviceRead */
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mc68681_write_support_int, /* deviceWrite */
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mc68681_initialize_interrupts, /* deviceInitialize */
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mc68681_write_polled, /* deviceWritePolled */
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FALSE, /* deviceOutputUsesInterrupts */
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};
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console_fns mc68681_fns_polled =
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{
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mc68681_probe, /* deviceProbe */
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mc68681_open, /* deviceFirstOpen */
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mc68681_close, /* deviceLastClose */
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mc68681_inbyte_nonblocking_polled, /* deviceRead */
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mc68681_write_support_polled, /* deviceWrite */
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mc68681_init, /* deviceInitialize */
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mc68681_write_polled, /* deviceWritePolled */
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FALSE, /* deviceOutputUsesInterrupts */
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};
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extern void set_vector( rtems_isr_entry, rtems_vector_number, int );
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/*
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* Console Device Driver Entry Points
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*/
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1998-06-22 10:17:14 +00:00
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1998-06-22 09:28:03 +00:00
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static boolean mc68681_probe(int minor)
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{
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/*
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1998-06-22 11:09:32 +00:00
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* If the configuration dependent probe has located the device then
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1998-06-22 09:28:03 +00:00
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* assume it is there
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*/
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return(TRUE);
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}
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static void mc68681_init(int minor)
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{
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1998-06-22 11:09:32 +00:00
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/* XXX */
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1998-06-22 09:28:03 +00:00
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unsigned32 pMC68681;
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unsigned8 ucTrash;
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unsigned8 ucDataByte;
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unsigned32 ulBaudDivisor;
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1998-06-22 11:09:32 +00:00
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mc68681_context *pmc68681Context;
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1998-06-22 09:28:03 +00:00
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setRegister_f setReg;
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getRegister_f getReg;
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1998-06-22 11:09:32 +00:00
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#if 1
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ulBaudDivisor = ucDataByte = ucTrash = 0;
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#endif
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pmc68681Context = (mc68681_context *) malloc(sizeof(mc68681_context));
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1998-06-22 09:28:03 +00:00
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1998-06-22 11:09:32 +00:00
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Console_Port_Data[minor].pDeviceContext = (void *)pmc68681Context;
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#if 0
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pmc68681Context->ucModemCtrl = SP_MODEM_IRQ;
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#endif
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1998-06-22 09:28:03 +00:00
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pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
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setReg = Console_Port_Tbl[minor].setRegister;
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getReg = Console_Port_Tbl[minor].getRegister;
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1998-06-22 11:09:32 +00:00
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#if 0
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1998-06-22 09:28:03 +00:00
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/* Clear the divisor latch, clear all interrupt enables,
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* and reset and
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* disable the FIFO's.
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*/
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1998-06-22 11:09:32 +00:00
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(*setReg)(pMC68681, MC68681_LINE_CONTROL, 0x0);
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(*setReg)(pMC68681, MC68681_INTERRUPT_ENABLE, 0x0);
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1998-06-22 09:28:03 +00:00
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/* Set the divisor latch and set the baud rate. */
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ulBaudDivisor=MC68681_Baud((unsigned32)Console_Port_Tbl[minor].pDeviceParams);
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ucDataByte = SP_LINE_DLAB;
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1998-06-22 11:09:32 +00:00
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(*setReg)(pMC68681, MC68681_LINE_CONTROL, ucDataByte);
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(*setReg)(pMC68681, MC68681_TRANSMIT_BUFFER, ulBaudDivisor&0xff);
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(*setReg)(pMC68681, MC68681_INTERRUPT_ENABLE, (ulBaudDivisor>>8)&0xff);
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1998-06-22 09:28:03 +00:00
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/* Clear the divisor latch and set the character size to eight bits */
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/* with one stop bit and no parity checking. */
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ucDataByte = EIGHT_BITS;
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1998-06-22 11:09:32 +00:00
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(*setReg)(pMC68681, MC68681_LINE_CONTROL, ucDataByte);
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1998-06-22 09:28:03 +00:00
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/* Enable and reset transmit and receive FIFOs. TJA */
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ucDataByte = SP_FIFO_ENABLE;
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1998-06-22 11:09:32 +00:00
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(*setReg)(pMC68681, MC68681_FIFO_CONTROL, ucDataByte);
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1998-06-22 09:28:03 +00:00
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ucDataByte = SP_FIFO_ENABLE | SP_FIFO_RXRST | SP_FIFO_TXRST;
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1998-06-22 11:09:32 +00:00
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(*setReg)(pMC68681, MC68681_FIFO_CONTROL, ucDataByte);
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1998-06-22 09:28:03 +00:00
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/*
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* Disable interrupts
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*/
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ucDataByte = 0;
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1998-06-22 11:09:32 +00:00
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(*setReg)(pMC68681, MC68681_INTERRUPT_ENABLE, ucDataByte);
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1998-06-22 09:28:03 +00:00
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/* Set data terminal ready. */
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/* And open interrupt tristate line */
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1998-06-22 11:09:32 +00:00
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(*setReg)(pMC68681, MC68681_MODEM_CONTROL,pmc68681Context->ucModemCtrl);
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1998-06-22 09:28:03 +00:00
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1998-06-22 11:09:32 +00:00
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ucTrash = (*getReg)(pMC68681, MC68681_LINE_STATUS );
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ucTrash = (*getReg)(pMC68681, MC68681_RECEIVE_BUFFER );
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#endif
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1998-06-22 09:28:03 +00:00
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}
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static int mc68681_open(
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int major,
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int minor,
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void * arg
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)
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{
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1998-06-22 11:09:32 +00:00
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/* XXX */
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1998-06-22 09:28:03 +00:00
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/*
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* Assert DTR
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*/
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if(Console_Port_Tbl[minor].pDeviceFlow != &mc68681_flow_DTRCTS) {
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mc68681_assert_DTR(minor);
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}
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return(RTEMS_SUCCESSFUL);
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}
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static int mc68681_close(
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int major,
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int minor,
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void * arg
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)
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{
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1998-06-22 11:09:32 +00:00
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/* XXX */
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1998-06-22 09:28:03 +00:00
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/*
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* Negate DTR
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*/
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if(Console_Port_Tbl[minor].pDeviceFlow != &mc68681_flow_DTRCTS) {
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mc68681_negate_DTR(minor);
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}
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return(RTEMS_SUCCESSFUL);
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}
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/*
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* mc68681_write_polled
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*/
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1998-06-22 10:17:14 +00:00
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1998-06-22 09:28:03 +00:00
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static void mc68681_write_polled(
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int minor,
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char cChar
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)
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{
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unsigned32 pMC68681;
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unsigned char ucLineStatus;
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int iTimeout;
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getRegister_f getReg;
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1998-06-22 11:09:32 +00:00
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setData_f setData;
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1998-06-22 09:28:03 +00:00
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pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
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getReg = Console_Port_Tbl[minor].getRegister;
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1998-06-22 11:09:32 +00:00
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setData = Console_Port_Tbl[minor].setData;
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1998-06-22 09:28:03 +00:00
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/*
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* wait for transmitter holding register to be empty
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*/
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1998-06-22 11:09:32 +00:00
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iTimeout = 1000;
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ucLineStatus = (*getReg)(pMC68681, MC68681_STATUS_REG);
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while ((ucLineStatus & MC68681_TX_READY) == 0) {
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1998-06-22 09:28:03 +00:00
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/*
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* Yield while we wait
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*/
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1998-06-22 11:09:32 +00:00
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1998-06-22 09:28:03 +00:00
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if(_System_state_Is_up(_System_state_Get())) {
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rtems_task_wake_after(RTEMS_YIELD_PROCESSOR);
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}
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1998-06-22 11:09:32 +00:00
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ucLineStatus = (*getReg)(pMC68681, MC68681_STATUS_REG);
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1998-06-22 09:28:03 +00:00
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if(!--iTimeout) {
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break;
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}
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}
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/*
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* transmit character
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*/
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1998-06-22 11:09:32 +00:00
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(*setData)(pMC68681, cChar);
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1998-06-22 09:28:03 +00:00
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}
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/*
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* These routines provide control of the RTS and DTR lines
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*/
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1998-06-22 11:09:32 +00:00
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1998-06-22 09:28:03 +00:00
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/*
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* mc68681_assert_RTS
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*/
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1998-06-22 11:09:32 +00:00
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1998-06-22 09:28:03 +00:00
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static int mc68681_assert_RTS(int minor)
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{
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1998-06-22 11:09:32 +00:00
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/* XXX */
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1998-06-22 09:28:03 +00:00
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unsigned32 pMC68681;
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unsigned32 Irql;
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1998-06-22 11:09:32 +00:00
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mc68681_context *pmc68681Context;
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1998-06-22 09:28:03 +00:00
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setRegister_f setReg;
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1998-06-22 11:09:32 +00:00
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pmc68681Context = (mc68681_context *) Console_Port_Data[minor].pDeviceContext;
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1998-06-22 09:28:03 +00:00
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pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
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setReg = Console_Port_Tbl[minor].setRegister;
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/*
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* Assert RTS
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*/
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rtems_interrupt_disable(Irql);
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1998-06-22 11:09:32 +00:00
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#if 0
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pmc68681Context->ucModemCtrl |= SP_MODEM_RTS;
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(*setReg)(pMC68681, MC68681_MODEM_CONTROL, pmc68681Context->ucModemCtrl);
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#endif
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1998-06-22 09:28:03 +00:00
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rtems_interrupt_enable(Irql);
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return 0;
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}
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/*
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* mc68681_negate_RTS
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*/
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static int mc68681_negate_RTS(int minor)
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{
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1998-06-22 11:09:32 +00:00
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/* XXX */
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1998-06-22 09:28:03 +00:00
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unsigned32 pMC68681;
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unsigned32 Irql;
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1998-06-22 11:09:32 +00:00
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mc68681_context *pmc68681Context;
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1998-06-22 09:28:03 +00:00
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setRegister_f setReg;
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1998-06-22 11:09:32 +00:00
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pmc68681Context = (mc68681_context *) Console_Port_Data[minor].pDeviceContext;
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1998-06-22 09:28:03 +00:00
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pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
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setReg = Console_Port_Tbl[minor].setRegister;
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/*
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* Negate RTS
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*/
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rtems_interrupt_disable(Irql);
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1998-06-22 11:09:32 +00:00
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#if 0
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pmc68681Context->ucModemCtrl &= ~SP_MODEM_RTS;
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(*setReg)(pMC68681, MC68681_MODEM_CONTROL, pmc68681Context->ucModemCtrl);
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#endif
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1998-06-22 09:28:03 +00:00
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rtems_interrupt_enable(Irql);
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return 0;
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}
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/*
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* These flow control routines utilise a connection from the local DTR
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* line to the remote CTS line
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*/
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1998-06-22 11:09:32 +00:00
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1998-06-22 09:28:03 +00:00
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/*
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|
* mc68681_assert_DTR
|
|
|
|
|
*/
|
1998-06-22 11:09:32 +00:00
|
|
|
|
1998-06-22 09:28:03 +00:00
|
|
|
static int mc68681_assert_DTR(int minor)
|
|
|
|
|
{
|
1998-06-22 11:09:32 +00:00
|
|
|
/* XXX */
|
1998-06-22 09:28:03 +00:00
|
|
|
unsigned32 pMC68681;
|
|
|
|
|
unsigned32 Irql;
|
1998-06-22 11:09:32 +00:00
|
|
|
mc68681_context *pmc68681Context;
|
1998-06-22 09:28:03 +00:00
|
|
|
setRegister_f setReg;
|
|
|
|
|
|
1998-06-22 11:09:32 +00:00
|
|
|
pmc68681Context = (mc68681_context *) Console_Port_Data[minor].pDeviceContext;
|
1998-06-22 09:28:03 +00:00
|
|
|
|
|
|
|
|
pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
|
|
|
|
|
setReg = Console_Port_Tbl[minor].setRegister;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Assert DTR
|
|
|
|
|
*/
|
|
|
|
|
rtems_interrupt_disable(Irql);
|
1998-06-22 11:09:32 +00:00
|
|
|
#if 0
|
|
|
|
|
pmc68681Context->ucModemCtrl |= SP_MODEM_DTR;
|
|
|
|
|
(*setReg)(pMC68681, MC68681_MODEM_CONTROL, pmc68681Context->ucModemCtrl);
|
|
|
|
|
#endif
|
1998-06-22 09:28:03 +00:00
|
|
|
rtems_interrupt_enable(Irql);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* mc68681_negate_DTR
|
|
|
|
|
*/
|
1998-06-22 11:09:32 +00:00
|
|
|
|
1998-06-22 09:28:03 +00:00
|
|
|
static int mc68681_negate_DTR(int minor)
|
|
|
|
|
{
|
1998-06-22 11:09:32 +00:00
|
|
|
/* XXX */
|
1998-06-22 09:28:03 +00:00
|
|
|
unsigned32 pMC68681;
|
|
|
|
|
unsigned32 Irql;
|
1998-06-22 11:09:32 +00:00
|
|
|
mc68681_context *pmc68681Context;
|
1998-06-22 09:28:03 +00:00
|
|
|
setRegister_f setReg;
|
|
|
|
|
|
1998-06-22 11:09:32 +00:00
|
|
|
pmc68681Context = (mc68681_context *) Console_Port_Data[minor].pDeviceContext;
|
1998-06-22 09:28:03 +00:00
|
|
|
|
|
|
|
|
pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
|
|
|
|
|
setReg = Console_Port_Tbl[minor].setRegister;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Negate DTR
|
|
|
|
|
*/
|
|
|
|
|
rtems_interrupt_disable(Irql);
|
1998-06-22 11:09:32 +00:00
|
|
|
#if 0
|
|
|
|
|
pmc68681Context->ucModemCtrl &= ~SP_MODEM_DTR;
|
|
|
|
|
(*setReg)(pMC68681, MC68681_MODEM_CONTROL,pmc68681Context->ucModemCtrl);
|
|
|
|
|
#endif
|
1998-06-22 09:28:03 +00:00
|
|
|
rtems_interrupt_enable(Irql);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* mc68681_isr
|
|
|
|
|
*
|
1998-06-22 11:09:32 +00:00
|
|
|
* This routine is the console interrupt handler.
|
1998-06-22 09:28:03 +00:00
|
|
|
*
|
|
|
|
|
* Input parameters:
|
|
|
|
|
* vector - vector number
|
|
|
|
|
*
|
|
|
|
|
* Output parameters: NONE
|
|
|
|
|
*
|
|
|
|
|
* Return values: NONE
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
static void mc68681_process(
|
|
|
|
|
int minor
|
|
|
|
|
)
|
|
|
|
|
{
|
1998-06-22 11:09:32 +00:00
|
|
|
/* XXX */
|
1998-06-22 09:28:03 +00:00
|
|
|
unsigned32 pMC68681;
|
|
|
|
|
volatile unsigned8 ucLineStatus;
|
|
|
|
|
volatile unsigned8 ucInterruptId;
|
|
|
|
|
char cChar;
|
|
|
|
|
getRegister_f getReg;
|
|
|
|
|
setRegister_f setReg;
|
|
|
|
|
|
1998-06-22 11:09:32 +00:00
|
|
|
#if 1
|
|
|
|
|
cChar = ucInterruptId = ucLineStatus = 0;
|
|
|
|
|
#endif
|
1998-06-22 09:28:03 +00:00
|
|
|
pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
|
|
|
|
|
getReg = Console_Port_Tbl[minor].getRegister;
|
|
|
|
|
setReg = Console_Port_Tbl[minor].setRegister;
|
|
|
|
|
|
1998-06-22 11:09:32 +00:00
|
|
|
#if 0
|
1998-06-22 09:28:03 +00:00
|
|
|
do {
|
|
|
|
|
/*
|
|
|
|
|
* Deal with any received characters
|
|
|
|
|
*/
|
|
|
|
|
while(TRUE) {
|
1998-06-22 11:09:32 +00:00
|
|
|
ucLineStatus = (*getReg)(pMC68681, MC68681_LINE_STATUS);
|
1998-06-22 09:28:03 +00:00
|
|
|
if(~ucLineStatus & SP_LSR_RDY) {
|
|
|
|
|
break;
|
|
|
|
|
}
|
1998-06-22 11:09:32 +00:00
|
|
|
cChar = (*getReg)(pMC68681, MC68681_RECEIVE_BUFFER);
|
1998-06-22 09:28:03 +00:00
|
|
|
rtems_termios_enqueue_raw_characters(
|
|
|
|
|
Console_Port_Data[minor].termios_data,
|
|
|
|
|
&cChar,
|
|
|
|
|
1
|
|
|
|
|
);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
while(TRUE) {
|
|
|
|
|
if(Ring_buffer_Is_empty(&Console_Port_Data[minor].TxBuffer)) {
|
1998-06-22 11:09:32 +00:00
|
|
|
Console_Port_Data[minor].bActive = FALSE;
|
|
|
|
|
if(Console_Port_Tbl[minor].pDeviceFlow != &mc68681_flow_RTSCTS) {
|
1998-06-22 09:28:03 +00:00
|
|
|
mc68681_negate_RTS(minor);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* There is no data to transmit
|
|
|
|
|
*/
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
1998-06-22 11:09:32 +00:00
|
|
|
ucLineStatus = (*getReg)(pMC68681, MC68681_LINE_STATUS);
|
1998-06-22 09:28:03 +00:00
|
|
|
if(~ucLineStatus & SP_LSR_THOLD) {
|
|
|
|
|
/*
|
|
|
|
|
* We'll get another interrupt when
|
|
|
|
|
* the transmitter holding reg. becomes
|
|
|
|
|
* free again
|
|
|
|
|
*/
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
Ring_buffer_Remove_character( &Console_Port_Data[minor].TxBuffer, cChar);
|
|
|
|
|
/*
|
|
|
|
|
* transmit character
|
|
|
|
|
*/
|
1998-06-22 11:09:32 +00:00
|
|
|
(*setReg)(pMC68681, MC68681_TRANSMIT_BUFFER, cChar);
|
1998-06-22 09:28:03 +00:00
|
|
|
}
|
|
|
|
|
|
1998-06-22 11:09:32 +00:00
|
|
|
ucInterruptId = (*getReg)(pMC68681, MC68681_INTERRUPT_ID);
|
1998-06-22 09:28:03 +00:00
|
|
|
}
|
1998-06-22 11:09:32 +00:00
|
|
|
while((ucInterruptId&0xf) != 0x1);
|
|
|
|
|
#endif
|
1998-06-22 09:28:03 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static rtems_isr mc68681_isr(
|
|
|
|
|
rtems_vector_number vector
|
|
|
|
|
)
|
|
|
|
|
{
|
|
|
|
|
int minor;
|
|
|
|
|
|
1998-06-22 11:09:32 +00:00
|
|
|
for(minor=0 ; minor<Console_Port_Count ; minor++) {
|
|
|
|
|
if(vector == Console_Port_Tbl[minor].ulIntVector) {
|
1998-06-22 09:28:03 +00:00
|
|
|
mc68681_process(minor);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* mc68681_flush
|
|
|
|
|
*/
|
1998-06-22 11:09:32 +00:00
|
|
|
|
1998-06-22 09:28:03 +00:00
|
|
|
static int mc68681_flush(int major, int minor, void *arg)
|
|
|
|
|
{
|
|
|
|
|
while(!Ring_buffer_Is_empty(&Console_Port_Data[minor].TxBuffer)) {
|
|
|
|
|
/*
|
|
|
|
|
* Yield while we wait
|
|
|
|
|
*/
|
|
|
|
|
if(_System_state_Is_up(_System_state_Get())) {
|
|
|
|
|
rtems_task_wake_after(RTEMS_YIELD_PROCESSOR);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mc68681_close(major, minor, arg);
|
|
|
|
|
|
|
|
|
|
return(RTEMS_SUCCESSFUL);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* mc68681_initialize_interrupts
|
|
|
|
|
*
|
|
|
|
|
* This routine initializes the console's receive and transmit
|
|
|
|
|
* ring buffers and loads the appropriate vectors to handle the interrupts.
|
|
|
|
|
*
|
|
|
|
|
* Input parameters: NONE
|
|
|
|
|
*
|
|
|
|
|
* Output parameters: NONE
|
|
|
|
|
*
|
|
|
|
|
* Return values: NONE
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
static void mc68681_enable_interrupts(
|
|
|
|
|
int minor
|
|
|
|
|
)
|
|
|
|
|
{
|
1998-06-22 11:09:32 +00:00
|
|
|
/* XXX */
|
1998-06-22 09:28:03 +00:00
|
|
|
unsigned32 pMC68681;
|
|
|
|
|
unsigned8 ucDataByte;
|
1998-06-22 11:09:32 +00:00
|
|
|
setRegister_f setReg;
|
1998-06-22 09:28:03 +00:00
|
|
|
|
1998-06-22 11:09:32 +00:00
|
|
|
#if 1
|
|
|
|
|
ucDataByte = 0;
|
|
|
|
|
#endif
|
1998-06-22 09:28:03 +00:00
|
|
|
pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
|
|
|
|
|
setReg = Console_Port_Tbl[minor].setRegister;
|
|
|
|
|
|
1998-06-22 11:09:32 +00:00
|
|
|
#if 0
|
1998-06-22 09:28:03 +00:00
|
|
|
/*
|
|
|
|
|
* Enable interrupts
|
|
|
|
|
*/
|
|
|
|
|
ucDataByte = SP_INT_RX_ENABLE | SP_INT_TX_ENABLE;
|
1998-06-22 11:09:32 +00:00
|
|
|
(*setReg)(pMC68681, MC68681_INTERRUPT_ENABLE, ucDataByte);
|
|
|
|
|
#endif
|
1998-06-22 09:28:03 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mc68681_initialize_interrupts(int minor)
|
|
|
|
|
{
|
|
|
|
|
mc68681_init(minor);
|
|
|
|
|
|
|
|
|
|
Ring_buffer_Initialize(&Console_Port_Data[minor].TxBuffer);
|
|
|
|
|
|
|
|
|
|
Console_Port_Data[minor].bActive = FALSE;
|
|
|
|
|
|
|
|
|
|
set_vector(mc68681_isr, Console_Port_Tbl[minor].ulIntVector, 1);
|
|
|
|
|
|
|
|
|
|
mc68681_enable_interrupts(minor);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* mc68681_write_support_int
|
|
|
|
|
*
|
|
|
|
|
* Console Termios output entry point.
|
|
|
|
|
*/
|
1998-06-22 11:09:32 +00:00
|
|
|
|
1998-06-22 09:28:03 +00:00
|
|
|
static int mc68681_write_support_int(
|
|
|
|
|
int minor,
|
|
|
|
|
const char *buf,
|
|
|
|
|
int len
|
|
|
|
|
)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
unsigned32 Irql;
|
|
|
|
|
|
1998-06-22 11:09:32 +00:00
|
|
|
for(i=0 ; i<len ;) {
|
1998-06-22 09:28:03 +00:00
|
|
|
if(Ring_buffer_Is_full(&Console_Port_Data[minor].TxBuffer)) {
|
|
|
|
|
if(!Console_Port_Data[minor].bActive) {
|
|
|
|
|
/*
|
|
|
|
|
* Wake up the device
|
|
|
|
|
*/
|
|
|
|
|
rtems_interrupt_disable(Irql);
|
|
|
|
|
Console_Port_Data[minor].bActive = TRUE;
|
|
|
|
|
if(Console_Port_Tbl[minor].pDeviceFlow != &mc68681_flow_RTSCTS) {
|
|
|
|
|
mc68681_assert_RTS(minor);
|
|
|
|
|
}
|
|
|
|
|
mc68681_process(minor);
|
|
|
|
|
rtems_interrupt_enable(Irql);
|
|
|
|
|
} else {
|
|
|
|
|
/*
|
|
|
|
|
* Yield
|
|
|
|
|
*/
|
|
|
|
|
rtems_task_wake_after(RTEMS_YIELD_PROCESSOR);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Wait for ring buffer to empty
|
|
|
|
|
*/
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
else {
|
|
|
|
|
Ring_buffer_Add_character( &Console_Port_Data[minor].TxBuffer, buf[i]);
|
|
|
|
|
i++;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Ensure that characters are on the way
|
|
|
|
|
*/
|
1998-06-22 11:09:32 +00:00
|
|
|
|
1998-06-22 09:28:03 +00:00
|
|
|
if(!Console_Port_Data[minor].bActive) {
|
|
|
|
|
/*
|
|
|
|
|
* Wake up the device
|
|
|
|
|
*/
|
|
|
|
|
rtems_interrupt_disable(Irql);
|
|
|
|
|
Console_Port_Data[minor].bActive = TRUE;
|
1998-06-22 11:09:32 +00:00
|
|
|
if(Console_Port_Tbl[minor].pDeviceFlow != &mc68681_flow_RTSCTS) {
|
1998-06-22 09:28:03 +00:00
|
|
|
mc68681_assert_RTS(minor);
|
|
|
|
|
}
|
|
|
|
|
mc68681_process(minor);
|
|
|
|
|
rtems_interrupt_enable(Irql);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return (len);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* mc68681_write_support_polled
|
|
|
|
|
*
|
|
|
|
|
* Console Termios output entry point.
|
|
|
|
|
*
|
|
|
|
|
*/
|
1998-06-22 11:09:32 +00:00
|
|
|
|
1998-06-22 09:28:03 +00:00
|
|
|
static int mc68681_write_support_polled(
|
|
|
|
|
int minor,
|
|
|
|
|
const char *buf,
|
|
|
|
|
int len
|
|
|
|
|
)
|
|
|
|
|
{
|
|
|
|
|
int nwrite = 0;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* poll each byte in the string out of the port.
|
|
|
|
|
*/
|
|
|
|
|
while (nwrite < len) {
|
|
|
|
|
/*
|
|
|
|
|
* transmit character
|
|
|
|
|
*/
|
|
|
|
|
mc68681_write_polled(minor, *buf++);
|
|
|
|
|
nwrite++;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* return the number of bytes written.
|
|
|
|
|
*/
|
|
|
|
|
return nwrite;
|
|
|
|
|
}
|
|
|
|
|
|
|
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/*
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* mc68681_inbyte_nonblocking_polled
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*
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* Console Termios polling input entry point.
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*/
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static int mc68681_inbyte_nonblocking_polled(
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int minor
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)
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{
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unsigned32 pMC68681;
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unsigned char ucLineStatus;
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char cChar;
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getRegister_f getReg;
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1998-06-22 11:09:32 +00:00
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getData_f getData;
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1998-06-22 09:28:03 +00:00
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pMC68681 = Console_Port_Tbl[minor].ulCtrlPort1;
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getReg = Console_Port_Tbl[minor].getRegister;
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1998-06-22 11:09:32 +00:00
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getData = Console_Port_Tbl[minor].getData;
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1998-06-22 09:28:03 +00:00
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1998-06-22 11:09:32 +00:00
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ucLineStatus = (*getReg)(pMC68681, MC68681_STATUS_REG);
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if(ucLineStatus & MC68681_RX_READY) {
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cChar = (*getData)(pMC68681);
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return (int)cChar;
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1998-06-22 09:28:03 +00:00
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} else {
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return(-1);
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}
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}
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