mirror of
https://github.com/qmk/qmk_firmware.git
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61 lines
2.9 KiB
C
61 lines
2.9 KiB
C
/*
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Copyright 2019 Massdrop Inc.
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "arm_atsam_protocol.h"
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void SR_EXP_Init_kb(void) {
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/* Initialize shift register */
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SR_EXP_OE_N_DIS;
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SR_EXP_RCLK_HI;
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SR_EXP_SERCOM->SPI.CTRLA.bit.DORD = 1; //Data Order - LSB is transferred first
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SR_EXP_SERCOM->SPI.CTRLA.bit.CPOL = 1; //Clock Polarity - SCK high when idle. Leading edge of cycle is falling. Trailing rising.
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SR_EXP_SERCOM->SPI.CTRLA.bit.CPHA = 1; //Clock Phase - Leading Edge Falling, change, Trailing Edge - Rising, sample
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SR_EXP_SERCOM->SPI.CTRLA.bit.DIPO = 3; //Data In Pinout - SERCOM PAD[3] is used as data input (Configure away from DOPO. Not using input.)
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SR_EXP_SERCOM->SPI.CTRLA.bit.DOPO = 0; //Data Output PAD[0], Serial Clock PAD[1]
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SR_EXP_SERCOM->SPI.CTRLA.bit.MODE = 3; //Operating Mode - Master operation
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SR_EXP_SERCOM->SPI.CTRLA.bit.ENABLE = 1; //Enable - Peripheral is enabled or being enabled
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while (SR_EXP_SERCOM->SPI.SYNCBUSY.bit.ENABLE) { DBGC(DC_SPI_EXP_SYNC_ENABLING); }
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/* Set default shift register values */
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sr_exp_data.reg = 0; //Clear data register
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sr_exp_data.bit.HUB_CONNECT = 0; //USB Hub disconnected
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sr_exp_data.bit.HUB_RESET_N = 0; //USB Hub in reset state
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sr_exp_data.bit.SRC_1_A5 = 1; //Set CON1 CC A5 as Rd 5.1k
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sr_exp_data.bit.SRC_1_B5 = 1; //Set CON1 CC B5 as Rd 5.1k
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sr_exp_data.bit.SRC_2_A5 = 1; //Set CON2 CC A5 as Rd 5.1k
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sr_exp_data.bit.SRC_2_B5 = 1; //Set CON2 CC B5 as Rd 5.1k
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sr_exp_data.bit.S_A_UP = 0; //0 = DN1 to A and UP to B, 1 = DN1 to B and UP to A
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sr_exp_data.bit.S_A_EXT = 1; //0 = Onboard, 1 = Offboard
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sr_exp_data.bit.S_B_EXT = 0; //1 = Onboard, 0 = Offboard
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sr_exp_data.bit.ENB = 0; //Disable CON1
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sr_exp_data.bit.ENA = 0; //Disable CON2
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sr_exp_data.bit.E_VBUS_1 = 0; //Disable CON1 5V
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sr_exp_data.bit.E_VBUS_2 = 0; //Disable CON2 5V
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sr_exp_data.bit.IRST = 1; //LED drivers I2C in reset
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sr_exp_data.bit.SDB_N = 0; //LED drivers in shutdown
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/* Write shift register data */
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SR_EXP_WriteData();
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/* Enable shift register output */
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SR_EXP_OE_N_ENA;
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}
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